A low voltage cmos constant current-voltage ... - Semantic Scholar
A LOW VOLTAGE CMOS CONSTANT CURRENT-VOLTAGE REFERENCE CIRCUIT Ilkka Nissinen, Juha Kostamovaara University of Oulu, Department of Electrical and Information Engineering, Electronics Laboratory Linnanmaa, P.O.Box 4500, FIN-90014 University of Oulu, Finland ABSTRACT The proposed CMOS current-voltage reference circuit consists of a traditional bandgap circuit based on the use of PMOS transistors in weak inversion. Its current is stabilized by an on-chip resistor with positive temperature coefficient. The voltage reference is produced by compensating the positive temperature coefficient of a resistor by the negative temperature coefficient of the diode connected PMOS transistor by driving the constant current of the current reference through them. The simulated temperature coefficients of the voltage and the current were less than 85 ppm/°C and 54 ppm/°C, respectively, in the worst-case simulation over the temperature range of -10°C to 70°C without trimming, and the supply-voltage coefficient of the voltage and current were 0.16% over the supply voltage range of 1.1 V to 2.2 V.
The current reference generation is based on the traditional bandgap circuit, except that here PNP bipolar transistors are substituted by diode connected PMOS transistors and the current reference is realized by compensating the positive temperature performance of the on-chip, N diffusion resistor R1 and R2 by the negative temperature dependence of the node n1 and n2 [3]. The voltage reference is generated by compensating the negative temperature coefficient of the diode connected PMOS transistor M3 by the positive temperature coefficient of the N diffusion resistor Re.
1. INTRODUCTION A stable frequency-to-voltage converter needs both the constant current and the constant voltage to operate in a voltage reference locked oscillator circuit [1]. A stable voltage reference can be designed by using a conventional bandgap reference circuit [2] and a stable current reference is achieved by using a modified bandgap structure [3]. The disadvantages are that the size and the current consumption of the whole circuit increase. The aim of this work was to develop a reference circuit that contains both the current and voltage references in a compact way. An idea was to generate the constant current by using the modified bandgap structure and then use this current to generate a constant voltage reference. 2. THE CURRENT-VOLTAGE REFERENCE CIRCUIT The schematic diagram of the used current-voltage reference circuit is shown in figure 1. The circuit has two outputs Vref and Iref. The voltage Vref is the generated voltage reference and the current Iref is the mirrored, constant current reference. Both the current IVref and the Iref can be trimmed by using a bias net to reduce the effect of the variation of the process parameters.
;,(((
Figure 1. The schematic diagram of the current-voltage reference circuit. PMOS transistors are in weak inversion, so they can be analyzed as PNP bipolar transistors in the first order analysis. The drain current ID of the PMOS transistor can be expressed as [4]
ID =
⎛ VSG − Vth W K exp⎜ ⎜ n ⋅V L T ⎝
⎞ ⎟ ⎟ ⎠
(1)
where W/L is the width to length ratio of the transistor, K is a process parameter, VSG is the source to gate voltage, Vth is a threshold voltage of PMOS transistor, VT equals to kT/q and n is approximately 1.5. If VSG is solved from equation (1), VSG can be expressed as
,
⎛ I ⋅L⎞ VSG = ln⎜ D ⎟ ⋅ nVT + Vth ⎝ KW ⎠
(2)
,6&$6
and now the ∆VSG of the transistors of different W/L ratio can be expressed as ∆VSG = nVTln(N), where N is 8 in figure 1. The voltages of nodes 1 and 2 are kept on the same potential by an operational amplifier, so the currents through the equal resistors R1 and R2 are proportional to the VSG of M1. Now we get the equation for the reference current.
I1 = I 2 =
n ⋅ VT ln N VSG + R0 R1
kT0 (1 + α ⋅ ∆T ) q
(5)
where T0 is the nominal temperature, and ∆T = T – T0. Also VSG and R0 can be expressed as
VSG = VSG ,T 0 (1 − β ⋅ ∆T )
(6)
R0 = R0,T 0 (1 + γ ⋅ ∆T )
(7)
The ratio (r) of R1 to R0 can be chosen so that Iref is stabilized. In this case the ratio should be satisfied as
r=
β+γ ⋅ kT0 n ln( N ) α − γ qVSG ,T 0
(8)
and then the constant current is
I1 = I 2 =
1 R0,To
V ∂V = γR eT 0 − SGT 0 β ∂T I Vref
VSG ,T 0 ⎛ kT ⋅ ⎜⎜ n 0 ln( N ) + r ⎝ q
⎞ ⎟⎟ ⎠
(9)
(12)
∂V/∂T is zero, so ReT0 can be expressed as
ReT 0 =
(4)
In the first order analysis VT can be expressed as
VT =
and by differentiating this we derive
V SGT 0 β ⋅ I Vref γ
(13)
The resistor Rex is only used to choose the level of the reference voltage Vref [2]. The temperature drift of the reference voltage is proportional to the absolute value of resistor ReT0, but the process variation of the N diffusion resistor (±20%) is compensated for by the reference current variation, which is inversely proportional to the absolute value of the resistor R1 and R2. The variation of process parameters in different chips is the main error source in a reference circuit. This is usually compensated by trimming resistors in reference circuits. Here trimming is made by using bias net circuits for both voltage generation to minimize a drift and to set an absolute value and the current generation to set an absolute value. Figure 2 shows the schematic diagram of the bias net circuit. The output of the operational amplifier is connected to the bias nets and the out nets are connected to the nodes Vref and VIref shown in figure 1. The required current is chosen by a binary word (B0 – Bn). The widths of the bias transistors are shown in table 1. WV and WI are the widths of the transistors in Iref and Vref generation, respectively. The absolute value of Iref varies more than Vref by the absolute value of the resistors in different chips, wherefore Iref generation requires more transistors than Vref generation.
Iref can now be generated to the required level of the application by choosing the size of the bias net transistor shown in figure 2. The reference voltage Vref can be expressed as
V ref =
(
Rex ⋅ I Vref Re + V SG R e + R ex
)
(10)
The mirrored current IVref is also constant, so if the voltage Vref needs to be constant, too, the temperature drift of the VSG of the transistor M3 has to be compensated for by the drift of Re. This means that IVrefRe + VSG has to be constant as a function of temperature, so we can use (6) and (7) and write
V = I Vref R eT 0 (1 + γ ⋅ ∆T ) + V SGT 0 (1 − β ⋅ ∆T )
Figure 2. The schematic diagram of the bias net circuit. Table 1. The sizes of the bias transistors in the bias net circuit. M1
M2
M3
M4
M5
M6
M7
M8
M9
M
0.5 0.5
1 1
1 1
1 1
1 1
5 5
5 10
10 20
30
4 0
10
(11)
,
WV WI
550 540 530 Voltage (mV)
The circuit was simulated in the 0.18 µm CMOS process by Spectre. The circuit was simulated at 9 different corner points, which were the combinations of maximum, typical and minimum value of resistors and slow, typical and fast MOS parameters. These 9 simulations were made in the temperature range of -10ºC to 70ºC and in the supply voltage range of 1 V to 2.2 V with and without trimming. The supply voltage was set to 1.8 V in the temperature performance simulations. The temperature performance of the reference voltage at the different corner points without trimming is shown at the top of figure 4. Two worst-case parameter simulations are marked by a square and a triangle and the typical case parameter simulation by a rhombus. The temperature drifts were 6.6 ppm/ºC and 85 ppm/ºC in a typical and the worst-case parameter simulation, respectively, while the absolute variation was ±8.5%. The temperature performance of the reference current at the different corner points without trimming is shown at the bottom of figure 4. The middle line is the current drift of typical case parameters. Other lines show the worst drifts at different corner points. The temperature drift of a typical case was 11 ppm/ºC and both of the worst-case drifts were less than 54 ppm/ºC and the absolute variation stayed within ±30%. The temperature performance of the reference voltage and current at all different corner points with trimming the absolute value of the instants is shown from the top to the bottom in figure 5. The maximum temperature drifts of the reference voltage and current were 92 ppm/ºC and 53 ppm/ºC, respectively. The supply voltage performance of the reference voltage and current at all different corner points with trimming the absolute value of the references is shown from the top to the bottom in figure 6. The maximum voltage and current variations were 0.35% and 0.43%, respectively, for a supply voltage of 1 to 2.2 V. The maximum variations were discovered in the simulations of the slow MOS process parameters and those results can be seen in figure 6, where the lines have nonlinear points for a supply voltage of 1 to 1.2 V. The reason for those nonlinear points is that load transistors enter the edge of the triode region in the operational amplifier. The simulations also showed that the maximum voltage and current variations were 0.13% and 0.16%, respectively, for a supply voltage of 1.1 to 2.2 V. Temperature drift simulations were also made by using the supply voltage of 1 V, and then the maximum temperature drifts of the reference voltage and current were 94 ppm/ºC and 116 ppm/ºC, respectively. Using the supply voltage of 1.1 V maximum temperature drifts were the same as the drifts shown at the bottom in figure 5. The voltage reference simulation also showed that if the absolute value of the voltage were not critical in an
application such as a voltage reference locked oscillator circuit, the voltage reference could be trimmed so that the temperature drift is minimized. In that case the temperature drift of the voltage reference is less than 10 ppm/ºC at all different corner points. The current consumption of the circuit is approximately 160 µA. In comparison with the design made of two separate reference circuits in a similar manner, this design needs only approximately 60% of the current and area.
520 510 500 490 480 470 460 -10
10
30
50
70
10
30
50
70
20.5 19.5 Current (uA)
3. SIMULATION RESULTS
18.5 17.5 16.5 15.5 14.5 -10
Temperature (C)
Figure 4. The temperature performance of the voltage and current references at the different corner points. 4. CONCLUSIONS An integrated CMOS current-voltage reference circuit has been described. The current-voltage reference circuit has been simulated in the 0.18 µm CMOS process by Spectre. The current reference generation is based on diode connected PMOS transistors in weak inversion in the traditional bandgap circuit. The voltage reference is generated by using the constant reference current by compensating the negative temperature coefficient of the diode connected PMOS transistor by the positive temperature coefficient of the N diffusion resistor Re. This makes it possible to fabricate a reference circuit, where both the current and the voltage are generated by using
,
only one operational amplifier. This saves the current consumption and the used chip area of the circuit compared to the structure, where both the current and the voltage references are implemented by using conventional circuits. The simulated worst-case temperature drifts of the voltage and current references were 92 ppm/ºC and 53 ppm/ºC with trimming and 85 ppm/ºC and 54 ppm/ºC without trimming, respectively, in the temperature range of -10ºC to 70ºC, and the simulated worst-case supply voltage drifts of the voltage and current references were 0.13% and 0.16%, respectively, for a supply voltage of 1.1 to 2.2 V. The current consumption and the area of the design were also reduced by 40% as compared to the structure, where both the current and the voltage references are implemented by using conventional circuits.
505
Voltage (mV)
504.5 504 503.5 503 502.5 1
1.2
1.4
1.6
1.8
2
2.2
1
1.2
1.4
1.6
1.8
2
2.2
17.22 17.2
Current (uA)
506.5 506
Voltage (mV)
505.5 505 504.5
17.18 17.16 17.14 17.12 17.1
504
17.08
503.5 503
Supply voltage (V)
502.5
Figure 6. The supply voltage drifts of the voltage and current references at all different corner points.
502
Current (uA)
-10 17.23 17.22 17.21 17.2 17.19 17.18 17.17 17.16 17.15 17.14 17.13 17.12 -10
10
30
50
70
5. REFERENCES
10
30
50
70
Temperature (C)
Figure 5. The temperature drifts of the trimmed voltage and current references at all different corner points.
[1] A. Djemouai, M. Sawan, M. Slamani, “New Circuit Techniques based on a High performance Frequencyto-Voltage Converter.”,Proc. ICECS’99, pp. 13-16, 1999, Pafos, Cyprus. [2] K. Lasanen, V. Korkala, E. Räisänen-Ruotsalainen, and J. Kostamovaara, ”Design of a 1-V Low Power CMOS Bandgap Reference based on Resistive Subdivision.”, Proc. MWSCAS’02, pp. 564-567, 2002, Tulsa, Oklahoma, USA. [3] J. Chen and B Shi, “1V CMOS Current Reference with 50 ppm/°C Temperature Coefficient.”, Electronics letter 23rd january2003 Vol. 39 No. 2. [4] Paul R. Gray and Robert G. Meyer, “Analysis and Design of Analog Integrated Circuits”, 4th Edition, John Wiley & Sons Inc., 2000.
,
The current reference generation is based on the traditional bandgap circuit, except that here PNP bipolar transistors are substituted by diode connected PMOS transistors and the current reference is realized by compensating the positive temperature performance of the on-chip, N diffusion resistor R1 and R2 by the negative temperature dependence of the node n1 and n2 [3]. The voltage reference is generated by compensating the negative temperature coefficient of the diode connected PMOS transistor M3 by the positive temperature coefficient of the N diffusion resistor Re.
1. INTRODUCTION A stable frequency-to-voltage converter needs both the constant current and the constant voltage to operate in a voltage reference locked oscillator circuit [1]. A stable voltage reference can be designed by using a conventional bandgap reference circuit [2] and a stable current reference is achieved by using a modified bandgap structure [3]. The disadvantages are that the size and the current consumption of the whole circuit increase. The aim of this work was to develop a reference circuit that contains both the current and voltage references in a compact way. An idea was to generate the constant current by using the modified bandgap structure and then use this current to generate a constant voltage reference. 2. THE CURRENT-VOLTAGE REFERENCE CIRCUIT The schematic diagram of the used current-voltage reference circuit is shown in figure 1. The circuit has two outputs Vref and Iref. The voltage Vref is the generated voltage reference and the current Iref is the mirrored, constant current reference. Both the current IVref and the Iref can be trimmed by using a bias net to reduce the effect of the variation of the process parameters.
;,(((
Figure 1. The schematic diagram of the current-voltage reference circuit. PMOS transistors are in weak inversion, so they can be analyzed as PNP bipolar transistors in the first order analysis. The drain current ID of the PMOS transistor can be expressed as [4]
ID =
⎛ VSG − Vth W K exp⎜ ⎜ n ⋅V L T ⎝
⎞ ⎟ ⎟ ⎠
(1)
where W/L is the width to length ratio of the transistor, K is a process parameter, VSG is the source to gate voltage, Vth is a threshold voltage of PMOS transistor, VT equals to kT/q and n is approximately 1.5. If VSG is solved from equation (1), VSG can be expressed as
,
⎛ I ⋅L⎞ VSG = ln⎜ D ⎟ ⋅ nVT + Vth ⎝ KW ⎠
(2)
,6&$6
and now the ∆VSG of the transistors of different W/L ratio can be expressed as ∆VSG = nVTln(N), where N is 8 in figure 1. The voltages of nodes 1 and 2 are kept on the same potential by an operational amplifier, so the currents through the equal resistors R1 and R2 are proportional to the VSG of M1. Now we get the equation for the reference current.
I1 = I 2 =
n ⋅ VT ln N VSG + R0 R1
kT0 (1 + α ⋅ ∆T ) q
(5)
where T0 is the nominal temperature, and ∆T = T – T0. Also VSG and R0 can be expressed as
VSG = VSG ,T 0 (1 − β ⋅ ∆T )
(6)
R0 = R0,T 0 (1 + γ ⋅ ∆T )
(7)
The ratio (r) of R1 to R0 can be chosen so that Iref is stabilized. In this case the ratio should be satisfied as
r=
β+γ ⋅ kT0 n ln( N ) α − γ qVSG ,T 0
(8)
and then the constant current is
I1 = I 2 =
1 R0,To
V ∂V = γR eT 0 − SGT 0 β ∂T I Vref
VSG ,T 0 ⎛ kT ⋅ ⎜⎜ n 0 ln( N ) + r ⎝ q
⎞ ⎟⎟ ⎠
(9)
(12)
∂V/∂T is zero, so ReT0 can be expressed as
ReT 0 =
(4)
In the first order analysis VT can be expressed as
VT =
and by differentiating this we derive
V SGT 0 β ⋅ I Vref γ
(13)
The resistor Rex is only used to choose the level of the reference voltage Vref [2]. The temperature drift of the reference voltage is proportional to the absolute value of resistor ReT0, but the process variation of the N diffusion resistor (±20%) is compensated for by the reference current variation, which is inversely proportional to the absolute value of the resistor R1 and R2. The variation of process parameters in different chips is the main error source in a reference circuit. This is usually compensated by trimming resistors in reference circuits. Here trimming is made by using bias net circuits for both voltage generation to minimize a drift and to set an absolute value and the current generation to set an absolute value. Figure 2 shows the schematic diagram of the bias net circuit. The output of the operational amplifier is connected to the bias nets and the out nets are connected to the nodes Vref and VIref shown in figure 1. The required current is chosen by a binary word (B0 – Bn). The widths of the bias transistors are shown in table 1. WV and WI are the widths of the transistors in Iref and Vref generation, respectively. The absolute value of Iref varies more than Vref by the absolute value of the resistors in different chips, wherefore Iref generation requires more transistors than Vref generation.
Iref can now be generated to the required level of the application by choosing the size of the bias net transistor shown in figure 2. The reference voltage Vref can be expressed as
V ref =
(
Rex ⋅ I Vref Re + V SG R e + R ex
)
(10)
The mirrored current IVref is also constant, so if the voltage Vref needs to be constant, too, the temperature drift of the VSG of the transistor M3 has to be compensated for by the drift of Re. This means that IVrefRe + VSG has to be constant as a function of temperature, so we can use (6) and (7) and write
V = I Vref R eT 0 (1 + γ ⋅ ∆T ) + V SGT 0 (1 − β ⋅ ∆T )
Figure 2. The schematic diagram of the bias net circuit. Table 1. The sizes of the bias transistors in the bias net circuit. M1
M2
M3
M4
M5
M6
M7
M8
M9
M
0.5 0.5
1 1
1 1
1 1
1 1
5 5
5 10
10 20
30
4 0
10
(11)
,
WV WI
550 540 530 Voltage (mV)
The circuit was simulated in the 0.18 µm CMOS process by Spectre. The circuit was simulated at 9 different corner points, which were the combinations of maximum, typical and minimum value of resistors and slow, typical and fast MOS parameters. These 9 simulations were made in the temperature range of -10ºC to 70ºC and in the supply voltage range of 1 V to 2.2 V with and without trimming. The supply voltage was set to 1.8 V in the temperature performance simulations. The temperature performance of the reference voltage at the different corner points without trimming is shown at the top of figure 4. Two worst-case parameter simulations are marked by a square and a triangle and the typical case parameter simulation by a rhombus. The temperature drifts were 6.6 ppm/ºC and 85 ppm/ºC in a typical and the worst-case parameter simulation, respectively, while the absolute variation was ±8.5%. The temperature performance of the reference current at the different corner points without trimming is shown at the bottom of figure 4. The middle line is the current drift of typical case parameters. Other lines show the worst drifts at different corner points. The temperature drift of a typical case was 11 ppm/ºC and both of the worst-case drifts were less than 54 ppm/ºC and the absolute variation stayed within ±30%. The temperature performance of the reference voltage and current at all different corner points with trimming the absolute value of the instants is shown from the top to the bottom in figure 5. The maximum temperature drifts of the reference voltage and current were 92 ppm/ºC and 53 ppm/ºC, respectively. The supply voltage performance of the reference voltage and current at all different corner points with trimming the absolute value of the references is shown from the top to the bottom in figure 6. The maximum voltage and current variations were 0.35% and 0.43%, respectively, for a supply voltage of 1 to 2.2 V. The maximum variations were discovered in the simulations of the slow MOS process parameters and those results can be seen in figure 6, where the lines have nonlinear points for a supply voltage of 1 to 1.2 V. The reason for those nonlinear points is that load transistors enter the edge of the triode region in the operational amplifier. The simulations also showed that the maximum voltage and current variations were 0.13% and 0.16%, respectively, for a supply voltage of 1.1 to 2.2 V. Temperature drift simulations were also made by using the supply voltage of 1 V, and then the maximum temperature drifts of the reference voltage and current were 94 ppm/ºC and 116 ppm/ºC, respectively. Using the supply voltage of 1.1 V maximum temperature drifts were the same as the drifts shown at the bottom in figure 5. The voltage reference simulation also showed that if the absolute value of the voltage were not critical in an
application such as a voltage reference locked oscillator circuit, the voltage reference could be trimmed so that the temperature drift is minimized. In that case the temperature drift of the voltage reference is less than 10 ppm/ºC at all different corner points. The current consumption of the circuit is approximately 160 µA. In comparison with the design made of two separate reference circuits in a similar manner, this design needs only approximately 60% of the current and area.
520 510 500 490 480 470 460 -10
10
30
50
70
10
30
50
70
20.5 19.5 Current (uA)
3. SIMULATION RESULTS
18.5 17.5 16.5 15.5 14.5 -10
Temperature (C)
Figure 4. The temperature performance of the voltage and current references at the different corner points. 4. CONCLUSIONS An integrated CMOS current-voltage reference circuit has been described. The current-voltage reference circuit has been simulated in the 0.18 µm CMOS process by Spectre. The current reference generation is based on diode connected PMOS transistors in weak inversion in the traditional bandgap circuit. The voltage reference is generated by using the constant reference current by compensating the negative temperature coefficient of the diode connected PMOS transistor by the positive temperature coefficient of the N diffusion resistor Re. This makes it possible to fabricate a reference circuit, where both the current and the voltage are generated by using
,
only one operational amplifier. This saves the current consumption and the used chip area of the circuit compared to the structure, where both the current and the voltage references are implemented by using conventional circuits. The simulated worst-case temperature drifts of the voltage and current references were 92 ppm/ºC and 53 ppm/ºC with trimming and 85 ppm/ºC and 54 ppm/ºC without trimming, respectively, in the temperature range of -10ºC to 70ºC, and the simulated worst-case supply voltage drifts of the voltage and current references were 0.13% and 0.16%, respectively, for a supply voltage of 1.1 to 2.2 V. The current consumption and the area of the design were also reduced by 40% as compared to the structure, where both the current and the voltage references are implemented by using conventional circuits.
505
Voltage (mV)
504.5 504 503.5 503 502.5 1
1.2
1.4
1.6
1.8
2
2.2
1
1.2
1.4
1.6
1.8
2
2.2
17.22 17.2
Current (uA)
506.5 506
Voltage (mV)
505.5 505 504.5
17.18 17.16 17.14 17.12 17.1
504
17.08
503.5 503
Supply voltage (V)
502.5
Figure 6. The supply voltage drifts of the voltage and current references at all different corner points.
502
Current (uA)
-10 17.23 17.22 17.21 17.2 17.19 17.18 17.17 17.16 17.15 17.14 17.13 17.12 -10
10
30
50
70
5. REFERENCES
10
30
50
70
Temperature (C)
Figure 5. The temperature drifts of the trimmed voltage and current references at all different corner points.
[1] A. Djemouai, M. Sawan, M. Slamani, “New Circuit Techniques based on a High performance Frequencyto-Voltage Converter.”,Proc. ICECS’99, pp. 13-16, 1999, Pafos, Cyprus. [2] K. Lasanen, V. Korkala, E. Räisänen-Ruotsalainen, and J. Kostamovaara, ”Design of a 1-V Low Power CMOS Bandgap Reference based on Resistive Subdivision.”, Proc. MWSCAS’02, pp. 564-567, 2002, Tulsa, Oklahoma, USA. [3] J. Chen and B Shi, “1V CMOS Current Reference with 50 ppm/°C Temperature Coefficient.”, Electronics letter 23rd january2003 Vol. 39 No. 2. [4] Paul R. Gray and Robert G. Meyer, “Analysis and Design of Analog Integrated Circuits”, 4th Edition, John Wiley & Sons Inc., 2000.
,
