A Vertically Integrated Junctionless Nanowire Transistor
Supporting Information for:
A Vertically Integrated Junctionless Nanowire Transistor Byung-Hyun Lee a,b, Jae Hur a, Min-Ho Kang c, Tewook Bang a, Dae-Chul Ahn a, Dongil Lee a , Kwang-Hee Kim c, and Yang-Kyu Choi a* a
School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea
b
Memory Business, Samsung Electronics, San #16 Banwol-Dong, Hwasung-City, Gyeonggi-Do 18448, Republic of Korea
c
Department of Nano-process, National Nanofab Center (NNFC), 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea
Byung-Hyun Lee: [email protected] Jae Hur: [email protected] Min-Ho Kang: [email protected] Tewook Bang: [email protected] Dae-Chul Ahn: [email protected]
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Dongil Lee: [email protected] Kwang-Hee Kim: [email protected] Yang-Kyu Choi: [email protected] * Address correspondence to [email protected].
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Table of contents 1. Fabrication process 2. Optimization of the one-route all-dry etching process (ORADEP) 3. Experimental equipment 4. Flash memory operation 5. Promising approaches to improve the uniformity of the SiNWs in the ORADEP 6. 3-D simulation analysis on the correlation of the channel doping concentration and the channel thickness for the performance of the junctionless FET
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Supporting Information 1: Fabrication process The entire fabrication process of the vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is illustrated in Figure S1, where a boron-doped bulk silicon (bulk-Si) wafer was used as the substrate. Boron ions were implanted in the initially boron-doped bulk-Si wafer to block the unwanted leakage current that can flow along the bulk-Si substrate below the bottom of the 5-story nanowire channel. This implantation process is known as the channel stop implantation process. To form an n+-doped channel and an S/D simultaneously, phosphorous implantation without any masking area (blanket implantation) was carried out on a bulk-Si wafer followed by post annealing at 900 °C for 60 minutes. This postannealing has multiple purposes: (1) formation of the uniform doping profile; (2) dopant activation; and (3) repairing the possible damage by high-energy and heavy dose ion implantation. A high-density plasma (HDP) oxide, which serves as the hard mask (HM) to protect the target pattern (active region) during the etching process to carve the nanowire structure, was deposited by plasma-enhanced chemical vapor deposition (PECVD). The active region was defined on the HM by a krypton fluoride (KrF) laser-based photolithography and dry etching process. An optimized one-route all-dry etching process (ORADEP) was employed, resulting in stable formation of the vertically integrated multi-nanowire structure without stiction failure. To isolate the transistors, tetraethyl orthosilicate (TEOS) was deposited as an inter-layer dielectric (ILD) oxide by low-pressure chemical vapor deposition (LPCVD). Prior to the application of the direct chemical mechanical polishing (CMP) process for planarizing the ILD oxide, a negative photoresist (PR)-based photolithography process using the same active mask
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and a dry etching process were carried out to reduce the large difference in
height between the
active region with the nanowire patterns and the field region without the nanowire patterns. This height difference is 1.2 m due to the 5-story nanowire. Planarization of the remaining ILD oxide was then achieved by CMP. In the fabrication process for the VJ-FET, the significant height of the vertically integrated multi-nanowires makes the formation process of the gate electrode very difficult. The formation of a “trench hole” was employed to ease the formation of the gate electrode in this study. A photolithography process was performed to define the trench hole pattern on both sides of the nanowire. A dry etching process partially removed the ILD oxide insomuch that a 3-story nanowire was exposed, and a sequential wet etching process was conducted to merge the two trench holes located on either side of the nanowires, resulting in the release of the vertically integrated multi-nanowires from the covered ILD oxide. During the process to merge the trench holes, the dry etching and wet etching processes were carefully applied to keep the ILD oxide at a proper thickness on the bulk-Si substrate for channel-tochannel isolation. The ILD oxide remaining on the bulk-Si substrate plays an important role to block the leakage current path from the source (S) to the drain (D), which is similar to the role of the channel stop implantation process. The growth and deposition processes were done to form two types of gate dielectric: (1) a thermally grown gate oxide for a logic device and (2) oxide/nitride/oxide (ONO) gate dielectrics for flash nonvolatile memory (NVM), which are formed by the use of thermal growth and LPCVD, respectively. The doped poly-crystalline Si (poly-Si) for the gate electrode was deposited to fully wrap the SiNW with the gate dielectric, resulting in the completion of the gate-all-around (GAA) configuration. The poly-Si deposited by LPCVD was planarized by the subsequent CMP process.
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In this step, the conventional junction-embedded vertically integrated multi-nanowire FET (VM-FET) operated by inversion mode (IM) requires a thick mask layer to protect the channel region from the subsequent S/D implantation with high dose and high energy.1 As a result, the thick gate stack requires careful dry etching to minimize process-induced damage. In contrast, the fabrication of the VJ-FET without an S/D formation process simplifies the overall process. Furthermore, it does not require the formation of a gate spacer, which is necessary for the IM-FET. Therefore, gate patterning was easily accomplished using a conventional photolithography and dry etching process. Finally, a forming gas annealing (FGA) process was conducted to improve the interface quality of the Si-to-SiO2. Figure S2 shows the schematic of the fabricated VJ-FET. As shown in Figure S2, the gate channel length is defined not by the process to delineate the gate electrode but by the process to merge the two adjacent trench holes.
Figure S1. Schematic of the entire fabrication process of the VJ-FET. LTH is the length of the trench hole, which corresponds to the actual gate length.
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Figure S2. Schematic of the fabricated VJ-FET. In the schematic, LExG and LBG represent the length of the exposed gate and the buried gate (actual gate), respectively. LExG is defined during the formation of the trench hole, and LBG is determined during the formation of the actual gate electrode.
Supporting Information 2: Optimization of the one-route all-dry etching process (ORADEP) As described in the main body of the paper, one cycle of the one-route all-dry etching process (ORADEP) consists of two steps: (1) a C4F8-based polymer passivation process to protect the sidewalls of the SiNW and (2) an SF6-based isotropic dry etching process to carve and gradually separate the vertically adjacent SiNWs. The iteration of the cycle allows the vertical integration of the nanowire, as shown in Figure S3.
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Figure S3. The number of nanowires corresponds to the number of etching cycles during the ORADEP. In the optimized ORADEP, the number of vertically integrated nanowires is equal to the number of cycles. However, a non-optimized ORADEP results in an abnormal SiNW shape. The ORADEP should therefore be optimized by controlling a few critical parameters such as the passivation time, etching time, plasma power, and amount of gas flow. Figure S4 shows scanning electron microscope (SEM) images of failed nanowires induced by a mismatch of the parameters during the ORADEP. Broken nanowires mainly resulted from excessive isotropic dry etching or insufficient polymer passivation, while non-separated nanowires were primarily caused by the opposite conditions, i.e., insufficient isotropic dry etching or excessive polymer passivation. Unformed nanowires result when extreme conditions of non-separated nanowires are applied.
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Figure S4. SEM images of the failed nanowire induced by the mismatch of the critical parameters in the ORADEP. (a) Broken nanowires. (b) Non-separated nanowires. (c) Unformed nanowires.
Figure S5. Optimized condition of the ORADEP.
Supporting Information 3: Experimental equipment
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All fabrication processes were done in the National Nanofab Center (NNFC) sponsored by the government (Republic of Korea). The equipment for the major fabrication processes is listed with the format of ‘Vendor, Model’ as follows: 1. Photolithography process : Nikon, NSR-S203B (KrF Scanner) 2. Oxide dry etching process : Lam Research, TCP9400DFM 3. One-route all-dry etching process for Si : Alcatel, AMS2000 4. Thermal oxidation and LPCVD process : CENTROTHERM, E1200 5. Deposition of HDP oxide: Novellus, ConceptⅡ-SPEED 6. CMP process : Doosan DND, UNIPLATM 231 7. Implantation process : DIM20, Excelis 8. RTA and FGA process : Metron, AG Heatpulse 8800 9. Wet etching and cleaning process : HIT, NXWET 10. Monitoring thickness of the layers : KLA-Tencor, SFX100 11. Monitoring critical dimension of each pattern : Hitachi, S-9260A
An SEM (S-4800) and transmission electron microscope (TEM, JEM-ARM200F) were used to analyze cross-sectional images of the multi-nanowire structure. The focused ion beam (FIB, Helios Nanolab) process to prepare the sample for the TEM analyses was carried out after the passivation of the silicon nitride deposited by plasma-enhanced chemical vapor deposition (PECVD). A fast Fourier transform (FFT) analysis to confirm the crystallinity of each layer was simultaneously conducted during the in situ TEM analyses. The clear identification of each layer was achieved with the aid of energy-dispersive X-ray spectroscopy (EDS, Quantax 400). Secondary ion mass spectrometry (SIMS, IMS7f) was used to analyze the doping profile. The current-voltage (I-V) characteristics were measured using an HP4156 semiconductor parameter
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analyzer. The memory function and reliability results were obtained from the HP4156 and a pulse generator (Agilent 81110A), respectively.
Supporting Information 4: Flash memory operation As shown in Figure S6, a large programming window above 5 V, referring to the difference in the threshold voltage (VT) before and after programming, is achieved from the VJFET for flash nonvolatile memory without degradation of the subthreshold slope (SS). The viability of the multi-level cell (MLC) operation of the device is demonstrated in Figure S6. That is, each programming voltage leads to a reproducible change in the VT, enabling various memory states.
Figure S6. Memory window for the programming and erasing operation, where VPGM and VERS are the gate biases for the programming and erasing operations, respectively. A high memory window of 5 V was obtained from the device, which is suitable for MLC operation.
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Supporting Information 5: Promising approaches to improve the uniformity of the SiNWs in the ORADEP A scalloped sidewall profile, which is patterned using the time-multiplexed Bosch plasma etch process based on SF6 for isotropic dry etching and C4F8 for sidewall passivation,2-5 is attractive for the formation of suspended nanowires. Moreover, owing to the process simplicity compared to the previous results, it is very suitable for the vertical stacking of the nanowire channels, which eventually permits the creation of the VM-FET with the aid of the ORADEP. The shape of the nanowires is mainly determined by the scalloped shape. Therefore, to obtain the customized shape of the scallops, many process parameters including pulse time, source power, substrate bias, plasma pressure, and substrate temperature should be optimized, where a balance between the etching and the passivation process is considerably crucial. In addition, to overcome the drawbacks of the time-multiplexed etch process and ensure the consistency and reproducibility of the sizes of each nanowire, promising approaches can be suggested as follows:2-5 First, one of the most important considerations for the formation of multi-nanowires with higher uniformity is the strict isolation of each process cycle. That is, the preformed silicon nanowires should not be influenced by the subsequent cycle. The etch damage of the preformed nanowire with sidewall passivation should be especially minimized in the subsequent SF6-based isotropic dry etch. In this regard, an SF6/Ar or SF6/O2-based anisotropic polymer-etching step embedded between the passivation in C4F8 plasma and the isotropic etching in SF6 plasma can be a good suggestion. It is expected that the embedded step would alleviate the etch damage of the
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preformed nanowire through the reduction of the etching time owing to the fast formation of the nanowire. Figure S7 shows such a process sequence. Second, for a balance of the vertical and lateral etch rates, the etching and passivation cycles in this work were maintained for only a few seconds, generally 1-3 seconds. The short cycle time causes some overlap of the two gases, i.e., SF6 and C4F8, with consequent mixing during the step transition. This problem can give rise to the variation of the sidewall scallop profiles, disrupting the clear isotropic dry etch and sidewall passivation. To solve this problem, inserting an “exhaust step” between the etching and passivation steps can be helpful by raising the accuracy of the etch and passivation processes, resulting in an improved controllability and uniformity of the nanowires. Third, as the etching depth or aspect ratio increases, the transport of reactive etch species, e.g., F radicals and ions, to the bottom of the trenches and the removal of the etch byproducts from the trenches become increasingly more difficult. This undesirable condition may be a severe obstacle for clear patterning. Therefore, the ion energy compensation method, which means an optimum control of the bias power or DC bias voltage for target depth, can be suggested for improving the uniformity and profile of the nanowire.
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Figure S7. (a) Current ORADEP. (b) ORADEP including an anisotropic dry etching process between the polymer passivation and isotropic dry etching processes. Due to the insertion of this process, the etch damage of the preformed nanowire can be alleviated via the faster formation of the nanowire, which can contribute to the uniform formation of each nanowire.
Supporting Information 6: 3-D Simulation analysis on the correlation of the channel doping concentration and the channel thickness for the performance of the junctionless FET A higher doping concentration (Nch) can improve the on current (Ion) thanks to the large amount of mobile carriers devoted to the total ION. When the Nch value, however, exceeds a critical point where full depletion of the channel does not occur with a small gate voltage near 0 V, the junctionless FET (JL-FET) would suffer from the feasibility of logic device applications due to their significantly large threshold voltage (VTH). To analyze the influence of Nch and the thickness of the SiNW (TSi) on the performance of the JL-FET, simulation works were conducted with the aid of the 3-dimensional SILVACO Atlas device simulator using the Lombardi mobility model along with the Shockley-Read-Hall model.6 Figure S8 (a) shows the transfer characteristic of the simulated device. Herein, the VTH values are concerned with the off-state characteristics because they represent the point at which the devices are turned off. The VTH values are extracted by the constant method,7 where the drain current is 10-7 A, as shown Figure S8 (b). It can be found that the VTH values abruptly decrease when the Nch value exceeds 1019 cm-3, meaning that the variabilities of the JL-FET become difficult to control at the off-state. The off current (Ioff, extracted at the gate voltage of VTH - 0.3 V) for the simulated devices is shown in Figure S8 (c).
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The Ioff slightly increases with respect to the increment of the Nch due to a small change in the subthreshold slope, but it maintained a very small value by virtue of the GAA structure with its excellent gate controllability. The on current (Ion, extracted at the gate voltage of VTH + 1 V) for the simulated devices is shown in Figure S8 (d). The Ion is considerably small when the Nch of the device is on the order of magnitude of 1018 cm-3, whereas devices with an Nch value of approximately 1019 cm-3 show greatly increased Ion. With respect to the simulated results from the above curves, it can be deduced that the JL-FET can be well-controlled within the values of 5x1018 cm-3≤ Nch ≤3x1019 cm-3 that are commonly used in many reported works.8-12 This specification can be varied according to how the devices are designed. There is a similar concern related to the TSi. The transfer curves of the simulated device are shown in Figure S9 (a). VTH and Ion linearly vary with respect to the TSi values, as shown in Figure S9 (b). Figure S9 (c) shows Ioff, which is extracted at VG = VTH - 0.3 V for the different TSi values. Ioff was very small at a TSi of 20 nm, abruptly increasing when TSi reaches 25 nm due to the failure of the device to be in the full-depletion mode in the off-state. Ioff becomes more nonnegligible when TSi exceeds 25 nm (not shown due to the finite mesh density13). Thus, it is important that TSi should be kept within the acceptable off-current range, which can be varied according to how the devices are designed. To keep Ioff at its smallest value, it is necessary to keep the low TSi whose Ion can be compensated by stacking more nanowires in the vertically stacked nanowire FET structures. Although the combination of the GAA structure and JL mode has various advantages in relation to the effective suppression of the short channel effects (SCEs) and process simplicity, the combination inevitably requires the proper compromise between high-performance and low
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power consumption mentioned above. In this regard, the suggested VJ-FET can be a good approach for versatile CMOS design with high Ion and low Ioff.
Figure S8. 3-D Simulation results. (a) Transfer characteristic (ID-VG) of the simulated device. (b) Variation of VTH as a function of Nch. (c) Variation of Ioff as a function of Nch. (d) Variation of Ion as a function of Nch.
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Figure S9. 3-D Simulation results. (a) Transfer characteristic of the simulated device with proper Nch (as extracted from Figure S8). (b) Variation of Ion and VTH as a function of Nch. (c) Variation of Ioff as a function of Nch.
Reference 1.
Lee, B.-H.; Kang, M.-H.; Ahn, D. C.; Park, J.-Y.; Bang, T.; Jeon, S.-B.; Hur, J.; Lee, D.; Choi, Y.-K. Nano Lett. 2015, 15, 8056–8061.
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Wu, B; Kumar, A; Pamarthy, S. Appl. Phys. Lett. 2010, 108, 051101
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Lai, S. L.; Johnson, D.; Westerman, R. J. Vac. Sci. Technol., A, 2004, 23, 905–9105.
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ATLAS User’s Manual; SILVACO Inc.; Santa Clara, CA 2008.
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Ortiz-Conde, A.; Garcia Sanchez, F. J.; Liou, J. J.; Cerdeira, A.; Estrada, M.; Yue, Y. Microelectron. Reliab. 2002, 42, 583–596.
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Colinge, J.-P.; Lee, C.-W.; Afzalian, A.; Akhavan, N. D.; Yan, R.; Ferain, I.; Razavi, P.; O'Neill, B.; Blake, A.; White, M.; Kelleher, A.-M.; McCarthy, B.; Murphy, R. Nature Nanotechnol. 2010, 5, 225—229.
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Colinge, J.-P.; Kranti, A.; Yan, R.; Lee, C.-W.; Ferain, I.; Yu, R.; Dehdashti, A.; Razavi, P. Solid-State Electron. 2011, 66, 33–37.
10. Cho, S.; Kim, K. R.; Park, B.-G.; Kang, I. M. IEEE T. Electron. Dev. 2011, 58, 1388–1396. 11. Ghosh, D.; Parihar, M. S.; Armstrong, G. A.; Kranti, A. IEEE Electr. Device L. 2012, 33, 1477–1479. 12. Lee, C.-W.; Ferain, I.; Afzalian, A.; Yan, R.; Akhavan, N. D.; Razavi, P.; Colinge, J.-P. Solid-State Electron. 2010, 54, 97–103. 13. Duarte, J. P.; Choi, S.-J.; Moon D.-I.; Ahn J.-H.; Kim, J.-Y.; Kim S.; Choi, Y.-K. IEEE T. Electron. Dev. 2013, 60, 848–855.
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A Vertically Integrated Junctionless Nanowire Transistor Byung-Hyun Lee a,b, Jae Hur a, Min-Ho Kang c, Tewook Bang a, Dae-Chul Ahn a, Dongil Lee a , Kwang-Hee Kim c, and Yang-Kyu Choi a* a
School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea
b
Memory Business, Samsung Electronics, San #16 Banwol-Dong, Hwasung-City, Gyeonggi-Do 18448, Republic of Korea
c
Department of Nano-process, National Nanofab Center (NNFC), 291 Daehak-ro, Yuseong-gu, Daejeon 34141, Republic of Korea
Byung-Hyun Lee: [email protected] Jae Hur: [email protected] Min-Ho Kang: [email protected] Tewook Bang: [email protected] Dae-Chul Ahn: [email protected]
1
Dongil Lee: [email protected] Kwang-Hee Kim: [email protected] Yang-Kyu Choi: [email protected] * Address correspondence to [email protected].
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Table of contents 1. Fabrication process 2. Optimization of the one-route all-dry etching process (ORADEP) 3. Experimental equipment 4. Flash memory operation 5. Promising approaches to improve the uniformity of the SiNWs in the ORADEP 6. 3-D simulation analysis on the correlation of the channel doping concentration and the channel thickness for the performance of the junctionless FET
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Supporting Information 1: Fabrication process The entire fabrication process of the vertically integrated junctionless field-effect transistor (VJ-FET), which is composed of vertically stacked multiple silicon nanowires (SiNWs) with a gate-all-around (GAA) structure, is illustrated in Figure S1, where a boron-doped bulk silicon (bulk-Si) wafer was used as the substrate. Boron ions were implanted in the initially boron-doped bulk-Si wafer to block the unwanted leakage current that can flow along the bulk-Si substrate below the bottom of the 5-story nanowire channel. This implantation process is known as the channel stop implantation process. To form an n+-doped channel and an S/D simultaneously, phosphorous implantation without any masking area (blanket implantation) was carried out on a bulk-Si wafer followed by post annealing at 900 °C for 60 minutes. This postannealing has multiple purposes: (1) formation of the uniform doping profile; (2) dopant activation; and (3) repairing the possible damage by high-energy and heavy dose ion implantation. A high-density plasma (HDP) oxide, which serves as the hard mask (HM) to protect the target pattern (active region) during the etching process to carve the nanowire structure, was deposited by plasma-enhanced chemical vapor deposition (PECVD). The active region was defined on the HM by a krypton fluoride (KrF) laser-based photolithography and dry etching process. An optimized one-route all-dry etching process (ORADEP) was employed, resulting in stable formation of the vertically integrated multi-nanowire structure without stiction failure. To isolate the transistors, tetraethyl orthosilicate (TEOS) was deposited as an inter-layer dielectric (ILD) oxide by low-pressure chemical vapor deposition (LPCVD). Prior to the application of the direct chemical mechanical polishing (CMP) process for planarizing the ILD oxide, a negative photoresist (PR)-based photolithography process using the same active mask
4
and a dry etching process were carried out to reduce the large difference in
height between the
active region with the nanowire patterns and the field region without the nanowire patterns. This height difference is 1.2 m due to the 5-story nanowire. Planarization of the remaining ILD oxide was then achieved by CMP. In the fabrication process for the VJ-FET, the significant height of the vertically integrated multi-nanowires makes the formation process of the gate electrode very difficult. The formation of a “trench hole” was employed to ease the formation of the gate electrode in this study. A photolithography process was performed to define the trench hole pattern on both sides of the nanowire. A dry etching process partially removed the ILD oxide insomuch that a 3-story nanowire was exposed, and a sequential wet etching process was conducted to merge the two trench holes located on either side of the nanowires, resulting in the release of the vertically integrated multi-nanowires from the covered ILD oxide. During the process to merge the trench holes, the dry etching and wet etching processes were carefully applied to keep the ILD oxide at a proper thickness on the bulk-Si substrate for channel-tochannel isolation. The ILD oxide remaining on the bulk-Si substrate plays an important role to block the leakage current path from the source (S) to the drain (D), which is similar to the role of the channel stop implantation process. The growth and deposition processes were done to form two types of gate dielectric: (1) a thermally grown gate oxide for a logic device and (2) oxide/nitride/oxide (ONO) gate dielectrics for flash nonvolatile memory (NVM), which are formed by the use of thermal growth and LPCVD, respectively. The doped poly-crystalline Si (poly-Si) for the gate electrode was deposited to fully wrap the SiNW with the gate dielectric, resulting in the completion of the gate-all-around (GAA) configuration. The poly-Si deposited by LPCVD was planarized by the subsequent CMP process.
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In this step, the conventional junction-embedded vertically integrated multi-nanowire FET (VM-FET) operated by inversion mode (IM) requires a thick mask layer to protect the channel region from the subsequent S/D implantation with high dose and high energy.1 As a result, the thick gate stack requires careful dry etching to minimize process-induced damage. In contrast, the fabrication of the VJ-FET without an S/D formation process simplifies the overall process. Furthermore, it does not require the formation of a gate spacer, which is necessary for the IM-FET. Therefore, gate patterning was easily accomplished using a conventional photolithography and dry etching process. Finally, a forming gas annealing (FGA) process was conducted to improve the interface quality of the Si-to-SiO2. Figure S2 shows the schematic of the fabricated VJ-FET. As shown in Figure S2, the gate channel length is defined not by the process to delineate the gate electrode but by the process to merge the two adjacent trench holes.
Figure S1. Schematic of the entire fabrication process of the VJ-FET. LTH is the length of the trench hole, which corresponds to the actual gate length.
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Figure S2. Schematic of the fabricated VJ-FET. In the schematic, LExG and LBG represent the length of the exposed gate and the buried gate (actual gate), respectively. LExG is defined during the formation of the trench hole, and LBG is determined during the formation of the actual gate electrode.
Supporting Information 2: Optimization of the one-route all-dry etching process (ORADEP) As described in the main body of the paper, one cycle of the one-route all-dry etching process (ORADEP) consists of two steps: (1) a C4F8-based polymer passivation process to protect the sidewalls of the SiNW and (2) an SF6-based isotropic dry etching process to carve and gradually separate the vertically adjacent SiNWs. The iteration of the cycle allows the vertical integration of the nanowire, as shown in Figure S3.
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Figure S3. The number of nanowires corresponds to the number of etching cycles during the ORADEP. In the optimized ORADEP, the number of vertically integrated nanowires is equal to the number of cycles. However, a non-optimized ORADEP results in an abnormal SiNW shape. The ORADEP should therefore be optimized by controlling a few critical parameters such as the passivation time, etching time, plasma power, and amount of gas flow. Figure S4 shows scanning electron microscope (SEM) images of failed nanowires induced by a mismatch of the parameters during the ORADEP. Broken nanowires mainly resulted from excessive isotropic dry etching or insufficient polymer passivation, while non-separated nanowires were primarily caused by the opposite conditions, i.e., insufficient isotropic dry etching or excessive polymer passivation. Unformed nanowires result when extreme conditions of non-separated nanowires are applied.
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Figure S4. SEM images of the failed nanowire induced by the mismatch of the critical parameters in the ORADEP. (a) Broken nanowires. (b) Non-separated nanowires. (c) Unformed nanowires.
Figure S5. Optimized condition of the ORADEP.
Supporting Information 3: Experimental equipment
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All fabrication processes were done in the National Nanofab Center (NNFC) sponsored by the government (Republic of Korea). The equipment for the major fabrication processes is listed with the format of ‘Vendor, Model’ as follows: 1. Photolithography process : Nikon, NSR-S203B (KrF Scanner) 2. Oxide dry etching process : Lam Research, TCP9400DFM 3. One-route all-dry etching process for Si : Alcatel, AMS2000 4. Thermal oxidation and LPCVD process : CENTROTHERM, E1200 5. Deposition of HDP oxide: Novellus, ConceptⅡ-SPEED 6. CMP process : Doosan DND, UNIPLATM 231 7. Implantation process : DIM20, Excelis 8. RTA and FGA process : Metron, AG Heatpulse 8800 9. Wet etching and cleaning process : HIT, NXWET 10. Monitoring thickness of the layers : KLA-Tencor, SFX100 11. Monitoring critical dimension of each pattern : Hitachi, S-9260A
An SEM (S-4800) and transmission electron microscope (TEM, JEM-ARM200F) were used to analyze cross-sectional images of the multi-nanowire structure. The focused ion beam (FIB, Helios Nanolab) process to prepare the sample for the TEM analyses was carried out after the passivation of the silicon nitride deposited by plasma-enhanced chemical vapor deposition (PECVD). A fast Fourier transform (FFT) analysis to confirm the crystallinity of each layer was simultaneously conducted during the in situ TEM analyses. The clear identification of each layer was achieved with the aid of energy-dispersive X-ray spectroscopy (EDS, Quantax 400). Secondary ion mass spectrometry (SIMS, IMS7f) was used to analyze the doping profile. The current-voltage (I-V) characteristics were measured using an HP4156 semiconductor parameter
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analyzer. The memory function and reliability results were obtained from the HP4156 and a pulse generator (Agilent 81110A), respectively.
Supporting Information 4: Flash memory operation As shown in Figure S6, a large programming window above 5 V, referring to the difference in the threshold voltage (VT) before and after programming, is achieved from the VJFET for flash nonvolatile memory without degradation of the subthreshold slope (SS). The viability of the multi-level cell (MLC) operation of the device is demonstrated in Figure S6. That is, each programming voltage leads to a reproducible change in the VT, enabling various memory states.
Figure S6. Memory window for the programming and erasing operation, where VPGM and VERS are the gate biases for the programming and erasing operations, respectively. A high memory window of 5 V was obtained from the device, which is suitable for MLC operation.
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Supporting Information 5: Promising approaches to improve the uniformity of the SiNWs in the ORADEP A scalloped sidewall profile, which is patterned using the time-multiplexed Bosch plasma etch process based on SF6 for isotropic dry etching and C4F8 for sidewall passivation,2-5 is attractive for the formation of suspended nanowires. Moreover, owing to the process simplicity compared to the previous results, it is very suitable for the vertical stacking of the nanowire channels, which eventually permits the creation of the VM-FET with the aid of the ORADEP. The shape of the nanowires is mainly determined by the scalloped shape. Therefore, to obtain the customized shape of the scallops, many process parameters including pulse time, source power, substrate bias, plasma pressure, and substrate temperature should be optimized, where a balance between the etching and the passivation process is considerably crucial. In addition, to overcome the drawbacks of the time-multiplexed etch process and ensure the consistency and reproducibility of the sizes of each nanowire, promising approaches can be suggested as follows:2-5 First, one of the most important considerations for the formation of multi-nanowires with higher uniformity is the strict isolation of each process cycle. That is, the preformed silicon nanowires should not be influenced by the subsequent cycle. The etch damage of the preformed nanowire with sidewall passivation should be especially minimized in the subsequent SF6-based isotropic dry etch. In this regard, an SF6/Ar or SF6/O2-based anisotropic polymer-etching step embedded between the passivation in C4F8 plasma and the isotropic etching in SF6 plasma can be a good suggestion. It is expected that the embedded step would alleviate the etch damage of the
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preformed nanowire through the reduction of the etching time owing to the fast formation of the nanowire. Figure S7 shows such a process sequence. Second, for a balance of the vertical and lateral etch rates, the etching and passivation cycles in this work were maintained for only a few seconds, generally 1-3 seconds. The short cycle time causes some overlap of the two gases, i.e., SF6 and C4F8, with consequent mixing during the step transition. This problem can give rise to the variation of the sidewall scallop profiles, disrupting the clear isotropic dry etch and sidewall passivation. To solve this problem, inserting an “exhaust step” between the etching and passivation steps can be helpful by raising the accuracy of the etch and passivation processes, resulting in an improved controllability and uniformity of the nanowires. Third, as the etching depth or aspect ratio increases, the transport of reactive etch species, e.g., F radicals and ions, to the bottom of the trenches and the removal of the etch byproducts from the trenches become increasingly more difficult. This undesirable condition may be a severe obstacle for clear patterning. Therefore, the ion energy compensation method, which means an optimum control of the bias power or DC bias voltage for target depth, can be suggested for improving the uniformity and profile of the nanowire.
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Figure S7. (a) Current ORADEP. (b) ORADEP including an anisotropic dry etching process between the polymer passivation and isotropic dry etching processes. Due to the insertion of this process, the etch damage of the preformed nanowire can be alleviated via the faster formation of the nanowire, which can contribute to the uniform formation of each nanowire.
Supporting Information 6: 3-D Simulation analysis on the correlation of the channel doping concentration and the channel thickness for the performance of the junctionless FET A higher doping concentration (Nch) can improve the on current (Ion) thanks to the large amount of mobile carriers devoted to the total ION. When the Nch value, however, exceeds a critical point where full depletion of the channel does not occur with a small gate voltage near 0 V, the junctionless FET (JL-FET) would suffer from the feasibility of logic device applications due to their significantly large threshold voltage (VTH). To analyze the influence of Nch and the thickness of the SiNW (TSi) on the performance of the JL-FET, simulation works were conducted with the aid of the 3-dimensional SILVACO Atlas device simulator using the Lombardi mobility model along with the Shockley-Read-Hall model.6 Figure S8 (a) shows the transfer characteristic of the simulated device. Herein, the VTH values are concerned with the off-state characteristics because they represent the point at which the devices are turned off. The VTH values are extracted by the constant method,7 where the drain current is 10-7 A, as shown Figure S8 (b). It can be found that the VTH values abruptly decrease when the Nch value exceeds 1019 cm-3, meaning that the variabilities of the JL-FET become difficult to control at the off-state. The off current (Ioff, extracted at the gate voltage of VTH - 0.3 V) for the simulated devices is shown in Figure S8 (c).
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The Ioff slightly increases with respect to the increment of the Nch due to a small change in the subthreshold slope, but it maintained a very small value by virtue of the GAA structure with its excellent gate controllability. The on current (Ion, extracted at the gate voltage of VTH + 1 V) for the simulated devices is shown in Figure S8 (d). The Ion is considerably small when the Nch of the device is on the order of magnitude of 1018 cm-3, whereas devices with an Nch value of approximately 1019 cm-3 show greatly increased Ion. With respect to the simulated results from the above curves, it can be deduced that the JL-FET can be well-controlled within the values of 5x1018 cm-3≤ Nch ≤3x1019 cm-3 that are commonly used in many reported works.8-12 This specification can be varied according to how the devices are designed. There is a similar concern related to the TSi. The transfer curves of the simulated device are shown in Figure S9 (a). VTH and Ion linearly vary with respect to the TSi values, as shown in Figure S9 (b). Figure S9 (c) shows Ioff, which is extracted at VG = VTH - 0.3 V for the different TSi values. Ioff was very small at a TSi of 20 nm, abruptly increasing when TSi reaches 25 nm due to the failure of the device to be in the full-depletion mode in the off-state. Ioff becomes more nonnegligible when TSi exceeds 25 nm (not shown due to the finite mesh density13). Thus, it is important that TSi should be kept within the acceptable off-current range, which can be varied according to how the devices are designed. To keep Ioff at its smallest value, it is necessary to keep the low TSi whose Ion can be compensated by stacking more nanowires in the vertically stacked nanowire FET structures. Although the combination of the GAA structure and JL mode has various advantages in relation to the effective suppression of the short channel effects (SCEs) and process simplicity, the combination inevitably requires the proper compromise between high-performance and low
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power consumption mentioned above. In this regard, the suggested VJ-FET can be a good approach for versatile CMOS design with high Ion and low Ioff.
Figure S8. 3-D Simulation results. (a) Transfer characteristic (ID-VG) of the simulated device. (b) Variation of VTH as a function of Nch. (c) Variation of Ioff as a function of Nch. (d) Variation of Ion as a function of Nch.
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Figure S9. 3-D Simulation results. (a) Transfer characteristic of the simulated device with proper Nch (as extracted from Figure S8). (b) Variation of Ion and VTH as a function of Nch. (c) Variation of Ioff as a function of Nch.
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