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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 8, AUGUST 2003
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An Accurate Automatic Tuning Scheme for High-Q Continuous-Time Bandpass Filters Based on Amplitude Comparison Hengsheng Liu, Member, IEEE, and Aydın ˙Ilker Kars¸ılayan, Member, IEEE
Abstract—A new automatic tuning scheme for continuous-time high-Q-bandpass filters is presented. It is conducted by amplitude comparison at three frequencies generated by an on-chip frequency synthesizer. Theoretical analysis and experimental results are provided. Analysis shows the tuning method is suitable for 10. A m second-order filter bandpass filters with is designed to demonstrate the proposed tuning scheme. The test chip is fabricated in AMI 0.5- m process. The measured frequency tuning error is 0.25%, and Q-tuning error is 3% for a 200-MHz filter with a desired Q of 28.6. Index Terms—Automatic tuning, bandpass filters, CMOS analog integrated circuits, continuous-time filters.
I. INTRODUCTION
F
REQUENCY response of an integrated continuous-time filter is determined by absolute values of resistors, capacitors, inductors or transconductors, depending on the implementation. Process variations, temperature fluctuation, and parasitics can limit the accuracy of these parameters. To achieve the desired filter performance, an on-chip automatic tuning scheme is usually required. Several automatic-tuning methods for second-order bandpass filters have been proposed. The frequency tuning methods have been reported to achieve tuning error less than 1% [1]–[6]. However, Q-tuning at high frequency ( 100 MHz) is still a big challenge. The Q-tuning method based on step response [1] has an advantage that the tuning circuitry has little impact on the filter’s SNR. It is performed by matching the envelope of a biquad’s step response with that of a well-defined first-order reference filter. However, its accuracy is limited to 30% due to the difficulty of envelope matching. Other Q-tuning schemes utilize magnitude-locked-loop [2]–[7] techniques. They are based on the fact that Q is equal to biquad’s peak gain (G) when the filter is tuned. In [2], peak detectors are used to detect the filter’s input and output amplitude, and hence, the gain. However, mismatch of the peak detectors will cause the gain control error, thus, the Q-tuning error. Another Q-tuning method [4], [6] utiManuscript received April 8, 2002; revised February 11, 2003. This work was supported in part by the Semiconductor Research Corporation under Grant 2000-HJ-767. This paper was recommended by Associated Editor A. Tang H. Liu was with the Department of Electrical Engineering, Texas A&M University, College Station, TX 77843-3128 USA. He is now with Linear Technology Corporation, Colorado Springs, CO 80919 USA. A. ˙I. Kars¸ılayan is with the Department of Electrical Engineering, Texas A&M University, College Station, TX 77843-3128 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSII.2003.814802
lizes the least-mean-square algorithm to lock the filter’s gain, where Q-tuning error of 1% is reported for a 10.7 MHz OTA-C bandpass filter. An accurate high-frequency divide-by-Q circuit is necessary to define the Q-factor in this method, but the proposed capacitive voltage divider is vulnerable to parasitic and loading capacitance. All Q-tuning methods based on share a common problem: the relation of is usually not accurate when nonidealities such as mismatch, parasitics, nonzero output conductance, and excess phase of OTA-C integrator are considered. Other filters, such as LC filters, do not have a direct relation between gain and Q-factor [8]. The principle of frequency tuning in this work is similar to that in [9], where two signals with frequencies at which the filter’s output is 12-dB lower than its peak gain are used as stimuli. The filter’s center frequency is supposed to be tuned to the average frequency of the two input signals by balancing their output amplitude. However, using stimuli with gains far below the filter’s peak gain will suffer from the asymmetry of filter’s frequency response. In addition, no Q-tuning scheme is proposed, so there is no guarantee that the filter gains at the reference frequencies will be 12-dB below the peak without any additional gain control loop. In the proposed scheme, an on-chip frequency synthesizer alternatively generates references at three different frequencies to stimulate the filter [10]. Both frequency and Q-tuning are performed through the gain comparison among different frequenassumption. cies. The Q-tuning does not rely on the A start-up tuning circuit is provided to increase the frequency tuning range. An OTA-C biquad is designed to evaluate the tuning scheme. Frequency tuning error of 0.25% and Q-tuning error of 3% are achieved from test chips. The paper is divided as follows. The second-order OTA-C filter is described in Section II. The principle of our proposed tuning scheme is described in Section III. Section IV presents the implementation details. In Section V, experimental results of the fabricated chip are presented. Section VI is the conclusion of the work. II. SECOND-ORDER BANDPASS FILTER Fig. 1 shows a differential biquadratic filter with Q-enhancement technique. The operational transconductance forms a positive feedback loop amplifier (OTA) labeled to compensate the loss of the filter due to the finite output impedance of the OTA, therefore increasing the Q value. The and , center frequency can be tuned by changing
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Fig. 1.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 8, AUGUST 2003
Second-order OTA-C bandpass filter.
while the Q-factor can be tuned by adjusting . The transfer function of the biquad is given as (1) at bottom of page, and are the sums of the output conductances, where and are the sums of the parasitic capacitances at the and , respectively. The excess phases of OTA-C nodes integrators are not included. Around the center frequency, (1) can be approximated as (2)–(5), shown at the bottom of page. yields Therefore,
Assuming
is negligible and
(6) , (6) leads to (7)
For simplicity, all OTAs are assumed to have the same input , and the same output parasitic caparasitic capacitances, . Then pacitances, (8) (9)
Equations (8) and (9) indicate . In high frequency OTA-C filters, the intentional integration capacitor C will be scaled down, and transistor sizes will be scaled up to will be a achieve large transconductance. Therefore, very poor assumption due to large parasitic capacitances. Even , , and at relatively low frequencies, perfectly matching is not easy. In addition, the requirement put extra constraints in filter design. For example, high Q results in high gain, thus the input signal will have little voltage swing. A simple OTA and its common-mode feedback circuits used in this work are shown in Fig. 2. The source degeneration resistor is split into two resistors to sense the common-mode voltage of previous stage [11], which can be used to generate the common-mode feedback. This technique avoids the distortion introduced by additional common-mode detectors. The detected common-mode voltage is compared with the . reference voltage, and the error is fed back to the node is much smaller than and to decrease Q-tuning uses transistor source degeneration sensitivity. In addition, to have larger tuning range. The design details of all OTAs are listed in Tables I and II. Due to its simplicity, the OTA does not have additional internal poles. The transconductance can be adjusted by the bias voltage . When the total tail current flows through the left side of the bias circuit, the OTA will achieve the maximum transconductance. More linearization techniques have been discussed in [12]. is intentionally chosen, Even though simulation shows the Q-factor is about one-third greater than G when the filter’s center frequency is 200 MHz, with Q between 5 and 40. In the actual design, in order to maintain a moderate is chosen smaller than and , gain at high Q values, so that the filter has a relatively large input voltage swing.
(1)
(2) Therefore (3)
(4)
(5)
LIU AND KARS¸ILAYAN: AN ACCURATE AUTOMATIC TUNING SCHEME FOR HIGH-Q CONTINUOUS-TIME BANDPASS FILTERS
(a)
417
(b)
(c) Fig. 2.
(a) g
,g
, and g
PARAMETERS OF g
. (b) g
. (c) Common-mode feedback circuit.
TABLE I , g , AND g
TRANSCONDUCTORS
at and to be equal, while the Q-factor can be tuned to a certain value by forcing the filter gain at its center and . frequency to double that at Around its center frequency, a second-order bandpass filter can be characterized as (10) where G is the gain at the center frequency , and Q is the and quality factor. Assuming the filter gains at both are equal to , then at and the following should hold (11)
TABLE II PARAMETERS OF g TRANSCONDUCTOR
Equation (11) can be rearranged as (12) For convenience, define Equation (12) yields
, and
. (13) (14)
Hence III. PRINCIPLE OF THE PROPOSED TUNING SCHEME In the proposed scheme, references with frequencies of , , are fed to the bandpass filter periodically. The by forcing the filter gains center frequency can be tuned to
(15)
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Fig. 3. Frequency-tuning error as a function of Q-factor.
Fig. 4. Block diagram of the proposed tuning scheme.
IV. IMPLEMENTATION (16) Equation (15) indicates the tuning error between the reference and the actual frequencies is (17) if (18)
Fig. 4 shows the block diagram of the proposed tuning scheme. The phased-locked loop (PLL)-based frequency , synthesizer generates references at frequencies and periodically by changing the division ratio of its frequency divider. The selective attenuator performs two functions as follows: 1) it attenuates large output of the frequency synthesizer, therefore, the OTA-C filter works in the linear region; double that at . 2) it sets the attenuation ratio at is twice that at Since the gain of the tuned filter at , the filter will have constant output over all these three frequencies.
from (16) and (18), Q-factor can be derived as (19) Equations (18) and (19) are the bases of this tuning scheme. The frequency tuning can be conducted by and . If comparing , its center frequency can be approximated to . Based on (17), the frequency-tuning error of this method is plotted in Fig. 3. Notice is negligible. At low-Q case, the that the error at transfer characteristic of the second-order filter is asymmetric, . The systematic and the center frequency will deviate from . By following the frequency tuning error is 4.2% at procedure above, the frequency tuning error of [9] can be derived as
The center frequency and Q-factor are tuned to the desired values once the filter has constant output over the three frequencies. The output amplitude of the filter can be detected by a peak detector. Two switched-capacitor integrators are used to integrate the differences of the filter’s output amplitude among the three frequencies, hence adjusting the frequency and Q-bias voltages. The clock generator provides clock signals to synchronize the frequency synthesizer, the selective attenuator, and the integrators. The master–slave tuning structure is used by most existing tuning techniques. However, the tuning accuracy will be limited by the mismatch between master and slave filters. Fortunately, many communication systems, such as time-division multiple access (TDMA) systems, do not demand continuous signal processing. So, the no-signal time slots can be used to tune the bandpass filter. The filter will be switched back for filtering once it is tuned.
(20) A. PLL-Based Frequency Synthesizer which is also plotted in Fig. 3. This error is about five times larger than that of the proposed scheme in this paper. doubles that at Once the frequency is tuned, if the gain at , the Q-factor of the bandpass filter will be . The practical solution for Q-tuning used here is to force to be equal to .
The frequency synthesizer shown in Fig. 5 consists of a phase/frequency detector (P/FD), a charge pump, a second-order loop filter, a ring voltage-control oscillator (VCO) and a frequency divider. The division ratio is periodi, N, or by changing and . The cally set to , output frequency of the VCO is therefore
LIU AND KARS¸ILAYAN: AN ACCURATE AUTOMATIC TUNING SCHEME FOR HIGH-Q CONTINUOUS-TIME BANDPASS FILTERS
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Fig. 5. Frequency synthesizer.
Fig. 7. Selective attenuator, V
Fig. 6.
= V 0V
,V
= V 0V
.
Delay cell and replica biasing of VCO.
and
, correspondingly. We choose MHz, , therefore, the desired center frequency of the filter will be 200 MHz, and the desired Q-factor will be
Fig. 8.
Peak detector.
HIGH. When Therefore
is generated,
is HIGH,
is LOW.
(21) (24) Generally speaking, N does not have to be an integer if a fractional-N frequency divider is used in the synthesizer. Therefore, the desired Q is not limited to some discrete values. The ring VCO consists of four identical differential delay cells as shown in Fig. 6. The pMOS transistors work in the deep triode region. The oscillation frequency is proportional to the tail current. The left side replica is used to define the output swing [13], so that the VCO output swing is independent of its is used to staoscillation frequency. Compensation capacitor bilize the feedback loop in the replica biasing circuit and to reduce the phase noise introduced by the power supply. B. Selective Attenuator Large reference signals from the frequency synthesizer can , then be attenuated by the circuit in Fig. 7. If (22) (23) . and are the selection switches. resulting in is generated by the synthesizer, is LOW, is When
is twice that at . The attenuation ratio at when the The filter’s center frequency may be far from power supply is just turned on. The filter’s output can be too small to detect and the tuning circuits will be out of lock. A start-up scheme for the automatic tuning is provided through the will bypass at selective divider; the two transistors across the beginning of tuning process, relatively large signals will go through the filter. Once the center frequency is pulled within the , the peak detector produces a large output, vicinity of will be set to LOW, and then large attenuation will guarantee that the filter is operating in linear region. C. Peak Detector The peak detector [3] shown in Fig. 8 detects the amplitude of the filter’s output. It consists of a buffer and a full wave rectifier. The common-mode voltage of the biquad slightly depends on signal frequency even though common-mode feedback circuits are applied. The differential buffer can alleviate the effect of the common-mode voltage. The capacitor connected to the rectifier will filter out the high-frequency signal. Since only one peak detector is used, matching two (or more) peak detectors is not relevant. Furthermore, linearity of the peak detector is not
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 8, AUGUST 2003
Fig. 10.
Fig. 9. Switch-capacitor integrators for frequency and Q-bias, where V is the output of the peak detector. C C C C 0:2 pF, C = mC = C = C = 1 pF.
=
=
=
=
Clock generator.
The next four steps will repeat the above process, except the switch will be closed at Step 3 instead of Step 1. Therefore, Q-bias voltage will be updated as (27)
important since its input at the three references has the same amplitude at the steady state.
The frequency bias voltage will be updated according to the same (25). The average effect of (26) and (27) is
D. Integrators , and given The filter’s output amplitude at , and , by the peak detector are will respectively. The difference be integrated for frequency bias, whereas will be integrated for Q-bias. Switchedcapacitor integrators shown in Fig. 9 are used because of the discrete nature of the tuning scheme. The synthesizer produces fre, and periodically. The switched-caquencies pacitor circuits sample the filter output amplitude only when the synthesizer and filter reach steady states. Its operation procedure is as follows. Step 1) The division ratio of the frequency divider is chosen is as 32. A signal with frequency of generated. The filter’s output amplitude given by the peak detector will be sampled into and . capacitor Step 2) The division ratio is chosen as 33. A signal with freis generated by the frequency quency of synthesizer. The filter’s output amplitude will be sampled into capacitor . Step 3) The division ratio is chosen as 34. A signal with is generated by the frequency of synthesizer. The filter’s output amplitude will be sampled into capacitor . Step 4) After is turned off, the Switches will be closed. , , , and will be inCharges stored in , , , and , corjected to the capacitors respondingly. Therefore the frequency and Q-bias voltage will be updated as (25) (26)
(28) The tuning system repetitively run the eight steps described , the freabove. Once quency and -tuning loops are settled. The differential nature of switched-capacitor integrators can partially reduce the clock feedthrough of switches. Minimum-sized transistors are used as switches to further reduce the clock feedthrough. The frequency and Q-tuning loops are coupled because the filter’s center frequency and Q are interacted. Small ratios of and can reduce the ripples in and , and improve the loops’ stabilities, but will increase the settling pF, times. We chose pF. In order to avoid the two loops fighting each other, we designed the Q-tuning loop to be much slower than the frequency-tuning loop [14]. This was achieved in Fig. 2(a) and (b). Stability of by choosing the loops were also verified by simulation results. E. Clock Generator Clock signals are required to synchronize the frequency synthesizer, the attenuator, and the integrators. These clock signals and set are provided by the circuit shown in Fig. 10. the division ratio of the frequency divider, hence, the output freand are control signals of the quency of the synthesizer. selective attenuator. , , , , and are switching signals of the integrators. is not an independent clock, it switches bein Fig. 10 alternatively tween and , i.e., the capacitor or . It is equivalent to sample samples . Simulation result of the clock , the frequency of generator is shown in Fig. 11. When , and is set to 1. When the synthesizer will be settled to , , the frequency of the synthesizer will be settled , is set to 0. When , , the frequency to
LIU AND KARS¸ILAYAN: AN ACCURATE AUTOMATIC TUNING SCHEME FOR HIGH-Q CONTINUOUS-TIME BANDPASS FILTERS
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Fig. 13. Microphotograph of the chip.
Fig. 11. Simulated waveforms of the synchronization clocks.
Fig. 12.
Simulation results of the tuning process. Fig. 14. Spectrum of the frequency synthesizer.
of the synthesizer will be settled to , and is set to 1.The is chosen longer since the frequency synthetime slot for to . sizer needs longer time to transit from F. Simulation A simulation result of tuning process for the bandpass filter is shown in Fig. 12. To lock the bandpass filter at the desired center frequency of 200 MHz, the input reference of the frequency synthesizer should be square wave with a frequency of 6.06 MHz (200 MHz/33). We choose the frequency of clk, the input of the clock generator as 400 kHz, such that the frequency synthesizer, the integrators have adequate times to settle down. As can be seen in Fig. 12, SW is HIGH at the beginning of the tuning process. As the tuning circuits drive the filter to the desired frequency and Q-factor, its output increases. Once the filter output reaches a certain value, SW is set to LOW and the gain of the attenuator is reduced. Eventually, the frequency and the Q-bias voltages settle to 1.418 V and 877 mV, respectively, leading to a center frequency of the bandpass filter of 200.2 MHz, and Q-factor of 29.1 Therefore, the simulated frequency tuning error is 0.1%, and the Q-tuning error is 1.7%. The tuning loops converge in about 220 S.
V. EXPERIMENTAL RESULTS The circuit has been fabricated using the AMI 0.5- m process. Fig. 13 shows the die photograph of the chip. The active area is about 0.25 mm . Power supply voltage is 3 V. The of the synthesizer is set to 6.06 MHz. reference frequency Fig. 14 shows the spectrum of the frequency synthesizer, three generated frequencies are 193.64, 200, and 206.06 MHz. Actually, the three frequencies are generated at different time intervals. The average power at 193.64 MHz is larger than the other two because this frequency is held for a longer time. The center frequency is adjustable simply by varying , the input reference frequency of the frequency synthesizer. The Q is not adjustable due to the limited programmability of the designed frequency divider, where the division ration was fixed to 32, 33, and 34 depending on the control input. To have adjustable Q, a frequency divider with more programmability should be used. Fig. 15 shows the bandpass filter’s output voltage and the control voltage of the VCO in the frequency synthesizer. The three levels of VCO control voltage correspond to three different frequencies generated. The filter’s output amplitude is constant over the three frequencies. It indicates that frequency
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 8, AUGUST 2003
TABLE III EXPERIMENTAL RESULTS AT f 200:5 MHz, Q = 29:5
=
Fig. 15.
Filter output (top) and VCO control voltage (bottom).
The tuned filter’s response curve is plotted in Fig. 16. The center frequencies is 200.5 MHz, Q-factor is 29.5, yielding to frequency error of 0.25% and Q error of 3%. Fig. 17 shows the in-band two-tone third-order intermodulation (IM3) distortion measurement, with the two tones at 199.5 and 200.5 MHz, respectively. The IM3 products are on 198.5 and 201.5 MHz, which fall within the filter’s passband. The test results are summarized in Table III. VI. CONCLUSION
Fig. 16.
Frequency response of the tuned filter.
An OTA-C prototype bandpass filter is designed to evaluate the proposed tuning scheme. Experiments show that this scheme is reliable for high frequency and high-Q bandpass filter tuning. The proposed tuning scheme is based on gain comparison at three frequencies. The Q-tuning does not rely on the assumption , and the Q-factor is not set by the analog divide-by-Q of circuit. Instead, it is digitally set through the frequency divider. Therefore, high accuracy can be achieved. This tuning scheme is also suitable for tuning of on-chip LC bandpass filters, and other filters, whose quality factor is not a known function of filter’s gain. REFERENCES
Fig. 17. Third-order intermodulation measurement.
and Q-tuning loops are settled. The ripples at the filter’s output are due to the transition between different frequencies.
[1] J. Silva-Martínez, M. S. Steyaert, and W. C. Sansen, “A 10.7 MHz 68-dB SNR CMOS continuous-time filter with on-chip automatic tuning,” IEEE J. Solid-State Circuits, vol. 27, pp. 1843–1853, Dec. 1992. [2] C. S. Park and R. Schaumann, “Design of a 4-MHz analog integrated CMOS transconductance-C bandpass filter,” IEEE J. Solid-State Circuits, vol. SC-23, pp. 987–996, Aug. 1988. [3] J. F. Parker and K. W. Current, “A CMOS continuous-time bandpass filter with peak detector-based automatic tuning,” Int. J. Electron., vol. 81, no. 5, pp. 551–564, 1996. [4] J.-M. Stevenson and E. Sánchez-Sinencio, “An accurate quality factor tuning scheme for IF and high-Q continuous-time filter,” IEEE J. SolidState Circuits, vol. SC-33, pp. 1970–1978, Dec. 1998. [5] A. ˙I. Kars¸ılayan and R. Schaumann, “Automatic tuning of frequency and Q-factor of bandpass filters based on peak detection,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 1998, pp. 65–68.
LIU AND KARS¸ILAYAN: AN ACCURATE AUTOMATIC TUNING SCHEME FOR HIGH-Q CONTINUOUS-TIME BANDPASS FILTERS
[6] Y. W. Choi and H. C. Luong, “A high-Q and wide-dynamic-range 70-MHz CMOS bandpass filter for wireless receivers,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 433–440, May 2001. [7] J. I. Osa, A. Carlosena, and A. J. Lopez-Martin, “MOSFET-C filter with on-chip tuning and wide programming range,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 944–951, Oct. 2001. [8] W. Gao and W. M. Snelgrove, “A linear integrated LC bandpass filter with Q-enhancement,” IEEE Trans. Circuits Syst., pt. II, vol. 45, pp. 635–639, May 1998. [9] Y. Chang, J. Wills, and J. Choma, “On-chip automatic direct tuning circuitry based on the synchronous rectification scheme for CMOS gigahertz band front-end filters,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 4, 2001, pp. 246–249. [10] H. Liu and A. ˙I. Kars¸ılayan, “An automatic tuning scheme for high frequency bandpass filters,” in Proc. IEEE ISCAS, vol. 3, 2002, pp. 551–554. [11] A. Lopez-Martinez, R. Antonio-Chavez, and J. Silva-Martinez, “A 150 MHz continuous-time seventh order 0.05 equiripple linear phase filter with automatic tuning system,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 1, 2001, pp. 156–159. [12] K.-K. Kuo and A. Leuciuc, “A linear CMOS transconductor using source degeneration and adaptive biasing,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 937–943, Oct 2001. [13] B. Kim and P. Gray, “30 MHz hybrid analog/digital clock recovery circuit in 2-um CMOS,” IEEE J. Solid-State Circuits, vol. 25, pp. 1385–1394, Dec. 1990. [14] H. Liu, “Automatic tuning for high frequency continuous-time bandpass filters,” Ph.D. dissertation, Dept. Elect. Eng., Texas A&M Univ., College Station, TX, Dec. 2002.
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Hengsheng Liu (S’00–M’03) received the B. S. degree in solid-state electronics from Huazhong University of Science and Technology, Wuhan, China, and the M.S. degree in plasma physics from the Chinese Academy of Science, Beijing, China, in 1989 and 1992, and the Ph.D. degree in electrical engineering from Texas A&M University, College Station, in 2002. He was with National Synchrotron Radiation Laboratory, University of Science and Technology of China, Anhui, from 1992 to 1998. From August 2000 to January 2001, he was an Intern at Analog/Mixed Signal Design Center, Cadence Design Service, Cary, NC. He is currently with Linear Technology Corporation, Colorado Springs, CO.
˙ Aydın Ilker Kars¸ılayan (S’93–M’99) received the B.S. and M.S. degrees in electrical engineering from Bilkent University, Ankara, Turkey, and the Ph.D. degree from Portland State University, Portland, OR, in 1993, 1995, and 2000, respectively. In 2000, he joined the faculty of Texas A&M University, College Station, where he is currently an Assistant Professor of electrical engineering. His research interests include high-frequency analog filters, automatic tuning, mixed-mode IC design, and RF communication circuits. Dr. Kars¸ılayan currently serves as an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: FUNDAMENTAL THEORY AND APPLICATIONS. He is a Member of Tau Beta Pi and Eta Kappa Nu.
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An Accurate Automatic Tuning Scheme for High-Q Continuous-Time Bandpass Filters Based on Amplitude Comparison Hengsheng Liu, Member, IEEE, and Aydın ˙Ilker Kars¸ılayan, Member, IEEE
Abstract—A new automatic tuning scheme for continuous-time high-Q-bandpass filters is presented. It is conducted by amplitude comparison at three frequencies generated by an on-chip frequency synthesizer. Theoretical analysis and experimental results are provided. Analysis shows the tuning method is suitable for 10. A m second-order filter bandpass filters with is designed to demonstrate the proposed tuning scheme. The test chip is fabricated in AMI 0.5- m process. The measured frequency tuning error is 0.25%, and Q-tuning error is 3% for a 200-MHz filter with a desired Q of 28.6. Index Terms—Automatic tuning, bandpass filters, CMOS analog integrated circuits, continuous-time filters.
I. INTRODUCTION
F
REQUENCY response of an integrated continuous-time filter is determined by absolute values of resistors, capacitors, inductors or transconductors, depending on the implementation. Process variations, temperature fluctuation, and parasitics can limit the accuracy of these parameters. To achieve the desired filter performance, an on-chip automatic tuning scheme is usually required. Several automatic-tuning methods for second-order bandpass filters have been proposed. The frequency tuning methods have been reported to achieve tuning error less than 1% [1]–[6]. However, Q-tuning at high frequency ( 100 MHz) is still a big challenge. The Q-tuning method based on step response [1] has an advantage that the tuning circuitry has little impact on the filter’s SNR. It is performed by matching the envelope of a biquad’s step response with that of a well-defined first-order reference filter. However, its accuracy is limited to 30% due to the difficulty of envelope matching. Other Q-tuning schemes utilize magnitude-locked-loop [2]–[7] techniques. They are based on the fact that Q is equal to biquad’s peak gain (G) when the filter is tuned. In [2], peak detectors are used to detect the filter’s input and output amplitude, and hence, the gain. However, mismatch of the peak detectors will cause the gain control error, thus, the Q-tuning error. Another Q-tuning method [4], [6] utiManuscript received April 8, 2002; revised February 11, 2003. This work was supported in part by the Semiconductor Research Corporation under Grant 2000-HJ-767. This paper was recommended by Associated Editor A. Tang H. Liu was with the Department of Electrical Engineering, Texas A&M University, College Station, TX 77843-3128 USA. He is now with Linear Technology Corporation, Colorado Springs, CO 80919 USA. A. ˙I. Kars¸ılayan is with the Department of Electrical Engineering, Texas A&M University, College Station, TX 77843-3128 USA (e-mail: [email protected]). Digital Object Identifier 10.1109/TCSII.2003.814802
lizes the least-mean-square algorithm to lock the filter’s gain, where Q-tuning error of 1% is reported for a 10.7 MHz OTA-C bandpass filter. An accurate high-frequency divide-by-Q circuit is necessary to define the Q-factor in this method, but the proposed capacitive voltage divider is vulnerable to parasitic and loading capacitance. All Q-tuning methods based on share a common problem: the relation of is usually not accurate when nonidealities such as mismatch, parasitics, nonzero output conductance, and excess phase of OTA-C integrator are considered. Other filters, such as LC filters, do not have a direct relation between gain and Q-factor [8]. The principle of frequency tuning in this work is similar to that in [9], where two signals with frequencies at which the filter’s output is 12-dB lower than its peak gain are used as stimuli. The filter’s center frequency is supposed to be tuned to the average frequency of the two input signals by balancing their output amplitude. However, using stimuli with gains far below the filter’s peak gain will suffer from the asymmetry of filter’s frequency response. In addition, no Q-tuning scheme is proposed, so there is no guarantee that the filter gains at the reference frequencies will be 12-dB below the peak without any additional gain control loop. In the proposed scheme, an on-chip frequency synthesizer alternatively generates references at three different frequencies to stimulate the filter [10]. Both frequency and Q-tuning are performed through the gain comparison among different frequenassumption. cies. The Q-tuning does not rely on the A start-up tuning circuit is provided to increase the frequency tuning range. An OTA-C biquad is designed to evaluate the tuning scheme. Frequency tuning error of 0.25% and Q-tuning error of 3% are achieved from test chips. The paper is divided as follows. The second-order OTA-C filter is described in Section II. The principle of our proposed tuning scheme is described in Section III. Section IV presents the implementation details. In Section V, experimental results of the fabricated chip are presented. Section VI is the conclusion of the work. II. SECOND-ORDER BANDPASS FILTER Fig. 1 shows a differential biquadratic filter with Q-enhancement technique. The operational transconductance forms a positive feedback loop amplifier (OTA) labeled to compensate the loss of the filter due to the finite output impedance of the OTA, therefore increasing the Q value. The and , center frequency can be tuned by changing
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Fig. 1.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 8, AUGUST 2003
Second-order OTA-C bandpass filter.
while the Q-factor can be tuned by adjusting . The transfer function of the biquad is given as (1) at bottom of page, and are the sums of the output conductances, where and are the sums of the parasitic capacitances at the and , respectively. The excess phases of OTA-C nodes integrators are not included. Around the center frequency, (1) can be approximated as (2)–(5), shown at the bottom of page. yields Therefore,
Assuming
is negligible and
(6) , (6) leads to (7)
For simplicity, all OTAs are assumed to have the same input , and the same output parasitic caparasitic capacitances, . Then pacitances, (8) (9)
Equations (8) and (9) indicate . In high frequency OTA-C filters, the intentional integration capacitor C will be scaled down, and transistor sizes will be scaled up to will be a achieve large transconductance. Therefore, very poor assumption due to large parasitic capacitances. Even , , and at relatively low frequencies, perfectly matching is not easy. In addition, the requirement put extra constraints in filter design. For example, high Q results in high gain, thus the input signal will have little voltage swing. A simple OTA and its common-mode feedback circuits used in this work are shown in Fig. 2. The source degeneration resistor is split into two resistors to sense the common-mode voltage of previous stage [11], which can be used to generate the common-mode feedback. This technique avoids the distortion introduced by additional common-mode detectors. The detected common-mode voltage is compared with the . reference voltage, and the error is fed back to the node is much smaller than and to decrease Q-tuning uses transistor source degeneration sensitivity. In addition, to have larger tuning range. The design details of all OTAs are listed in Tables I and II. Due to its simplicity, the OTA does not have additional internal poles. The transconductance can be adjusted by the bias voltage . When the total tail current flows through the left side of the bias circuit, the OTA will achieve the maximum transconductance. More linearization techniques have been discussed in [12]. is intentionally chosen, Even though simulation shows the Q-factor is about one-third greater than G when the filter’s center frequency is 200 MHz, with Q between 5 and 40. In the actual design, in order to maintain a moderate is chosen smaller than and , gain at high Q values, so that the filter has a relatively large input voltage swing.
(1)
(2) Therefore (3)
(4)
(5)
LIU AND KARS¸ILAYAN: AN ACCURATE AUTOMATIC TUNING SCHEME FOR HIGH-Q CONTINUOUS-TIME BANDPASS FILTERS
(a)
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(b)
(c) Fig. 2.
(a) g
,g
, and g
PARAMETERS OF g
. (b) g
. (c) Common-mode feedback circuit.
TABLE I , g , AND g
TRANSCONDUCTORS
at and to be equal, while the Q-factor can be tuned to a certain value by forcing the filter gain at its center and . frequency to double that at Around its center frequency, a second-order bandpass filter can be characterized as (10) where G is the gain at the center frequency , and Q is the and quality factor. Assuming the filter gains at both are equal to , then at and the following should hold (11)
TABLE II PARAMETERS OF g TRANSCONDUCTOR
Equation (11) can be rearranged as (12) For convenience, define Equation (12) yields
, and
. (13) (14)
Hence III. PRINCIPLE OF THE PROPOSED TUNING SCHEME In the proposed scheme, references with frequencies of , , are fed to the bandpass filter periodically. The by forcing the filter gains center frequency can be tuned to
(15)
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Fig. 3. Frequency-tuning error as a function of Q-factor.
Fig. 4. Block diagram of the proposed tuning scheme.
IV. IMPLEMENTATION (16) Equation (15) indicates the tuning error between the reference and the actual frequencies is (17) if (18)
Fig. 4 shows the block diagram of the proposed tuning scheme. The phased-locked loop (PLL)-based frequency , synthesizer generates references at frequencies and periodically by changing the division ratio of its frequency divider. The selective attenuator performs two functions as follows: 1) it attenuates large output of the frequency synthesizer, therefore, the OTA-C filter works in the linear region; double that at . 2) it sets the attenuation ratio at is twice that at Since the gain of the tuned filter at , the filter will have constant output over all these three frequencies.
from (16) and (18), Q-factor can be derived as (19) Equations (18) and (19) are the bases of this tuning scheme. The frequency tuning can be conducted by and . If comparing , its center frequency can be approximated to . Based on (17), the frequency-tuning error of this method is plotted in Fig. 3. Notice is negligible. At low-Q case, the that the error at transfer characteristic of the second-order filter is asymmetric, . The systematic and the center frequency will deviate from . By following the frequency tuning error is 4.2% at procedure above, the frequency tuning error of [9] can be derived as
The center frequency and Q-factor are tuned to the desired values once the filter has constant output over the three frequencies. The output amplitude of the filter can be detected by a peak detector. Two switched-capacitor integrators are used to integrate the differences of the filter’s output amplitude among the three frequencies, hence adjusting the frequency and Q-bias voltages. The clock generator provides clock signals to synchronize the frequency synthesizer, the selective attenuator, and the integrators. The master–slave tuning structure is used by most existing tuning techniques. However, the tuning accuracy will be limited by the mismatch between master and slave filters. Fortunately, many communication systems, such as time-division multiple access (TDMA) systems, do not demand continuous signal processing. So, the no-signal time slots can be used to tune the bandpass filter. The filter will be switched back for filtering once it is tuned.
(20) A. PLL-Based Frequency Synthesizer which is also plotted in Fig. 3. This error is about five times larger than that of the proposed scheme in this paper. doubles that at Once the frequency is tuned, if the gain at , the Q-factor of the bandpass filter will be . The practical solution for Q-tuning used here is to force to be equal to .
The frequency synthesizer shown in Fig. 5 consists of a phase/frequency detector (P/FD), a charge pump, a second-order loop filter, a ring voltage-control oscillator (VCO) and a frequency divider. The division ratio is periodi, N, or by changing and . The cally set to , output frequency of the VCO is therefore
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Fig. 5. Frequency synthesizer.
Fig. 7. Selective attenuator, V
Fig. 6.
= V 0V
,V
= V 0V
.
Delay cell and replica biasing of VCO.
and
, correspondingly. We choose MHz, , therefore, the desired center frequency of the filter will be 200 MHz, and the desired Q-factor will be
Fig. 8.
Peak detector.
HIGH. When Therefore
is generated,
is HIGH,
is LOW.
(21) (24) Generally speaking, N does not have to be an integer if a fractional-N frequency divider is used in the synthesizer. Therefore, the desired Q is not limited to some discrete values. The ring VCO consists of four identical differential delay cells as shown in Fig. 6. The pMOS transistors work in the deep triode region. The oscillation frequency is proportional to the tail current. The left side replica is used to define the output swing [13], so that the VCO output swing is independent of its is used to staoscillation frequency. Compensation capacitor bilize the feedback loop in the replica biasing circuit and to reduce the phase noise introduced by the power supply. B. Selective Attenuator Large reference signals from the frequency synthesizer can , then be attenuated by the circuit in Fig. 7. If (22) (23) . and are the selection switches. resulting in is generated by the synthesizer, is LOW, is When
is twice that at . The attenuation ratio at when the The filter’s center frequency may be far from power supply is just turned on. The filter’s output can be too small to detect and the tuning circuits will be out of lock. A start-up scheme for the automatic tuning is provided through the will bypass at selective divider; the two transistors across the beginning of tuning process, relatively large signals will go through the filter. Once the center frequency is pulled within the , the peak detector produces a large output, vicinity of will be set to LOW, and then large attenuation will guarantee that the filter is operating in linear region. C. Peak Detector The peak detector [3] shown in Fig. 8 detects the amplitude of the filter’s output. It consists of a buffer and a full wave rectifier. The common-mode voltage of the biquad slightly depends on signal frequency even though common-mode feedback circuits are applied. The differential buffer can alleviate the effect of the common-mode voltage. The capacitor connected to the rectifier will filter out the high-frequency signal. Since only one peak detector is used, matching two (or more) peak detectors is not relevant. Furthermore, linearity of the peak detector is not
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Fig. 10.
Fig. 9. Switch-capacitor integrators for frequency and Q-bias, where V is the output of the peak detector. C C C C 0:2 pF, C = mC = C = C = 1 pF.
=
=
=
=
Clock generator.
The next four steps will repeat the above process, except the switch will be closed at Step 3 instead of Step 1. Therefore, Q-bias voltage will be updated as (27)
important since its input at the three references has the same amplitude at the steady state.
The frequency bias voltage will be updated according to the same (25). The average effect of (26) and (27) is
D. Integrators , and given The filter’s output amplitude at , and , by the peak detector are will respectively. The difference be integrated for frequency bias, whereas will be integrated for Q-bias. Switchedcapacitor integrators shown in Fig. 9 are used because of the discrete nature of the tuning scheme. The synthesizer produces fre, and periodically. The switched-caquencies pacitor circuits sample the filter output amplitude only when the synthesizer and filter reach steady states. Its operation procedure is as follows. Step 1) The division ratio of the frequency divider is chosen is as 32. A signal with frequency of generated. The filter’s output amplitude given by the peak detector will be sampled into and . capacitor Step 2) The division ratio is chosen as 33. A signal with freis generated by the frequency quency of synthesizer. The filter’s output amplitude will be sampled into capacitor . Step 3) The division ratio is chosen as 34. A signal with is generated by the frequency of synthesizer. The filter’s output amplitude will be sampled into capacitor . Step 4) After is turned off, the Switches will be closed. , , , and will be inCharges stored in , , , and , corjected to the capacitors respondingly. Therefore the frequency and Q-bias voltage will be updated as (25) (26)
(28) The tuning system repetitively run the eight steps described , the freabove. Once quency and -tuning loops are settled. The differential nature of switched-capacitor integrators can partially reduce the clock feedthrough of switches. Minimum-sized transistors are used as switches to further reduce the clock feedthrough. The frequency and Q-tuning loops are coupled because the filter’s center frequency and Q are interacted. Small ratios of and can reduce the ripples in and , and improve the loops’ stabilities, but will increase the settling pF, times. We chose pF. In order to avoid the two loops fighting each other, we designed the Q-tuning loop to be much slower than the frequency-tuning loop [14]. This was achieved in Fig. 2(a) and (b). Stability of by choosing the loops were also verified by simulation results. E. Clock Generator Clock signals are required to synchronize the frequency synthesizer, the attenuator, and the integrators. These clock signals and set are provided by the circuit shown in Fig. 10. the division ratio of the frequency divider, hence, the output freand are control signals of the quency of the synthesizer. selective attenuator. , , , , and are switching signals of the integrators. is not an independent clock, it switches bein Fig. 10 alternatively tween and , i.e., the capacitor or . It is equivalent to sample samples . Simulation result of the clock , the frequency of generator is shown in Fig. 11. When , and is set to 1. When the synthesizer will be settled to , , the frequency of the synthesizer will be settled , is set to 0. When , , the frequency to
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Fig. 13. Microphotograph of the chip.
Fig. 11. Simulated waveforms of the synchronization clocks.
Fig. 12.
Simulation results of the tuning process. Fig. 14. Spectrum of the frequency synthesizer.
of the synthesizer will be settled to , and is set to 1.The is chosen longer since the frequency synthetime slot for to . sizer needs longer time to transit from F. Simulation A simulation result of tuning process for the bandpass filter is shown in Fig. 12. To lock the bandpass filter at the desired center frequency of 200 MHz, the input reference of the frequency synthesizer should be square wave with a frequency of 6.06 MHz (200 MHz/33). We choose the frequency of clk, the input of the clock generator as 400 kHz, such that the frequency synthesizer, the integrators have adequate times to settle down. As can be seen in Fig. 12, SW is HIGH at the beginning of the tuning process. As the tuning circuits drive the filter to the desired frequency and Q-factor, its output increases. Once the filter output reaches a certain value, SW is set to LOW and the gain of the attenuator is reduced. Eventually, the frequency and the Q-bias voltages settle to 1.418 V and 877 mV, respectively, leading to a center frequency of the bandpass filter of 200.2 MHz, and Q-factor of 29.1 Therefore, the simulated frequency tuning error is 0.1%, and the Q-tuning error is 1.7%. The tuning loops converge in about 220 S.
V. EXPERIMENTAL RESULTS The circuit has been fabricated using the AMI 0.5- m process. Fig. 13 shows the die photograph of the chip. The active area is about 0.25 mm . Power supply voltage is 3 V. The of the synthesizer is set to 6.06 MHz. reference frequency Fig. 14 shows the spectrum of the frequency synthesizer, three generated frequencies are 193.64, 200, and 206.06 MHz. Actually, the three frequencies are generated at different time intervals. The average power at 193.64 MHz is larger than the other two because this frequency is held for a longer time. The center frequency is adjustable simply by varying , the input reference frequency of the frequency synthesizer. The Q is not adjustable due to the limited programmability of the designed frequency divider, where the division ration was fixed to 32, 33, and 34 depending on the control input. To have adjustable Q, a frequency divider with more programmability should be used. Fig. 15 shows the bandpass filter’s output voltage and the control voltage of the VCO in the frequency synthesizer. The three levels of VCO control voltage correspond to three different frequencies generated. The filter’s output amplitude is constant over the three frequencies. It indicates that frequency
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TABLE III EXPERIMENTAL RESULTS AT f 200:5 MHz, Q = 29:5
=
Fig. 15.
Filter output (top) and VCO control voltage (bottom).
The tuned filter’s response curve is plotted in Fig. 16. The center frequencies is 200.5 MHz, Q-factor is 29.5, yielding to frequency error of 0.25% and Q error of 3%. Fig. 17 shows the in-band two-tone third-order intermodulation (IM3) distortion measurement, with the two tones at 199.5 and 200.5 MHz, respectively. The IM3 products are on 198.5 and 201.5 MHz, which fall within the filter’s passband. The test results are summarized in Table III. VI. CONCLUSION
Fig. 16.
Frequency response of the tuned filter.
An OTA-C prototype bandpass filter is designed to evaluate the proposed tuning scheme. Experiments show that this scheme is reliable for high frequency and high-Q bandpass filter tuning. The proposed tuning scheme is based on gain comparison at three frequencies. The Q-tuning does not rely on the assumption , and the Q-factor is not set by the analog divide-by-Q of circuit. Instead, it is digitally set through the frequency divider. Therefore, high accuracy can be achieved. This tuning scheme is also suitable for tuning of on-chip LC bandpass filters, and other filters, whose quality factor is not a known function of filter’s gain. REFERENCES
Fig. 17. Third-order intermodulation measurement.
and Q-tuning loops are settled. The ripples at the filter’s output are due to the transition between different frequencies.
[1] J. Silva-Martínez, M. S. Steyaert, and W. C. Sansen, “A 10.7 MHz 68-dB SNR CMOS continuous-time filter with on-chip automatic tuning,” IEEE J. Solid-State Circuits, vol. 27, pp. 1843–1853, Dec. 1992. [2] C. S. Park and R. Schaumann, “Design of a 4-MHz analog integrated CMOS transconductance-C bandpass filter,” IEEE J. Solid-State Circuits, vol. SC-23, pp. 987–996, Aug. 1988. [3] J. F. Parker and K. W. Current, “A CMOS continuous-time bandpass filter with peak detector-based automatic tuning,” Int. J. Electron., vol. 81, no. 5, pp. 551–564, 1996. [4] J.-M. Stevenson and E. Sánchez-Sinencio, “An accurate quality factor tuning scheme for IF and high-Q continuous-time filter,” IEEE J. SolidState Circuits, vol. SC-33, pp. 1970–1978, Dec. 1998. [5] A. ˙I. Kars¸ılayan and R. Schaumann, “Automatic tuning of frequency and Q-factor of bandpass filters based on peak detection,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 1998, pp. 65–68.
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[6] Y. W. Choi and H. C. Luong, “A high-Q and wide-dynamic-range 70-MHz CMOS bandpass filter for wireless receivers,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 433–440, May 2001. [7] J. I. Osa, A. Carlosena, and A. J. Lopez-Martin, “MOSFET-C filter with on-chip tuning and wide programming range,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 944–951, Oct. 2001. [8] W. Gao and W. M. Snelgrove, “A linear integrated LC bandpass filter with Q-enhancement,” IEEE Trans. Circuits Syst., pt. II, vol. 45, pp. 635–639, May 1998. [9] Y. Chang, J. Wills, and J. Choma, “On-chip automatic direct tuning circuitry based on the synchronous rectification scheme for CMOS gigahertz band front-end filters,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 4, 2001, pp. 246–249. [10] H. Liu and A. ˙I. Kars¸ılayan, “An automatic tuning scheme for high frequency bandpass filters,” in Proc. IEEE ISCAS, vol. 3, 2002, pp. 551–554. [11] A. Lopez-Martinez, R. Antonio-Chavez, and J. Silva-Martinez, “A 150 MHz continuous-time seventh order 0.05 equiripple linear phase filter with automatic tuning system,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 1, 2001, pp. 156–159. [12] K.-K. Kuo and A. Leuciuc, “A linear CMOS transconductor using source degeneration and adaptive biasing,” IEEE Trans. Circuits Syst. II, vol. 48, pp. 937–943, Oct 2001. [13] B. Kim and P. Gray, “30 MHz hybrid analog/digital clock recovery circuit in 2-um CMOS,” IEEE J. Solid-State Circuits, vol. 25, pp. 1385–1394, Dec. 1990. [14] H. Liu, “Automatic tuning for high frequency continuous-time bandpass filters,” Ph.D. dissertation, Dept. Elect. Eng., Texas A&M Univ., College Station, TX, Dec. 2002.
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Hengsheng Liu (S’00–M’03) received the B. S. degree in solid-state electronics from Huazhong University of Science and Technology, Wuhan, China, and the M.S. degree in plasma physics from the Chinese Academy of Science, Beijing, China, in 1989 and 1992, and the Ph.D. degree in electrical engineering from Texas A&M University, College Station, in 2002. He was with National Synchrotron Radiation Laboratory, University of Science and Technology of China, Anhui, from 1992 to 1998. From August 2000 to January 2001, he was an Intern at Analog/Mixed Signal Design Center, Cadence Design Service, Cary, NC. He is currently with Linear Technology Corporation, Colorado Springs, CO.
˙ Aydın Ilker Kars¸ılayan (S’93–M’99) received the B.S. and M.S. degrees in electrical engineering from Bilkent University, Ankara, Turkey, and the Ph.D. degree from Portland State University, Portland, OR, in 1993, 1995, and 2000, respectively. In 2000, he joined the faculty of Texas A&M University, College Station, where he is currently an Assistant Professor of electrical engineering. His research interests include high-frequency analog filters, automatic tuning, mixed-mode IC design, and RF communication circuits. Dr. Kars¸ılayan currently serves as an Associate Editor for the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—PART I: FUNDAMENTAL THEORY AND APPLICATIONS. He is a Member of Tau Beta Pi and Eta Kappa Nu.
