Automatic Tuning
A 4MHz Gm-C Filter with On-Chip Frequency Automatic Tuning Jinke Yao
Department of Electronic Engineering Tsinghua University, Beijing, China
yaojkO0gmails.tsinghua.edu.cn
Baoyong Chi
Institute of Microelectronics Tsinghua University, Beijing, China
chibylxcgmails.tsinghua.edu.cn
Abstract A fifth-order elliptic low-pass Gm-C filter used in monolithic DAB receiver is presented, the filter integrates an on-chip frequency automatic tuning circuit based on PLL to control the cutoff frequency. The filter has been implemented in 0.25um CMOS process. The measurement results show that the frequency tuning error is within 1%, the dynamic range is
Zhihua Wang
Institute of Microelectronics Tsinghua University, Beijing, China
zhihuagtsinghua.edu.cn
performance and different accuracy. Among these methods, the filter with leapfrog structure could achieve the lowest sensitivity and the best DR performance [1], so it's adopted in this design. The state equations of the ladder filter shown in Fig. 1 can be listed using the current through the inductors and the voltage at the grounded cap
54dB, the stop-band rejection rate is greater than 40dB. The filte dras l3A curentfrom 3.3 powr suply.as the state
variables. After some conversions, a group of new state equations, which uses only voltage variables and has no differential operations, can be listed. When the GmC integrators have been used to realize the integration operations of the new state equations, a leapfrog filter with the same transfer function can be got, which is shown in Fig.2. To get higher tuning accuracy, the trans-conductors used in the filter are identical.
I. INTRODUCTION The continuous-time filter is one of the key modules in the monolithic receiver, and is often the bottleneck to implement the monolithic receiver. The low-pass filter presented in the paper is designed for L-band DAB (Digital Audio Broadcast) application, and must satisfy the following requirements: the pass band (0-3MHz) ripple is smaller than 0.5dB, the attenuation beyond 4MHz is higher than 40dB, the THD is less than 1% when Vpp=600mV, and the DR (dynamic range) is larger than 50dB.
Among the filter topologies, the elliptic topology could realize the required stop band attenuation with the minimum order, so the elliptic topology is selected for our filter. With the help of the filter synthesis software, the ladder filter prototype is deduced from the specifications and is shown in Fig. 1. 54 13nNH 37 4On
4336 rF
1471nF
1 UU. 1 n[
78.81 n
G,,G,,
Fig.2 A 5th order Gm-C leapfrog elliptic LPF
FILTER TOPOLOGY
II.
60.52nF
G
Fig.1 The ladder filter prototype High order filters based on the integrators could be constructed using the different methods. Different constructed methods would result in different DR
III. THE DESIGN OF THE LINEAR TRANSCONDUCTOR In this design, the linear input stage presented in Szczepanski's paper [2] is adopted. To add voltages at the input port, Fig.3 uses the dual port input stage, whereVCTL is a tunable floating voltage source. The transconductance of the transconductor is it can be controlled
[tCOX(W/L)VcTL,
efficiently by VCTL. The integrators time constants C/Gm
are defined by the transform function, but the values of the Gm could be selected freely. In this design, the Gm is defined through such a strategy: first, a unit transconductor with Gm=50uS is designed. After optimizing the bias current and the transistor size, the unit transconductor achieves less than 0.5°0 THD when Vpp=600mv. The filter is based on the unit transconductor. Then, the gain at the internal nodes is checked, when the gain is large than 1, we increase the grounded cap at integral times until the gain is less than 1, and then increase all the unit transconductors whose input ports be connected to the node, at the same times by shunt.
This research was partly supported by the National Science Foundation (No.60475018, No. 90407006)
0-7803-9390-2/06/$20.00
©)2006 IEEE
3814
ISCAS 2006
So the filter's transform function is unchanged while all internal nodes have gained less than 1. Finally, keeping the bias voltage unchanged, we scale up/down the size of each transistors of the unit transconductor and each caps to make the noise performance meet the specification. By such a strategy, we have defined the Gm=8OuS with the help of simulator. The simulation results of the final unit transconductor is shown in Fig.4, from which we can see the Gm can be tuned from 4OuS to 120uS by VCTL, so the process derivation of the cap can be completely
which is combined by the same unit transconductor, is reshaped by a hysteresis comparator, and then compared with a reference by PFD. The PFD generates a pulse sequence to drive the charge pump, whose output filtering by a loop filter is the frequency control signal both for VCO and the slave filter.
T
compensated.
V-AA
S-A
WTL Mu
M12
M13
M14
M21
M22
-
M24
M23
vip~~~~~~~~~~~~~~~~~2
Fig.5 The output stage Fig.3 Linear input stage with dual differential ports I
6l
I' Oi
+
4~~~~~~~~~~~~~LJ~~~~ ~ ~
~
1k
IMI
~~~~ 0
tri Wu~~~~~ i -O
1
"[V-
-Fig.6 Gain and phase of the unit transconductor
Fig.4 Simulation results of the transconductance with differentVCTL frqec uig fo used o 31Teotu is~~~~~1
c,
The output stage of the transconductor is shown in
Fig. 5, where Acm is a common mode feedback amplifier, Using the cascode structure with gain boost, the transconductor have a high dc gain. The simulated frequency response of the unit transconductor with a 0.5pF cap load is shown in Fig.6, from which we can see the phase shift is almost 90' between 100OKHz to 10OMHz. IV.
FREQUENcy TUNNG
deigedI hi dsin aPL, hchisshw i Fg.7
FogodmthnbewntefieradheVOte
~~~~~~~~~oscillation
Fg 1 amplitude has to be limited to the linear range of the transconductor. In this design, the ring VCO shown 3815,. the oscillation amplitude X,1 in Fig. 8 is used, is limited to 300mv by the nonlinear element shown in Fig. [4], which is combined by a linear active positive resistor and a nonlinear active negative resistor. I-V characteristic of the nonlinear element is shown in Fig. 10. To avoid the VCO disturbing the filter while keeping good matching properties, the oscillation frequency is set to 4MHz, which is the first zero of the filter. To avoid dead zone, the PFD given in Mijuskovic's yaper [5] and the charge 9
resut o th contrl ignal generate by PLL,- isshow inn
reference
rnveriter Charge
.
Pump
PFD
V
J25
4
vCo Toi~e
Cotrl
|~ ~~~~~~~~~~ based on PLL Fig.7 Frequency tuning loop
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ I II
Fig. I Simu ation result ofthe contol signa R
R
EXPERIMENTAL RESULTS ~~~~~~~~V. The filter has been fabricated in O.25um CMOS process.
The microphotograph of the chip is shown in Fig.12, it integrates two identical filters for I/Q path, a common automatic frequency tuning circuit, and some buffers for test M~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~* 1 1 The whole die area is 1I.0x2.O m2 Fig.8 The ring VCO N. K purpose. l~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Gm
Fig.9 Nonlinear element
Fig.12 Die Photograph of the filter Testing setup for the filter is shown in Fig. 13. The singleended input signal is converted to the differential signal by MAX4416 (a dual wideband opamp by Maxim), which is fed to the filter. The differential output signal of the filter is converted to single-ended signal by MAX44t12 (a single wideband opamp by Maxim) for test purpose.
Fig.12 Tesing bhoaordp for the filter Vin
Fl;.9 Nonlmear ele3816 V
Fig.10 I-V characteristic of the nonlinear element
R I
1
2
N
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Fig. 14 shows the measured transfer function of the filter with reference frequency change from 2.0MHz to 4.5MHz. The pass band ripple is about 1 dB, which is large than the expected 0.5dB. The reason is that the output impedance of the transconductor is lower than expected. The dashed line is the simulated S21 with 4MHz reference signal. The accuracy of frequency characteristic within the first zero is less than 1%, but the accuracy at second zero is bad. It's mean that the minimum cap is somewhat small.
in Table 1. o
i
_
S
Slitah
fref=2.5Mhz
l-X--\--t~~~--t------------=----------=----10t
L
a. fref=32Mhz ----
-~-~~W ~~~\
E
-- rSiluatio Resut w fr f=4 OMHz
0
-20 -------
a
ti P 2 S ---|v------------
-
|
hz fref=4M0hz
., C3 liXit:, .ftef=4~51Ahz
1
Fig.16 Measured output noise REFERENCES
0 --
-770-------------------7---------------------------------
0.2
004
--
'----7
_____
0
Su, Y. Sun, and R. Gordon, "Performance analysis and comparison of high-frequency CMOS OTA-C filters", IEE on Analog Signal Processing, Oxford, UK, 1st Nov. ov nalo-S ignl-P roc ssing, xford-U K,-1t-NSymposium -------------------------------------Ssium-o-A ym
-------m ----------------
0.6
0.8
____
_____
1
frequency
_____
1 2
____
1.
_____
1.6
[1]
--
2000, pp. 8/1-8/7
-~
1 8
x
H. W.
2
[2] S. Szczepanski, J. Jakusz and R. Schaumann, "A linear CMOS OTA
10&
for VHF applications", IEEE International Symposium on ISCAS,
Fig.14 Measured S21 with different reference freq.
[3]
The measured output spectrum of the filter with 1OOKHz input signal is shown in Fig.15. The power of 1s' harmonic is OdBm, while the power of 2nd and 3rd harmonic are -58dBm and -46.5dBm respectively, So the THD is about 0.7%. Fig.16 shows the output spectrum of the filter without input signal, which is measured with RBW=IOKHz. The in-band noise density is about -80 dBm, while the out-band is about -90dBm, so the integral noise power within 4MHz is about -54dBm, and the DR=54dBm. The summarized measured results are listed a .S;7 d 6
1995(2): 1344-1347.
H. Khorramabadi and P. R. Gray, "High-frequency CMOS continuous-time filters", IEEE J. Solid-State Circuits, 1984(19): 939-
948.
[4] F. Krummenacher and N. Joehl, "A 4MHz CMOS continuous-time
filter with on-chip automatic tuning", IEEE J. Solid-State Circuits,
1988(23):
750-758. [5] D. Mijuskovic, et al., "Cell-based fully integrated CMOS frequency synthesizers", IEEE J. Solid-State Circuits, 1994(29): 271-279.
[6] I. A. Young, et al., "A PLL clock generator with 5 to 110 MHz of lock range for microprocessors", IEEE J. Solid-State Circuits, 1992(27): 1599-1607. Process Die area
Vdd
TSMC 0.25um 1.0 X2.0 mm (dual) 3.3V 13mA
Idd Cutoff Freq. 4MHz Stop band Atten. -40dB In-band noise -54dBm(
Department of Electronic Engineering Tsinghua University, Beijing, China
yaojkO0gmails.tsinghua.edu.cn
Baoyong Chi
Institute of Microelectronics Tsinghua University, Beijing, China
chibylxcgmails.tsinghua.edu.cn
Abstract A fifth-order elliptic low-pass Gm-C filter used in monolithic DAB receiver is presented, the filter integrates an on-chip frequency automatic tuning circuit based on PLL to control the cutoff frequency. The filter has been implemented in 0.25um CMOS process. The measurement results show that the frequency tuning error is within 1%, the dynamic range is
Zhihua Wang
Institute of Microelectronics Tsinghua University, Beijing, China
zhihuagtsinghua.edu.cn
performance and different accuracy. Among these methods, the filter with leapfrog structure could achieve the lowest sensitivity and the best DR performance [1], so it's adopted in this design. The state equations of the ladder filter shown in Fig. 1 can be listed using the current through the inductors and the voltage at the grounded cap
54dB, the stop-band rejection rate is greater than 40dB. The filte dras l3A curentfrom 3.3 powr suply.as the state
variables. After some conversions, a group of new state equations, which uses only voltage variables and has no differential operations, can be listed. When the GmC integrators have been used to realize the integration operations of the new state equations, a leapfrog filter with the same transfer function can be got, which is shown in Fig.2. To get higher tuning accuracy, the trans-conductors used in the filter are identical.
I. INTRODUCTION The continuous-time filter is one of the key modules in the monolithic receiver, and is often the bottleneck to implement the monolithic receiver. The low-pass filter presented in the paper is designed for L-band DAB (Digital Audio Broadcast) application, and must satisfy the following requirements: the pass band (0-3MHz) ripple is smaller than 0.5dB, the attenuation beyond 4MHz is higher than 40dB, the THD is less than 1% when Vpp=600mV, and the DR (dynamic range) is larger than 50dB.
Among the filter topologies, the elliptic topology could realize the required stop band attenuation with the minimum order, so the elliptic topology is selected for our filter. With the help of the filter synthesis software, the ladder filter prototype is deduced from the specifications and is shown in Fig. 1. 54 13nNH 37 4On
4336 rF
1471nF
1 UU. 1 n[
78.81 n
G,,G,,
Fig.2 A 5th order Gm-C leapfrog elliptic LPF
FILTER TOPOLOGY
II.
60.52nF
G
Fig.1 The ladder filter prototype High order filters based on the integrators could be constructed using the different methods. Different constructed methods would result in different DR
III. THE DESIGN OF THE LINEAR TRANSCONDUCTOR In this design, the linear input stage presented in Szczepanski's paper [2] is adopted. To add voltages at the input port, Fig.3 uses the dual port input stage, whereVCTL is a tunable floating voltage source. The transconductance of the transconductor is it can be controlled
[tCOX(W/L)VcTL,
efficiently by VCTL. The integrators time constants C/Gm
are defined by the transform function, but the values of the Gm could be selected freely. In this design, the Gm is defined through such a strategy: first, a unit transconductor with Gm=50uS is designed. After optimizing the bias current and the transistor size, the unit transconductor achieves less than 0.5°0 THD when Vpp=600mv. The filter is based on the unit transconductor. Then, the gain at the internal nodes is checked, when the gain is large than 1, we increase the grounded cap at integral times until the gain is less than 1, and then increase all the unit transconductors whose input ports be connected to the node, at the same times by shunt.
This research was partly supported by the National Science Foundation (No.60475018, No. 90407006)
0-7803-9390-2/06/$20.00
©)2006 IEEE
3814
ISCAS 2006
So the filter's transform function is unchanged while all internal nodes have gained less than 1. Finally, keeping the bias voltage unchanged, we scale up/down the size of each transistors of the unit transconductor and each caps to make the noise performance meet the specification. By such a strategy, we have defined the Gm=8OuS with the help of simulator. The simulation results of the final unit transconductor is shown in Fig.4, from which we can see the Gm can be tuned from 4OuS to 120uS by VCTL, so the process derivation of the cap can be completely
which is combined by the same unit transconductor, is reshaped by a hysteresis comparator, and then compared with a reference by PFD. The PFD generates a pulse sequence to drive the charge pump, whose output filtering by a loop filter is the frequency control signal both for VCO and the slave filter.
T
compensated.
V-AA
S-A
WTL Mu
M12
M13
M14
M21
M22
-
M24
M23
vip~~~~~~~~~~~~~~~~~2
Fig.5 The output stage Fig.3 Linear input stage with dual differential ports I
6l
I' Oi
+
4~~~~~~~~~~~~~LJ~~~~ ~ ~
~
1k
IMI
~~~~ 0
tri Wu~~~~~ i -O
1
"[V-
-Fig.6 Gain and phase of the unit transconductor
Fig.4 Simulation results of the transconductance with differentVCTL frqec uig fo used o 31Teotu is~~~~~1
c,
The output stage of the transconductor is shown in
Fig. 5, where Acm is a common mode feedback amplifier, Using the cascode structure with gain boost, the transconductor have a high dc gain. The simulated frequency response of the unit transconductor with a 0.5pF cap load is shown in Fig.6, from which we can see the phase shift is almost 90' between 100OKHz to 10OMHz. IV.
FREQUENcy TUNNG
deigedI hi dsin aPL, hchisshw i Fg.7
FogodmthnbewntefieradheVOte
~~~~~~~~~oscillation
Fg 1 amplitude has to be limited to the linear range of the transconductor. In this design, the ring VCO shown 3815,. the oscillation amplitude X,1 in Fig. 8 is used, is limited to 300mv by the nonlinear element shown in Fig. [4], which is combined by a linear active positive resistor and a nonlinear active negative resistor. I-V characteristic of the nonlinear element is shown in Fig. 10. To avoid the VCO disturbing the filter while keeping good matching properties, the oscillation frequency is set to 4MHz, which is the first zero of the filter. To avoid dead zone, the PFD given in Mijuskovic's yaper [5] and the charge 9
resut o th contrl ignal generate by PLL,- isshow inn
reference
rnveriter Charge
.
Pump
PFD
V
J25
4
vCo Toi~e
Cotrl
|~ ~~~~~~~~~~ based on PLL Fig.7 Frequency tuning loop
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ I II
Fig. I Simu ation result ofthe contol signa R
R
EXPERIMENTAL RESULTS ~~~~~~~~V. The filter has been fabricated in O.25um CMOS process.
The microphotograph of the chip is shown in Fig.12, it integrates two identical filters for I/Q path, a common automatic frequency tuning circuit, and some buffers for test M~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~* 1 1 The whole die area is 1I.0x2.O m2 Fig.8 The ring VCO N. K purpose. l~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Gm
Fig.9 Nonlinear element
Fig.12 Die Photograph of the filter Testing setup for the filter is shown in Fig. 13. The singleended input signal is converted to the differential signal by MAX4416 (a dual wideband opamp by Maxim), which is fed to the filter. The differential output signal of the filter is converted to single-ended signal by MAX44t12 (a single wideband opamp by Maxim) for test purpose.
Fig.12 Tesing bhoaordp for the filter Vin
Fl;.9 Nonlmear ele3816 V
Fig.10 I-V characteristic of the nonlinear element
R I
1
2
N
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Fig. 14 shows the measured transfer function of the filter with reference frequency change from 2.0MHz to 4.5MHz. The pass band ripple is about 1 dB, which is large than the expected 0.5dB. The reason is that the output impedance of the transconductor is lower than expected. The dashed line is the simulated S21 with 4MHz reference signal. The accuracy of frequency characteristic within the first zero is less than 1%, but the accuracy at second zero is bad. It's mean that the minimum cap is somewhat small.
in Table 1. o
i
_
S
Slitah
fref=2.5Mhz
l-X--\--t~~~--t------------=----------=----10t
L
a. fref=32Mhz ----
-~-~~W ~~~\
E
-- rSiluatio Resut w fr f=4 OMHz
0
-20 -------
a
ti P 2 S ---|v------------
-
|
hz fref=4M0hz
., C3 liXit:, .ftef=4~51Ahz
1
Fig.16 Measured output noise REFERENCES
0 --
-770-------------------7---------------------------------
0.2
004
--
'----7
_____
0
Su, Y. Sun, and R. Gordon, "Performance analysis and comparison of high-frequency CMOS OTA-C filters", IEE on Analog Signal Processing, Oxford, UK, 1st Nov. ov nalo-S ignl-P roc ssing, xford-U K,-1t-NSymposium -------------------------------------Ssium-o-A ym
-------m ----------------
0.6
0.8
____
_____
1
frequency
_____
1 2
____
1.
_____
1.6
[1]
--
2000, pp. 8/1-8/7
-~
1 8
x
H. W.
2
[2] S. Szczepanski, J. Jakusz and R. Schaumann, "A linear CMOS OTA
10&
for VHF applications", IEEE International Symposium on ISCAS,
Fig.14 Measured S21 with different reference freq.
[3]
The measured output spectrum of the filter with 1OOKHz input signal is shown in Fig.15. The power of 1s' harmonic is OdBm, while the power of 2nd and 3rd harmonic are -58dBm and -46.5dBm respectively, So the THD is about 0.7%. Fig.16 shows the output spectrum of the filter without input signal, which is measured with RBW=IOKHz. The in-band noise density is about -80 dBm, while the out-band is about -90dBm, so the integral noise power within 4MHz is about -54dBm, and the DR=54dBm. The summarized measured results are listed a .S;7 d 6
1995(2): 1344-1347.
H. Khorramabadi and P. R. Gray, "High-frequency CMOS continuous-time filters", IEEE J. Solid-State Circuits, 1984(19): 939-
948.
[4] F. Krummenacher and N. Joehl, "A 4MHz CMOS continuous-time
filter with on-chip automatic tuning", IEEE J. Solid-State Circuits,
1988(23):
750-758. [5] D. Mijuskovic, et al., "Cell-based fully integrated CMOS frequency synthesizers", IEEE J. Solid-State Circuits, 1994(29): 271-279.
[6] I. A. Young, et al., "A PLL clock generator with 5 to 110 MHz of lock range for microprocessors", IEEE J. Solid-State Circuits, 1992(27): 1599-1607. Process Die area
Vdd
TSMC 0.25um 1.0 X2.0 mm (dual) 3.3V 13mA
Idd Cutoff Freq. 4MHz Stop band Atten. -40dB In-band noise -54dBm(
