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Analogue Coursework — Part 1 Design of a JFET/BJT common-drain / common-emitter cascade amplifier with an approximate 3dB low-frequency cut-off of 50Hz.
COURSE: MODULE: BY: DATE:
BEng (HONS) Electronic Systems EEE508J1 - Electronic Circuit Design Colin K McCord 10/11/2001
Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
CONTENTS
(a) Design a JFET/BJT common-drain / common-emitter cascade amplifier
(b) Estimate the input resistance, the output resistance and the voltage gain
Pages 1 to 3
Page 4
(c) Draw a high-frequency equivalent circuit and estimate 3dB high-frequency cut-off
Pages 5 to 6
(d) Simulation of circuit and comparison of results with calculated / designed values
Pages 7 to 13
Appendix 1 – PSpice Output File
Pages 14 to 17
Appendix 2 – JFET 2N3819 Datasheet
Pages 18 to 22
Appendix 3 – BJT 2N2222 Datasheet
Pages 23 to 27
EEE508J1 – Electronic Circuit Design
98425145
Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
(a) Design a JFET/BJT common-drain / common-emitter cascade amplifier Using a 15V power supply, with an approximate 3dB low-frequency cut-off of 50Hz. The amplifier input is capacitive coupled to a 10KΩ source and the output is capacitive coupled to a 1kΩ load. Transistors J2N3819 and Q2N2222 are available in the circuit simulation package PSpice. Circuit diagram shown below (resistor and capacitor values will be calculated): +15V
R1
RC
C2
J1 C1 J2N3819 Q1 Q2N2222 R R2
V
RL
RS
RE
CE
Available transistors have the following parameter values (from datasheets): J2N3819 IDSS = 10mA |Vp| = 3V
Note:
Q2N2222 VA = 74V hfe = β = 150
VCC = 15V RL = 1KΩ R = 10KΩ 3dB low-frequency cut-off of 50Hz
Resistor design by inspection
Let
ID =
IDSS 10 × 10 −3 = = 2.5mA 4 4
EEE508J1 – Electronic Circuit Design
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Thursday, 17 July 2003
VGS =
Vp 2
=
Analogue Coursework – Part 1
Colin K McCord
−3 = −1.5V 2
Let
IC = 1mA
Let
VG =
Let
R2 = 500K => R1 = 1MΩ
VCC 15 = = 5V 3 3
VS = VG + |VGS| = 5 + 1.5 = 6.5V
RS =
VS 6.5 = = 2.6 × 103 = 2.6KΩ ID 2.5 × 10−3
VE = VS – 0.7 = 6.5 – 0.7 = 5.8V
Let
VC =
2VCC = 10V 3
RE =
VE 5.8 = = 5.8 × 103 = 5.8KΩ IC 1× 10 −3
RC =
VCC − VC 15 − 10 = = 5KΩ IC 1mA
Capacitor design using method of short-circuit timer constants f = 50Hz Using the method of short-circuit time constants, the low-frequency cut-off ωL is given by 1.15ϖ L ≈
N
1
∑C R i =1
i
is
=
3
τ
Since this expression is generally accurate, whether or not a dominant pole exists, it is convenient to make the entire time-constants equal, so that each capacitor plays and equal role in determining the 3dB cut-off frequency. Let the time-constant be donated by τ .
ϖ L = 2π f = 2π 50 = 100π
τ=
3 = 8.30374 × 10−3 1.15 × 100π
Design of C1
C1 “sees” resistance R and Rin. Rin = R1 || R2 =
500K × 1M 500 × 109 = = 333.33KΩ 500K + 1M 1.5 × 106
EEE508J1 – Electronic Circuit Design
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Thursday, 17 July 2003
Analogue Coursework – Part 1
τ
C1 =
R + Rin
Colin K McCord
8.3 × 10−3 = 24.1983 × 10 −9 = 24.2nF 10K + 333K
=
Design of C2
C2 “sees” resistance RO and RL.
rO =
RO = RC || rO
RO = 5K || 74K =
τ
C2 =
=
RO + RL
VA 74 = = 74KΩ IC 1× 10 −3
5K × 74K 370 × 106 = = 4.68354 × 103 = 4.68KΩ 3 5K + 74K 79 × 10
8.3 × 10−3 8.3 × 10 −3 = = 1.46127 × 10 −6 = 1.46µF 4.68K + 1K 5.68 × 103
Design of CE R CE “sees” resistance RE || re + oi . β
Roi = RS ||
1 gm
Roi = 2.6K ||
re =
gm =
1 3.3333 × 10−3
=
2IDSS Vp
ID IDSS
=
2 × 10 × 10−3 3
2.5 × 10 −3 10 × 10−3
= 3.3333 × 10−3 = 3.333mA/V
2.6K × 300 780 × 103 = = 268.966 = 268.97Ω 2.6K + 300 2.9 × 103
25mV 25 × 10 −3 = = 25Ω IE 1× 10−3
R 268.97 5.8K × 26.79 RE || re + oi = 5.8K || 25 + = 26.6699Ω = 5.8K || 26.79 = β 150 5.8K + 26.79
CE =
τ 33.802
=
8.3 × 10−3 = 311.212 × 10−6 = 311.21µ F 26.6699
EEE508J1 – Electronic Circuit Design
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Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
(b) Estimate the input resistance, the output resistance and the voltage gain Rin 2 = β re = 150 × 25 = 3.75KΩ
VS RS || Rin 2 = Vg {RS || Rin 2 } +
Vg V
=
1 gm
=
2.6K || 3.75K 1.53543 × 103 = = 0.836551 {2.6K || 3.75K} + 300 1.83543 × 103
333.33 × 103 333.33 Rin = = = 0.99226 RS + Rin 2.6 × 103 + 333.33 × 103 335.93
VO RC || RL || rO 5K || 1K || 74K 824.053 = = = = 32.9621 = 33 VS re 25 25
VO VS Vg VO = × × = 0.836551× 0.99226 × 32.9621 = 27.3611 V Vg V VS
Voltage gain =
VO = 27.36 V
Input resistance (Rin) was calculated during the design of C1: Rin = 333.33KΩ Output resistance (RO) was calculated during the design of C2: RO = 4.68 KΩ
EEE508J1 – Electronic Circuit Design
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98425145
Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
(c) Draw a high-frequency equivalent circuit and estimate 3dB high-frequency cut-off Neglecting rX and Cgs, high frequency equivalent for the cascade amplifier circuit is: Roi
RL||Rc ||r o
A1
A2
R ßre
Cgd
Rin
Cp
A2 + 1 Cµ A2
(1+A2 )Cµ
V
R’
C’’
R’’
R’’’
Transistors have the following parameter values (from PSpice output file): -
J2N3819 Cgd = 671 x 10-15 = 0.671pF gm = 3.68 x 10-3
Q2N2222 Cµ = 4.11 x 10-12 = 4.11pF Cπ = 52.5 x 10-12 = 52.5pF FT = 111 x 106 = 111MHz rX = 10Ω rO = 75.6 x 103 = 75.6kΩ
We have all the values contained within the equation: fT =
1 2π re Cµ + Cπ
(
)
Let’s test this equation, put values Cµ, Cπ and re into equation and compare calculated fT with the value of fT contained in the PSpice output file. fTCAL =
(
2π 25 4.11× 10
1 −12
+ 52.5 × 10
−12
)
=
1 8.89228 × 10 −9
= 112.457 × 106 = 112.5MHz
It’s clear that the equation above for working out fT offers an extremely good approximation, as there was only difference of 1.313% between the calculated value and the PSpice value.
Calculation of fn1 R ' = Rin || R = 333.33K || 10K =
fn1 =
333.33 × 103 × 10 × 103 333.33 × 103 + 10 × 103
=
3.3333 × 109 343.33 × 103
= 9.70874 × 103 = 9.709KΩ
1 1 1 = = = 24.4306 × 106 = 24.43MHz 2π R ' Cgd 2π 9.709 × 103 × 671× 10−15 40.9322 × 10 −9
EEE508J1 – Electronic Circuit Design
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Analogue Coursework – Part 1
Colin K McCord
Calculation of fn2 Roi = RS ||
1 1 = 2.6K || = 2.6K || 271.739 = 246.026 = 246Ω gm 3.68 × 10−3
R '' = Roi || β re = 246.026 || 3750 =
246.026 × 3750 = 230.879Ω 246.026 + 3750
A2 = 32.96
(
(
)
)
C '' = Cπ || (1 + A2 )Cµ = Cπ + (1 + A2 )Cµ = 52.5 × 10−12 + (1 + 32.96 ) 4.11× 10 −12 = 192.076 × 10 −12 fn 2 =
1 1 1 = = = 3.58891× 106 = 3.6MHz 2π R '' C '' 2π 230.879 × 192.076 × 10−12 278.634 × 10−9
Calculation of fn3 R ''' = RL || RC || rO = 1K || 5K || 75.6K =
fn 3 =
1 2π R '''
A2 +1 Cµ A2
=
1 = 824.248Ω 1 1 1 + + 1× 103 5 × 103 75.6 × 103
1 2π × 824.248 × 33.96 × 4.11× 10 −12 32.96
=
1 21.9311× 10−9
= 45.5974 × 106 = 45.6MHz
Calculation of 3dB high-frequency cut-off (fn)
Clearly a dominant pole exists at fn2 and we can write: fn ≈ 3.6Mhz 1.15 1 1 1 = + + fn fn1 fn 2 fn3 1.15 1 1 1 = + + fn 24.4M 3.6M 45.6M fn =
1.15 1.15 = = 3.37549 × 106 = 3.4MHz −9 1 1 1 × 340.691 10 + + 24.4M 3.6M 45.6M
EEE508J1 – Electronic Circuit Design
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98425145
Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
(d) Simulation of circuit and comparison of results with calculated / designed values Using PSpice circuit simulation package, screen dump of circuit shown below: -
Setup simulator for an “AC sweep” and “bias point detail”: -
Configure “AC Sweep”: -
EEE508J1 – Electronic Circuit Design
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Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
The graph below is the result of simulating the circuit under specified conditions: -
Voltage Gain =
VMAX 13.44 = = 26.88 V .5
Voltage Gain (dB) = 20log(26.88) = 28.5886dB 3dB Voltage Gain (dB) = Voltage Gain (dB) - 3 = 28.5886 - 3 = 25.5886dB
3dB Voltage Gain = 10
25.5886 20
= 19.0296
3dB Voltage = 3dB Voltage Gain × V = 19.0296 × .5 = 9.51479V Using “Probe Cursor”, get “low frequency cut-off”, “high frequency cut-off” and “Bandwidth”: -
Low frequency cut-off ≈ 38.009Hz High frequency cut-off ≈ 3.7078MHz Bandwidth ≈ 3.7078MHz This is not the only way of getting “Low frequency cut-off”, “high frequency cut-off” and “Bandwidth using PSpice. A simpler way is to used the “Goal Functions” feature of PSpice, e.g. bring up the “Goal Functions” dialogue box from Menu item [Trace] [Goal Functions] and select the “Bandwidth” goal function. Screen dump of dialogue box shown below: -
EEE508J1 – Electronic Circuit Design
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Analogue Coursework – Part 1
Colin K McCord
Click the [Eval] button and the following will appear: -
Select the trace and enter 3dB then click OK, the following will appear: -
EEE508J1 – Electronic Circuit Design
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Analogue Coursework – Part 1
Colin K McCord
Screen dump of PSpice with bias voltage display enabled: -
Screen dump of PSpice with bias current display enabled: -
EEE508J1 – Electronic Circuit Design
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Analogue Coursework – Part 1
Colin K McCord
Using electronic workbench to measure input resistance (note: capacitors are short-circuited): -
Using electronic workbench to measure output resistance (note: capacitors are short-circuited): -
EEE508J1 – Electronic Circuit Design
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Analogue Coursework – Part 1
Colin K McCord
Comparison Table Design / Calculated Value 2.5mA 1mA 2.5mA 1mA 5V -1.5V 6.5V 5.8V 10V 3.33mA/V 74kΩ 333.33KΩ 4.68kΩ 112.457MHz 50Hz 3.4MHz 27.36
ID IC IS IE VG VGS VS VE VC gm ro Rin RO fT Low Frequency Cut-off High Frequency Cut-off Voltage Gain
Simulated Value
Difference
% Difference
2.55mA 1.022mA 2.543mA 1.029mA 5V -1.61V 6.612V 5.967V 9.89V 3.68mA/V 75.6kΩ 333.3kΩ 5kΩ 111MHz 38.01Hz 3.708MHz 26.88
0.05mA 0.022mA 0.043mA 0.029mA 0.00V 0.11V 0.112V 0.167V 0.11V 0.350mA/V 1.6KΩ 0.00kΩ 0.32kΩ 1.457MHz 11.99Hz 0.308MHz 0.48
2.00% 2.20% 1.72% 2.90% 0.00% 7.33% 1.72% 2.88% 1.11% 10.51% 2.15% 0.00% 6.84% 1.31% 31.54% 9.06% 1.79%
Conclusions
Simulated voltages (VG,VS, VE, VC) and currents (ID, IC, IS, IE) were extremely close (
COURSE: MODULE: BY: DATE:
BEng (HONS) Electronic Systems EEE508J1 - Electronic Circuit Design Colin K McCord 10/11/2001
Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
CONTENTS
(a) Design a JFET/BJT common-drain / common-emitter cascade amplifier
(b) Estimate the input resistance, the output resistance and the voltage gain
Pages 1 to 3
Page 4
(c) Draw a high-frequency equivalent circuit and estimate 3dB high-frequency cut-off
Pages 5 to 6
(d) Simulation of circuit and comparison of results with calculated / designed values
Pages 7 to 13
Appendix 1 – PSpice Output File
Pages 14 to 17
Appendix 2 – JFET 2N3819 Datasheet
Pages 18 to 22
Appendix 3 – BJT 2N2222 Datasheet
Pages 23 to 27
EEE508J1 – Electronic Circuit Design
98425145
Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
(a) Design a JFET/BJT common-drain / common-emitter cascade amplifier Using a 15V power supply, with an approximate 3dB low-frequency cut-off of 50Hz. The amplifier input is capacitive coupled to a 10KΩ source and the output is capacitive coupled to a 1kΩ load. Transistors J2N3819 and Q2N2222 are available in the circuit simulation package PSpice. Circuit diagram shown below (resistor and capacitor values will be calculated): +15V
R1
RC
C2
J1 C1 J2N3819 Q1 Q2N2222 R R2
V
RL
RS
RE
CE
Available transistors have the following parameter values (from datasheets): J2N3819 IDSS = 10mA |Vp| = 3V
Note:
Q2N2222 VA = 74V hfe = β = 150
VCC = 15V RL = 1KΩ R = 10KΩ 3dB low-frequency cut-off of 50Hz
Resistor design by inspection
Let
ID =
IDSS 10 × 10 −3 = = 2.5mA 4 4
EEE508J1 – Electronic Circuit Design
Page 1
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Thursday, 17 July 2003
VGS =
Vp 2
=
Analogue Coursework – Part 1
Colin K McCord
−3 = −1.5V 2
Let
IC = 1mA
Let
VG =
Let
R2 = 500K => R1 = 1MΩ
VCC 15 = = 5V 3 3
VS = VG + |VGS| = 5 + 1.5 = 6.5V
RS =
VS 6.5 = = 2.6 × 103 = 2.6KΩ ID 2.5 × 10−3
VE = VS – 0.7 = 6.5 – 0.7 = 5.8V
Let
VC =
2VCC = 10V 3
RE =
VE 5.8 = = 5.8 × 103 = 5.8KΩ IC 1× 10 −3
RC =
VCC − VC 15 − 10 = = 5KΩ IC 1mA
Capacitor design using method of short-circuit timer constants f = 50Hz Using the method of short-circuit time constants, the low-frequency cut-off ωL is given by 1.15ϖ L ≈
N
1
∑C R i =1
i
is
=
3
τ
Since this expression is generally accurate, whether or not a dominant pole exists, it is convenient to make the entire time-constants equal, so that each capacitor plays and equal role in determining the 3dB cut-off frequency. Let the time-constant be donated by τ .
ϖ L = 2π f = 2π 50 = 100π
τ=
3 = 8.30374 × 10−3 1.15 × 100π
Design of C1
C1 “sees” resistance R and Rin. Rin = R1 || R2 =
500K × 1M 500 × 109 = = 333.33KΩ 500K + 1M 1.5 × 106
EEE508J1 – Electronic Circuit Design
Page 2
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Thursday, 17 July 2003
Analogue Coursework – Part 1
τ
C1 =
R + Rin
Colin K McCord
8.3 × 10−3 = 24.1983 × 10 −9 = 24.2nF 10K + 333K
=
Design of C2
C2 “sees” resistance RO and RL.
rO =
RO = RC || rO
RO = 5K || 74K =
τ
C2 =
=
RO + RL
VA 74 = = 74KΩ IC 1× 10 −3
5K × 74K 370 × 106 = = 4.68354 × 103 = 4.68KΩ 3 5K + 74K 79 × 10
8.3 × 10−3 8.3 × 10 −3 = = 1.46127 × 10 −6 = 1.46µF 4.68K + 1K 5.68 × 103
Design of CE R CE “sees” resistance RE || re + oi . β
Roi = RS ||
1 gm
Roi = 2.6K ||
re =
gm =
1 3.3333 × 10−3
=
2IDSS Vp
ID IDSS
=
2 × 10 × 10−3 3
2.5 × 10 −3 10 × 10−3
= 3.3333 × 10−3 = 3.333mA/V
2.6K × 300 780 × 103 = = 268.966 = 268.97Ω 2.6K + 300 2.9 × 103
25mV 25 × 10 −3 = = 25Ω IE 1× 10−3
R 268.97 5.8K × 26.79 RE || re + oi = 5.8K || 25 + = 26.6699Ω = 5.8K || 26.79 = β 150 5.8K + 26.79
CE =
τ 33.802
=
8.3 × 10−3 = 311.212 × 10−6 = 311.21µ F 26.6699
EEE508J1 – Electronic Circuit Design
Page 3
98425145
Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
(b) Estimate the input resistance, the output resistance and the voltage gain Rin 2 = β re = 150 × 25 = 3.75KΩ
VS RS || Rin 2 = Vg {RS || Rin 2 } +
Vg V
=
1 gm
=
2.6K || 3.75K 1.53543 × 103 = = 0.836551 {2.6K || 3.75K} + 300 1.83543 × 103
333.33 × 103 333.33 Rin = = = 0.99226 RS + Rin 2.6 × 103 + 333.33 × 103 335.93
VO RC || RL || rO 5K || 1K || 74K 824.053 = = = = 32.9621 = 33 VS re 25 25
VO VS Vg VO = × × = 0.836551× 0.99226 × 32.9621 = 27.3611 V Vg V VS
Voltage gain =
VO = 27.36 V
Input resistance (Rin) was calculated during the design of C1: Rin = 333.33KΩ Output resistance (RO) was calculated during the design of C2: RO = 4.68 KΩ
EEE508J1 – Electronic Circuit Design
Page 4
98425145
Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
(c) Draw a high-frequency equivalent circuit and estimate 3dB high-frequency cut-off Neglecting rX and Cgs, high frequency equivalent for the cascade amplifier circuit is: Roi
RL||Rc ||r o
A1
A2
R ßre
Cgd
Rin
Cp
A2 + 1 Cµ A2
(1+A2 )Cµ
V
R’
C’’
R’’
R’’’
Transistors have the following parameter values (from PSpice output file): -
J2N3819 Cgd = 671 x 10-15 = 0.671pF gm = 3.68 x 10-3
Q2N2222 Cµ = 4.11 x 10-12 = 4.11pF Cπ = 52.5 x 10-12 = 52.5pF FT = 111 x 106 = 111MHz rX = 10Ω rO = 75.6 x 103 = 75.6kΩ
We have all the values contained within the equation: fT =
1 2π re Cµ + Cπ
(
)
Let’s test this equation, put values Cµ, Cπ and re into equation and compare calculated fT with the value of fT contained in the PSpice output file. fTCAL =
(
2π 25 4.11× 10
1 −12
+ 52.5 × 10
−12
)
=
1 8.89228 × 10 −9
= 112.457 × 106 = 112.5MHz
It’s clear that the equation above for working out fT offers an extremely good approximation, as there was only difference of 1.313% between the calculated value and the PSpice value.
Calculation of fn1 R ' = Rin || R = 333.33K || 10K =
fn1 =
333.33 × 103 × 10 × 103 333.33 × 103 + 10 × 103
=
3.3333 × 109 343.33 × 103
= 9.70874 × 103 = 9.709KΩ
1 1 1 = = = 24.4306 × 106 = 24.43MHz 2π R ' Cgd 2π 9.709 × 103 × 671× 10−15 40.9322 × 10 −9
EEE508J1 – Electronic Circuit Design
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Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
Calculation of fn2 Roi = RS ||
1 1 = 2.6K || = 2.6K || 271.739 = 246.026 = 246Ω gm 3.68 × 10−3
R '' = Roi || β re = 246.026 || 3750 =
246.026 × 3750 = 230.879Ω 246.026 + 3750
A2 = 32.96
(
(
)
)
C '' = Cπ || (1 + A2 )Cµ = Cπ + (1 + A2 )Cµ = 52.5 × 10−12 + (1 + 32.96 ) 4.11× 10 −12 = 192.076 × 10 −12 fn 2 =
1 1 1 = = = 3.58891× 106 = 3.6MHz 2π R '' C '' 2π 230.879 × 192.076 × 10−12 278.634 × 10−9
Calculation of fn3 R ''' = RL || RC || rO = 1K || 5K || 75.6K =
fn 3 =
1 2π R '''
A2 +1 Cµ A2
=
1 = 824.248Ω 1 1 1 + + 1× 103 5 × 103 75.6 × 103
1 2π × 824.248 × 33.96 × 4.11× 10 −12 32.96
=
1 21.9311× 10−9
= 45.5974 × 106 = 45.6MHz
Calculation of 3dB high-frequency cut-off (fn)
Clearly a dominant pole exists at fn2 and we can write: fn ≈ 3.6Mhz 1.15 1 1 1 = + + fn fn1 fn 2 fn3 1.15 1 1 1 = + + fn 24.4M 3.6M 45.6M fn =
1.15 1.15 = = 3.37549 × 106 = 3.4MHz −9 1 1 1 × 340.691 10 + + 24.4M 3.6M 45.6M
EEE508J1 – Electronic Circuit Design
Page 6
98425145
Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
(d) Simulation of circuit and comparison of results with calculated / designed values Using PSpice circuit simulation package, screen dump of circuit shown below: -
Setup simulator for an “AC sweep” and “bias point detail”: -
Configure “AC Sweep”: -
EEE508J1 – Electronic Circuit Design
Page 7
98425145
Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
The graph below is the result of simulating the circuit under specified conditions: -
Voltage Gain =
VMAX 13.44 = = 26.88 V .5
Voltage Gain (dB) = 20log(26.88) = 28.5886dB 3dB Voltage Gain (dB) = Voltage Gain (dB) - 3 = 28.5886 - 3 = 25.5886dB
3dB Voltage Gain = 10
25.5886 20
= 19.0296
3dB Voltage = 3dB Voltage Gain × V = 19.0296 × .5 = 9.51479V Using “Probe Cursor”, get “low frequency cut-off”, “high frequency cut-off” and “Bandwidth”: -
Low frequency cut-off ≈ 38.009Hz High frequency cut-off ≈ 3.7078MHz Bandwidth ≈ 3.7078MHz This is not the only way of getting “Low frequency cut-off”, “high frequency cut-off” and “Bandwidth using PSpice. A simpler way is to used the “Goal Functions” feature of PSpice, e.g. bring up the “Goal Functions” dialogue box from Menu item [Trace] [Goal Functions] and select the “Bandwidth” goal function. Screen dump of dialogue box shown below: -
EEE508J1 – Electronic Circuit Design
Page 8
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Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
Click the [Eval] button and the following will appear: -
Select the trace and enter 3dB then click OK, the following will appear: -
EEE508J1 – Electronic Circuit Design
Page 9
98425145
Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
Screen dump of PSpice with bias voltage display enabled: -
Screen dump of PSpice with bias current display enabled: -
EEE508J1 – Electronic Circuit Design
Page 10
98425145
Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
Using electronic workbench to measure input resistance (note: capacitors are short-circuited): -
Using electronic workbench to measure output resistance (note: capacitors are short-circuited): -
EEE508J1 – Electronic Circuit Design
Page 11
98425145
Thursday, 17 July 2003
Analogue Coursework – Part 1
Colin K McCord
Comparison Table Design / Calculated Value 2.5mA 1mA 2.5mA 1mA 5V -1.5V 6.5V 5.8V 10V 3.33mA/V 74kΩ 333.33KΩ 4.68kΩ 112.457MHz 50Hz 3.4MHz 27.36
ID IC IS IE VG VGS VS VE VC gm ro Rin RO fT Low Frequency Cut-off High Frequency Cut-off Voltage Gain
Simulated Value
Difference
% Difference
2.55mA 1.022mA 2.543mA 1.029mA 5V -1.61V 6.612V 5.967V 9.89V 3.68mA/V 75.6kΩ 333.3kΩ 5kΩ 111MHz 38.01Hz 3.708MHz 26.88
0.05mA 0.022mA 0.043mA 0.029mA 0.00V 0.11V 0.112V 0.167V 0.11V 0.350mA/V 1.6KΩ 0.00kΩ 0.32kΩ 1.457MHz 11.99Hz 0.308MHz 0.48
2.00% 2.20% 1.72% 2.90% 0.00% 7.33% 1.72% 2.88% 1.11% 10.51% 2.15% 0.00% 6.84% 1.31% 31.54% 9.06% 1.79%
Conclusions
Simulated voltages (VG,VS, VE, VC) and currents (ID, IC, IS, IE) were extremely close (
