Analysis and Design of Fully Differential Gain ... - Semantic Scholar
2009 Fifth International Joint Conference on INC, IMS and IDC
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Analysis and Design of Fully Differential Gain-Boosted Op-amp for 14bit 100MS/s Pipelined Analog-to-Digital Converter
Feng Wenxiao, Lu Tiejun, Wang Zongmin Beijing Microelectronics Technology Institute
Beijing, China http://www.DownloadBooks.ir [email protected]
Abstract—This paper presents the analysis and design of high speed, high gain fully differential operational amplifier(opamp). The op-amp is designed for sample and hold circuit of 14 bit 100MS/s pipelined analog-to-digital converter (ADC). Both the main op-amp and the boosting op-amp are fully differential folded-cascode. The main op-amp has a switched capacitance common mode feedback circuit. The boosting op-amp is connected as a follower. The op-amp is designed in 0.18ȝm CMOS process with 3.0V power supply. Spectre simulation shows that the op-amp has the DC gain of 112dB and the unity gain bandwidth of 1.15GHz.
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Keywords- fully differential op-amp; folded cascode; boosting amplifier; pipelined ADC
I. I http://www.DownloadPaper.ir NTRODUCTION
With the development of the wireless communication, high speed and high resolution ADCs are essential and the design of a high performance op-amp is the most important part. Analog and digital circuit integrates onto a single die to reduce system costs, but noisy digital circuit degrades analog performance due to noise injection through power distribution network or the substrate. Fully differential analog signal processing is one of the most important techniques that reduce the problems associated with noise coupling. The fully differential technique doubles the maximum signal swing in the circuit effectively. The op-amp as the most important analog system building block has had to adopt the fully differential design technique. Optimizing circuit for both speed and accuracy leads to contradictory demands [1][2]. High accuracy depends on high dc gain and fast settling requires a high unity-gain frequency. It is difficult to combine high dc gain with high unity-gain frequency in a CMOS op-amp. The structure of a single-stage op-amp is always used to designing high speed op-amps. It mainly has folded-cascode topology and telescopic topology. Compare to telescopic topology, the folded-cascode topology requires more power, but it offers large output swing and has good performance on commonmode input range[3][4]. For high gain, the architecture of a single stage amplifier with gain-boosted amplifier is a nice choice. So it is good to use a folded-cascode structure with gain-boosted amplifier in the sample and hold stage.
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Figure 1. The model of the gain-boosted amplifier
This paper describes the analysis and the design of fully differential gain-boosted op-amp for 14bit 100MS/s pipelined ADC. The organization of this paper is as follows: the model of the gain-boosted amplifier is explained in section Ċ and the circuit implementation with 0.18ȝm CMOS process is presented in section ċ. In section Č, the simulation results are given and discussed .The conclusions are presented in section č. II.
THE MODEL OF THE GAIN-BOOSTED AMPLIFIER
Fig.1 illustrates the model of the gain-boosted amplifier http://www.DownloadMaghale.ir [2]. M1 and M2 form the main cascode amplifier. A is a gain
-boosted amplifier. A drives the gate of M2 and forces the voltage at the drain of M1 and Vref to be equal. Because of the gain-boosted amplifier, voltage variations at the output will affect the voltage at the drain of M1 to a lesser extent variations [4]. As a result, the output resistance is almost A times larger than that of a regular cascode, the output resistance Rout is
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978-0-7695-3769-6/09 $26.00 © 2009 IEEE DOI 10.1109/NCM.2009.133
66
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http://www.DownloadPaper.ir Figure 2. Fully differential folded cascaded op-amp with fully differential gain-boosted amplifiers
Rout
( g m 2 ro 2 ( A 1) 1)ro1 ro 2
According to Rout , the DC gain is
http://www.DownloadEbooks.ir Atot
is
g m1ro1 ( g m 2 ro 2 ( A 1) 1) g m1ro 2
And the DC gain of the amplifier without gain boosting
Atot
g m1ro1 ( g m 2 ro 2 1)
The gain boosting technology makes the DC gain of the circuit increasing several orders of magnitude.
http://www.DownloadMaghale.ir III.
CIRCUIT IMPLEMENTATION
Figure 3. PMOS-input fully differential gain-boosted amplifier(BP)
A. The Op-amp Circuit In Fig.2, a fully differential folded cascode that has two fully differential folded cascode gain-boosted amplifiers has been chosen. Actually, any amplifier can be used as the gain -boosted amplifier. A single transistor is the simplest amplifier. It consumes less power. But for high gain, the
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http://www.DownloadBooks.ir Figure 4. Switched capacitance common mode feedback Figure 5. Nonoverlapping phase clocks Figure 6. Phase margin and AC response of the main op-amp
B. The Design of the CMFB Circuit http://www.FindPdf.ir Fully differential amplifier provides much better rejection of common-mode noise and high-frequency powersupply variations compared to their single-ended counterparts [7]. When the fully differential op-amp is in a feedback configuration like sample and hold circuits, the high differential gain of a fully differential amplifier stabilizes the differential-mode signals within the amplifier, but the common-mode signals can float. It needs an additional common-mode feedback (CMFB) circuit to control the output common-mode voltages. A CMFB circuit averages both differential output voltages to produce a common-mode voltage Vcm. Vcm is then compared to a The desired reference common-mode voltage VCM. difference between Vcm and VCM is amplified and this error voltage is used to change the common-mode feedback voltage of the op-amp to force Vcm and VCM to be equal. CMFB circuits can be divided into two general categories: switched-capacitor CMFB (SC-CMFB) circuits and continuous-time CMFB circuits. Compare to continuoustime CMFB, SC-CMFB consumes less power. Because the op-amp is used in sample and hold circuit, nonoverlapping phase clocks are available. The SC-CMFB is adopted which is shown in Fig.4. It consists of four capacitors and six switches. The size of the capacitors should be chosen carefully so that they will not over-load the main op-amp. The nonoverlapping phase clocks (Fig.5) control the switches on and off. When CLK1 is high , C1 is charge to V C M V B IA S [8] . V is 1.5V. When CLK is high, C and
http://www.DownloadPaper.ir folded cascode amplifiers are usually used for the gainboosted amplifiers. For the input transistors, NMOS means large unity gain bandwidth but low nondominant pole, while PMOS means small unity gain bandwidth but high nondominant pole. So for high phase margin, the main amplifier is with PMOS input transistor. Using a PMOS input also has the shortcomings. PMOS-input requires larger input transistors and higher current to achieve high speed. Boosting stage BP is with PMOS input transistors (Fig.3)[5]. Boosting stage BN is the same as the BP type except that it is with a NMOS input transistors to realize high output impedance. Considering about the stability, the unity-gain frequency ( Z1 ) of the boosting amplifier should not be above the second-pole frequency ( Z p 2 ) of the main amplifier [6].
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CM
2
1
C2 are connected parallel. The DC voltage of C2 is decided by C1 and refreshed every CLK2 period. The gain-boosted op-amp is connected as a follower.
Where £ is the feedback factor and Z p 1 is the unity-gain frequency of the main amplifier. Because the load of the boosting amplifier is smaller than the main amplifier, it is easy to satisfy (4)
http://www.DownloadMaghale.ir
EZ
p1
Z1 Z
p2
IV.
SIMULATION RESULTS
According to the above analysis and design, a fully differential amplifier is designed in a 0.18ȝm CMOS process and simulated with Spectre, with a CM voltage of 1.5V and
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Contact Us: [email protected]
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CONCLUSIONS
This paper presents the analysis and design of fully differential amplifier with gain boosting technology. The gain-boosted amplifier is achieved by using the folded cascode amplifier. Based on 0.18ȝm CMOS process, it has good performance, with a DC gain of 112dB and a unity gain bandwidth of 1.15GHz. The designed op-amp fulfills the stringent specifications of 14bit 100MS/s sample and hold circuit of pipelined ADC. ACKNOWLEDGMENT The authors would like to thank Zhao Yaohua, Xiao http://www.DownloadBooks.ir Du ,Zhang Tieliang , Kong Ying and other members of the
Analog to Digital Converters Group for contributions to this work.
Figure 7. Sample and hold circuit
REFERENCES [1]
TABLE I. DC Gain,(dB) Unity GBW,(GHz) Phase Margin,(deg) Supply Voltage,(V) Load Capacitor,(pF) Settling Time,(ns) Power,(mW)
PERFORMANCE PARAMETERS
This paper 112 1.15 69 3.0 3.0 2.44 19.48
B. Y. Kamath, R. G. Meyer and P. R. Gray, Relationship between frequency response and settling time of operational amplifiers.IEEE J. Solid State Circuits, Vol.Sc-9, No.6,Dec 1974. K. Bult and G. J. G. M. Geelen. A fast-settling cmos op amp for circuits with 90-db dc gain. IEEE J. Solid-State Circuits, vol. 25, pp.1379–1384, Dec. 1990. Yang W㧘 Kelly D 㧘 Mehr I. 㧚 A 3V 340mW 14b 75Msample/s CMOS ADC with 85dB SFDR at Nyquist Input[J]㧚IEEE Journal Solid̅State Circuits㧘2001㧘36(12)㧦1 931-1 936. Razavi B. Design of Analog CMOS Integrated circuits [M]㧚New York㧦McGraw Hill.2001. Yang Bin, Ying Xiumei, Yang Huazhong. A High-Speed HighResolution Sample-and-Hold Circuit[J]. Chinese Journal of Semiconductors.Vol.28, No.10,Oct.2007. Qyvind Berntsen, Carsten Wulff, Trond Ytterdal. High speed, high gain OTA in a digital 90nm CMOS technology[J].NORCHIP,2005. Ojas Choksi, L. Richard Carley. Analysis of Switched-Capacitor Common-Mode Feedback Circuit. IEEE Transations on Circuits and Systems—II: Analog and Digital Signal Processing, VOL. 50, NO. 12, Dec. 2003. H. Recoules, R. Bouchakour, P. Loumeau, F. T. Braz. Two SCCMFB Networks Used in Fully Differential OTA: Measurements and Improvements. Rohana Musa, Yuzman Yusoff, Tan Kong Yew . Design of SingleStage Folded-Cascode Gain Boost Amplifier for 100mW 10-bit 50MS/s Pipelined Analog-to-Digital Converter. ICSE2006 Proc.2006.
http://www.FindPdf.ir
Reference[2] 90 0.116 64 5.0 16 61.5 52
Reference[9] 95 0.412 75 3.0 1.9 7.5 12.8
[2]
[3]
[4] [5]
3pF load capacitor. Fig.6 shows the AC simulation of the main amplifier. The unity GBW is 1.15GHz. The DC gain is more than 112 dB and the phase margin is 69e. The setting behavior of the op-amp is simulated in a closed-loop configuration of sample and hold amplifier (Fig.7).The sample and hold circuit adopts the flip-around structure. The feedback factor £ is nearly 1. This structure consumes low power and has low noise. The whole performances of the op-amp are shown in Table 1. Previous designs are also included [2][9]. From Table 1, we can see that the op-amp proposed in this paper has a higher DC gain, a larger unity GBW and a faster setting time than the other designs.
http://www.DownloadPaper.ir [6]
[7]
[8]
http://www.DownloadEbooks.ir [9]
http://www.DownloadMaghale.ir
http://www.DownloadEbook.ir 69
Contact Us: [email protected]
http://www.GigaPaper.ir
Analysis and Design of Fully Differential Gain-Boosted Op-amp for 14bit 100MS/s Pipelined Analog-to-Digital Converter
Feng Wenxiao, Lu Tiejun, Wang Zongmin Beijing Microelectronics Technology Institute
Beijing, China http://www.DownloadBooks.ir [email protected]
Abstract—This paper presents the analysis and design of high speed, high gain fully differential operational amplifier(opamp). The op-amp is designed for sample and hold circuit of 14 bit 100MS/s pipelined analog-to-digital converter (ADC). Both the main op-amp and the boosting op-amp are fully differential folded-cascode. The main op-amp has a switched capacitance common mode feedback circuit. The boosting op-amp is connected as a follower. The op-amp is designed in 0.18ȝm CMOS process with 3.0V power supply. Spectre simulation shows that the op-amp has the DC gain of 112dB and the unity gain bandwidth of 1.15GHz.
http://www.FindPdf.ir
Keywords- fully differential op-amp; folded cascode; boosting amplifier; pipelined ADC
I. I http://www.DownloadPaper.ir NTRODUCTION
With the development of the wireless communication, high speed and high resolution ADCs are essential and the design of a high performance op-amp is the most important part. Analog and digital circuit integrates onto a single die to reduce system costs, but noisy digital circuit degrades analog performance due to noise injection through power distribution network or the substrate. Fully differential analog signal processing is one of the most important techniques that reduce the problems associated with noise coupling. The fully differential technique doubles the maximum signal swing in the circuit effectively. The op-amp as the most important analog system building block has had to adopt the fully differential design technique. Optimizing circuit for both speed and accuracy leads to contradictory demands [1][2]. High accuracy depends on high dc gain and fast settling requires a high unity-gain frequency. It is difficult to combine high dc gain with high unity-gain frequency in a CMOS op-amp. The structure of a single-stage op-amp is always used to designing high speed op-amps. It mainly has folded-cascode topology and telescopic topology. Compare to telescopic topology, the folded-cascode topology requires more power, but it offers large output swing and has good performance on commonmode input range[3][4]. For high gain, the architecture of a single stage amplifier with gain-boosted amplifier is a nice choice. So it is good to use a folded-cascode structure with gain-boosted amplifier in the sample and hold stage.
http://www.DownloadEbooks.ir
Figure 1. The model of the gain-boosted amplifier
This paper describes the analysis and the design of fully differential gain-boosted op-amp for 14bit 100MS/s pipelined ADC. The organization of this paper is as follows: the model of the gain-boosted amplifier is explained in section Ċ and the circuit implementation with 0.18ȝm CMOS process is presented in section ċ. In section Č, the simulation results are given and discussed .The conclusions are presented in section č. II.
THE MODEL OF THE GAIN-BOOSTED AMPLIFIER
Fig.1 illustrates the model of the gain-boosted amplifier http://www.DownloadMaghale.ir [2]. M1 and M2 form the main cascode amplifier. A is a gain
-boosted amplifier. A drives the gate of M2 and forces the voltage at the drain of M1 and Vref to be equal. Because of the gain-boosted amplifier, voltage variations at the output will affect the voltage at the drain of M1 to a lesser extent variations [4]. As a result, the output resistance is almost A times larger than that of a regular cascode, the output resistance Rout is
http://www.DownloadEbook.ir
978-0-7695-3769-6/09 $26.00 © 2009 IEEE DOI 10.1109/NCM.2009.133
66
Contact Us: [email protected]
http://www.GigaPaper.ir
http://www.DownloadBooks.ir
http://www.FindPdf.ir
http://www.DownloadPaper.ir Figure 2. Fully differential folded cascaded op-amp with fully differential gain-boosted amplifiers
Rout
( g m 2 ro 2 ( A 1) 1)ro1 ro 2
According to Rout , the DC gain is
http://www.DownloadEbooks.ir Atot
is
g m1ro1 ( g m 2 ro 2 ( A 1) 1) g m1ro 2
And the DC gain of the amplifier without gain boosting
Atot
g m1ro1 ( g m 2 ro 2 1)
The gain boosting technology makes the DC gain of the circuit increasing several orders of magnitude.
http://www.DownloadMaghale.ir III.
CIRCUIT IMPLEMENTATION
Figure 3. PMOS-input fully differential gain-boosted amplifier(BP)
A. The Op-amp Circuit In Fig.2, a fully differential folded cascode that has two fully differential folded cascode gain-boosted amplifiers has been chosen. Actually, any amplifier can be used as the gain -boosted amplifier. A single transistor is the simplest amplifier. It consumes less power. But for high gain, the
http://www.DownloadEbook.ir 67
Contact Us: [email protected]
http://www.GigaPaper.ir
http://www.DownloadBooks.ir Figure 4. Switched capacitance common mode feedback Figure 5. Nonoverlapping phase clocks Figure 6. Phase margin and AC response of the main op-amp
B. The Design of the CMFB Circuit http://www.FindPdf.ir Fully differential amplifier provides much better rejection of common-mode noise and high-frequency powersupply variations compared to their single-ended counterparts [7]. When the fully differential op-amp is in a feedback configuration like sample and hold circuits, the high differential gain of a fully differential amplifier stabilizes the differential-mode signals within the amplifier, but the common-mode signals can float. It needs an additional common-mode feedback (CMFB) circuit to control the output common-mode voltages. A CMFB circuit averages both differential output voltages to produce a common-mode voltage Vcm. Vcm is then compared to a The desired reference common-mode voltage VCM. difference between Vcm and VCM is amplified and this error voltage is used to change the common-mode feedback voltage of the op-amp to force Vcm and VCM to be equal. CMFB circuits can be divided into two general categories: switched-capacitor CMFB (SC-CMFB) circuits and continuous-time CMFB circuits. Compare to continuoustime CMFB, SC-CMFB consumes less power. Because the op-amp is used in sample and hold circuit, nonoverlapping phase clocks are available. The SC-CMFB is adopted which is shown in Fig.4. It consists of four capacitors and six switches. The size of the capacitors should be chosen carefully so that they will not over-load the main op-amp. The nonoverlapping phase clocks (Fig.5) control the switches on and off. When CLK1 is high , C1 is charge to V C M V B IA S [8] . V is 1.5V. When CLK is high, C and
http://www.DownloadPaper.ir folded cascode amplifiers are usually used for the gainboosted amplifiers. For the input transistors, NMOS means large unity gain bandwidth but low nondominant pole, while PMOS means small unity gain bandwidth but high nondominant pole. So for high phase margin, the main amplifier is with PMOS input transistor. Using a PMOS input also has the shortcomings. PMOS-input requires larger input transistors and higher current to achieve high speed. Boosting stage BP is with PMOS input transistors (Fig.3)[5]. Boosting stage BN is the same as the BP type except that it is with a NMOS input transistors to realize high output impedance. Considering about the stability, the unity-gain frequency ( Z1 ) of the boosting amplifier should not be above the second-pole frequency ( Z p 2 ) of the main amplifier [6].
http://www.DownloadEbooks.ir
CM
2
1
C2 are connected parallel. The DC voltage of C2 is decided by C1 and refreshed every CLK2 period. The gain-boosted op-amp is connected as a follower.
Where £ is the feedback factor and Z p 1 is the unity-gain frequency of the main amplifier. Because the load of the boosting amplifier is smaller than the main amplifier, it is easy to satisfy (4)
http://www.DownloadMaghale.ir
EZ
p1
Z1 Z
p2
IV.
SIMULATION RESULTS
According to the above analysis and design, a fully differential amplifier is designed in a 0.18ȝm CMOS process and simulated with Spectre, with a CM voltage of 1.5V and
http://www.DownloadEbook.ir 68
Contact Us: [email protected]
http://www.GigaPaper.ir V.
CONCLUSIONS
This paper presents the analysis and design of fully differential amplifier with gain boosting technology. The gain-boosted amplifier is achieved by using the folded cascode amplifier. Based on 0.18ȝm CMOS process, it has good performance, with a DC gain of 112dB and a unity gain bandwidth of 1.15GHz. The designed op-amp fulfills the stringent specifications of 14bit 100MS/s sample and hold circuit of pipelined ADC. ACKNOWLEDGMENT The authors would like to thank Zhao Yaohua, Xiao http://www.DownloadBooks.ir Du ,Zhang Tieliang , Kong Ying and other members of the
Analog to Digital Converters Group for contributions to this work.
Figure 7. Sample and hold circuit
REFERENCES [1]
TABLE I. DC Gain,(dB) Unity GBW,(GHz) Phase Margin,(deg) Supply Voltage,(V) Load Capacitor,(pF) Settling Time,(ns) Power,(mW)
PERFORMANCE PARAMETERS
This paper 112 1.15 69 3.0 3.0 2.44 19.48
B. Y. Kamath, R. G. Meyer and P. R. Gray, Relationship between frequency response and settling time of operational amplifiers.IEEE J. Solid State Circuits, Vol.Sc-9, No.6,Dec 1974. K. Bult and G. J. G. M. Geelen. A fast-settling cmos op amp for circuits with 90-db dc gain. IEEE J. Solid-State Circuits, vol. 25, pp.1379–1384, Dec. 1990. Yang W㧘 Kelly D 㧘 Mehr I. 㧚 A 3V 340mW 14b 75Msample/s CMOS ADC with 85dB SFDR at Nyquist Input[J]㧚IEEE Journal Solid̅State Circuits㧘2001㧘36(12)㧦1 931-1 936. Razavi B. Design of Analog CMOS Integrated circuits [M]㧚New York㧦McGraw Hill.2001. Yang Bin, Ying Xiumei, Yang Huazhong. A High-Speed HighResolution Sample-and-Hold Circuit[J]. Chinese Journal of Semiconductors.Vol.28, No.10,Oct.2007. Qyvind Berntsen, Carsten Wulff, Trond Ytterdal. High speed, high gain OTA in a digital 90nm CMOS technology[J].NORCHIP,2005. Ojas Choksi, L. Richard Carley. Analysis of Switched-Capacitor Common-Mode Feedback Circuit. IEEE Transations on Circuits and Systems—II: Analog and Digital Signal Processing, VOL. 50, NO. 12, Dec. 2003. H. Recoules, R. Bouchakour, P. Loumeau, F. T. Braz. Two SCCMFB Networks Used in Fully Differential OTA: Measurements and Improvements. Rohana Musa, Yuzman Yusoff, Tan Kong Yew . Design of SingleStage Folded-Cascode Gain Boost Amplifier for 100mW 10-bit 50MS/s Pipelined Analog-to-Digital Converter. ICSE2006 Proc.2006.
http://www.FindPdf.ir
Reference[2] 90 0.116 64 5.0 16 61.5 52
Reference[9] 95 0.412 75 3.0 1.9 7.5 12.8
[2]
[3]
[4] [5]
3pF load capacitor. Fig.6 shows the AC simulation of the main amplifier. The unity GBW is 1.15GHz. The DC gain is more than 112 dB and the phase margin is 69e. The setting behavior of the op-amp is simulated in a closed-loop configuration of sample and hold amplifier (Fig.7).The sample and hold circuit adopts the flip-around structure. The feedback factor £ is nearly 1. This structure consumes low power and has low noise. The whole performances of the op-amp are shown in Table 1. Previous designs are also included [2][9]. From Table 1, we can see that the op-amp proposed in this paper has a higher DC gain, a larger unity GBW and a faster setting time than the other designs.
http://www.DownloadPaper.ir [6]
[7]
[8]
http://www.DownloadEbooks.ir [9]
http://www.DownloadMaghale.ir
http://www.DownloadEbook.ir 69
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