Realizations of CMOS Fully Differential Current ... - Semantic Scholar
Realizations of CMOS Fully Differential Current Followers/Amplifiers Hussain Alzaher and Noman Tasadduq Department of Electrical Engineering King Fahd University of Petroleum & Minerals Dhahran 31261, Saudi Arabia Email: [email protected] Abstract- Three CMOS realizations of fully differential current followers (amplifiers) are presented. Their various characteristics are determined and evaluated. In general, the proposed circuits exhibit low input resistances, high output resistances, and low common-mode gains. However, interesting differences showing the advantages and disadvantages of each topology are highlighted. Simulation results obtained using 0.18µm CMOS models are provided.
I.
INTRODUCTION
The current follower (CF) and current amplifier (CA) are pure current–mode building blocks wherein the primary signal variable is current. A current follower is a current controlled current source with unity gain Ai=1. A current amplifier has a general current gain Ai=b. The current operational amplifier (COA) is obtained when current transfer Ai goes to infinity; see for example [1]-[3]. Unlike COAs, CFs/CAs can be used in open loop circuit topologies. Adjoint networks theorem can be applied to convert voltagemode circuits to their current-mode counterparts based on CFs or CAs [4]. This is to provide the advantages of lower power supply voltage operation and wider-band frequency applications. Also, such true current-mode elements have the potential advantage of providing wide signal swing. This results in achieving high linearity and possibly wide dynamic range [5]. Unfortunately, other presumed current-mode active elements such as the second-generation current conveyor (CCII) and the current feedback amplifier (CFA) employing voltage-mode followers lose most if not all of these potential. Fully differential architectures are essential to enhance the performance of mixed analog/digital systems in terms of supply noise rejection, dynamic range, and harmonic distortion and also to reduce the effect of coupling between various blocks [6]. The main objective of this work is to present several fully differential CF/CA topologies and to investigate their characteristics. The following section presents the design of low power class AB multi-output CF/CA. Section III presents three topologies and explains the advantages and disadvantages of each circuit. Simulation
II. LOW POWER SINGLE ENDED CF A CF/CA is a two terminal device which conveys an input current signal from a low impedance (ideally virtual ground) terminal (X), to a high impedance (ideally infinity) output terminal (Z). The CFs/CAs can be classified as positive (non-inverting), wherein input and output currents are both going in the same direction, and the negative (inverting) type, having the currents in opposite directions. A dual-output CF/CA having both positive Zp and negative Zn outputs is shown in Fig. 1. This circuit is a modified version of the circuit presented in [7]. Its operation can be explained as follows. Transistors M1 and M2 offer the required virtual ground needed at the input port X. This is achieved by forcing equal currents in both transistors. Hence, their source potentials will be equal since they share the same gate, provided they operate in the saturation region. Since the transconductance of a MOS transistor is small compared to a bipolar transistor, negative feedback must be incorporated to achieve low input impedance at the X terminal. The X terminal current is provided by the action of the class AB negative feedback loop formed by transistors M3, M4, M5 and M7. The feedback reduces the input impedance by the amount of feedback, yielding:
Fig. 1. A low power CMOS CF/CA with two complementary outputs.
The authors would like to thank King Abdulaziz City for Science and Technology (KACST) Project No: AT-25-62, for the financial support.
978-1-4244-3828-0/09/$25.00 ©2009 IEEE
results are provided in section IV. An application example demonstrating some advantages of the proposed fully differential CF is given in section V.
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rx ≈
1 g m1 ( g m 5 + g m 7 )(rds1 // rds10 )
(1)
where gm and rds are the transconductance and the output resistance of the MOSFET, respectively. The output resistance seen at the output terminal are rzp=rds6//rd8 and rzn=rds18//rds19. In reference to the current directions given in Fig. 1, it is clear that Izp=Izn=KIx where K is the ratio of the widths of the current mirroring transistors. Although selecting K=1 reduces the circuit from a CA to a CF, its bandwidth is maximized. This is due to the fact that as the area of a transistor is increased, its capacitance increases limiting high frequency operation. Thus, configuring the circuit of Fig. 1 as a CF exploits the entire possible bandwidth. In the remaining part of the paper the term CF will be mainly used, but discussions and principles are applicable to CA as well. III. FULLY DIFFERENTIAL TOPOLOGIES The fully differential CF (FDCF) is a four terminal device with two input currents (I1 and I2) and two output currents (Io1 and Io2). In general, the differential output current can be expressed as:
I o1 − I o 2 = I o = Adiff I diff + Acm I cm
(2)
single output stage used in COAs. The main problem with the concept presented in [1] and [2] is the required matching between different types of conveyors CCII+ and CCII-. This paper shows that extending this concept to fully differential outputs overcomes this drawback. The third topology shown in Fig. 2(c) avoids the use of dual-output CFs but requires four CFs (all having K=1). CF1 and CF3 must be of plus type to perform the required subtractions. It can be seen that all circuits ideally exhibit virtual ground at the input terminals. Also, it is clear that the power consumption and area increases, as we go from topology (a) to (c). However, the circuits of Fig. 2(b) and Fig. 2(c) have the advantage of equal (symmetrical) input resistances. In particular, Fig. 2(c) provides the least (best) input resistance, with a value of rx//rx//rzp, which is approximately one half the resistance of single ended CF. In addition, the circuits of Fig. 2(b) and Fig. 2(c) have the advantage of inherently equal (symmetrical) output resistances, where Fig. 2(c) offers higher (better) output resistance. Assuming perfect current transfer for the various CFs, it is easy to observe that the common-mode output is zero, while the differential gain is unity for circuits of Fig. 2(a) and (b). For the circuit of Fig. 2(c), it can be seen that Io1=I1b-I2a and Io2= I2b-I1a, thus the differential output can be expressed as Io= I1b-I2a-(I2b-I1a)=(I1b+I1a)-(I2a+I2b)=I1-I2.
where Adiff=Io/Ii when I1=-I2=Ii/2 and Acm=Io/Ii when I1=I2=Ii. Ideally, Adiff and Acm are unity and zero, respectively. This means that FDCF should not only have unity differential current-gain, but also zero common-mode current gain. In addition, the input impedances must be set to zero. This can be achieved by holding the two input voltages, V1 and V2, at virtual ground. Note that the FDCF is different from pseudo differential version, that requires balanced inputs (I1=-I2) to produce differential outputs. In this case, the common-mode signals are not cancelled. Three possible topologies of realizing FDCF based on CFs are depicted in Fig. 2. Note that the biasing transistors are shared during the implementation phase. Fig. 2(a) uses a CF of plus type to subtract I2 from I1, and a dual-output CF to provide the required two balanced outputs. In this case K must be unity and one half in the designs of CF1 and CF2, respectively, in order to set the differential gain to unity. This can be achieved easily by proper sizing of the current mirroring transistors. This concept was used in [3] as a differential input single output circuit to realize the input stage for a COA. Here this idea is extended to fully differential outputs and its common-mode rejection is analytically explored. Unfortunately, this work shows that the common-mode rejection of this circuit is significantly degraded as frequency increases. Fig. 2(b) employs two dual-output CFs and the subtractions are performed at the output terminals. Here K of one half in both CF is needed to provide unity differential gain. Note that similar realizations based on CCII were introduced in [1] and [2] to implement differential input
(a)
(b)
(c) Fig. 2. Three different FDCF topologies using single-ended CF
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The non-ideal performance of these circuits can be explored by assuming current transfer of αp and αn for the positive and negative outputs of the CFs, respectively. It can be shown that the differential-mode gains for the different circuits are given by:
Adiff a = (α p 2 + α n 2 )(α p1 + 1) / 2
3(a)
Adiffb = (α n1 + α n 2 + α p1 + α p 2 ) / 2
3(b)
respectively. However, Fig. 5 shows the high dependence between common-mode gain of the circuit shown in Fig. 2(a) and frequency, wherein highpass frequency response is observed as predicted. On the other hand, the circuit of Fig. 2(b) and (c) has demonstrated excellent common-mode responses, under good matching conditions. Fig. 2(b) shows slightly better response than Fig. 2(c), which is due to the
Adiffc = [α p2 β1 + α p4 β2 + α p3α p 4 (1− β1 ) + α p1α p 2 (1− β2 )]/ 2 3(c) where βi (ideally one half), for i= 1 and 2 in the circuit of Fig. 2(c), is used to represent the division weight between Iia and Iib with Iia=βiIi and Iib=(1- βi)Ii. The accuracy of the current division depends on the matching of input resistance of various devices. Also, it can be shown that the commonmode outputs for the various circuits can be expressed as follows:
Acma = (α p 2 + α n 2 )(α p1 − 1)
4(a)
Acmb = (α n1 − α n 2 ) + (α p1 − α p 2 )
4(b)
Acmc = (α p 2 β1 − α p 4 β 2 ) + [α p 3α p 4 (1 − β1 ) − α p1α p 2 (1 − β 2 )]
4(c)
Note that the ideal values of current transfers are αp1=1, αp2=αn2=0.5; αp1=αp2=αn1=αn2=0.5 and αp1=αp2=αp3=αp4=1, for the circuits of Fig. 2 (a), (b) and (c), respectively. It is clear from 4(a) that error in the value of CF1 gain, for the circuit of Fig. 2 (a), causes finite common-mode output. While the common-mode output 4(b), for the circuit of Fig. 2(b), is due to the difference between the gains of two devices of the same type (i.e. mismatch error). Also, Acm for the circuit of Fig. 2(c) is due to the mismatches between various CFs. More dangerously, it is observed that when current gain (αp1) of CF1 in Fig. 2(a) is represented by first order frequency dependent lowpass model, its common-mode gain exhibits highpass response. Consider the effect of the frequency response of CF1 (i.e. α p1 = 1/( s / ωo + 1) ), and assume CF2 is
Acma
ideal,
with
αp2= αn2=1/2, this leads to = − s /( s + ωo ) . This implies that the topology given
Fig. 3. Differential-mode DC operation for the three circuits.
Fig. 4. Differential-mode ac responses for the three circuits.
in Fig. 2(a) is unsuitable for high frequency applications. IV. SIMULATION RESULTS The design of CF/CA shown in Fig. 1 was revised and transistor aspect ratios were optimized using TSMC 0.18μm CMOS process. Throughout the post layout simulations, the supply voltages were set to ±1.5V, and biasing currents were IBP=40µA and ISB=10µA. The differential mode dc transfer characteristic is shown in Fig. 3. It can be seen from Fig. 3 that the three circuits have almost same DC response in the differential-mode. The ac responses of the three circuits are shown in Fig. 4 and Fig. 5. It can be seen from Fig. 4 that the circuits of Fig. 2(a), (b) and (c) exhibit differential-mode -3dB bandwidth of 57MHz, 77MHz and 36MHz,
Fig. 5. Common-mode ac responses for the three circuits.
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presence of less number of elementary blocks. In addition, Monte-Carlo analysis is used to investigate the effect of CFs mismatches on the common-mode rejection. Monte-Carlo analysis was performed varying current transfer of all CFs in 100 trials, according to Gaussian distribution, with several different standard deviations. It is found that the circuit of Fig. 2(b) exhibits average common-mode gain of -37.5dB, -45dB, -50dB, 56dB, and -65dB in the presence of mismatches of 2%, 1%, 0.5%, 0.2%, and 0.1%, respectively. Also, it is observed that Acmb is constant over the entire differential-mode bandwidth. On the other hand, it is observed that the common-mode gain is extremely low for the circuit of Fig. 2(c) (-110dB) even with 2% mismatch errors. However, Acmc turns out to be frequency dependent in the presence of mismatches. It increases as frequency increases, but it maintains an acceptable value of approximately -47dB at a frequency of 10MHz.
Fig. 6. Fully differential current-mode SK highpass filter.
V. APPLICATION EXAMPLE The Sallen-Key (SK) filter family requires only a single op-amp per biquad [8]. Hence, they are simple and attractive for low power applications. Since these filters are based on one active element, they also exhibit excellent noise and linearity performances. Using the op-amp as a voltage buffer exploits its entire bandwidth, permitting high frequency operation. However, they are implemented using either pseudo topologies with single ended voltage followers (VFs) [9] or sophisticated fully differential VFs [10]. Therefore, we propose the use of fully differential CF, for example Fig. 2(b) to provide simple solution for realizing the active element in the SK topology. Fig. 6 shows a fully differential version of the current-mode SK highpass filter, developed using adjoint networks theorem. It can be shown that the current transfer function of the filter is given by
H HP ( s ) =
s 2C1C2 R1 R2 s 2C1C2 R1 R2 + s (C1 + C2 ) R2 + 1
Fig. 7. Magnitude response of the filter shown in Fig. 7
the widest differential-mode bandwidth, symmetrical input and output resistances, and frequency independent commonmode gain, whose values can be reduced by improving the matching between two identical CFs. Also, note that the circuit of Fig 2(b) consumes slightly more supply current (3ISB), compared with its counterpart of Fig 2(a), therefore it can be concluded that the circuit of Fig 2(b) is the best candidate. REFERENCES E. Bruun, “A constant-bandwidth current-mode operational amplifier,” Electron. Lett., vol. 27, pp. 1673-1674, 1991. [2] T. Kaulberg, “A CMOS current-mode operational amplifier,” IEEE J. Solid-State Circuits, vol. 28, pp. 849-852, 1993. [3] M. Youssef, and A. Soliman, “A novel CMOS realization of differential input balanced output current operational amplifier and its applications,” Analog Integrated Circuits and Signal Processing, vol. 44, pp. 37-53, 2005. [4] G. W. Roberts, and A. S. Sedra, “All current-mode frequency selective circuits,” Electronics Letters, vol. 25, pp. 759-61, June 1989. [5] R. Zele, D. Allstot, and S. Fiez, “Fully balanced CMOS current-mode circuits,” IEEE J. Solid-State Circuits, vol. SC-28, pp. 569-575, 1993. [6] A. Durham, W. Redman-White, and J. Hughes, “High-linearity continuous time filter in 5-V VLSI CMOS,” IEEE J. Solid-State Circuits, vol. 27, pp. 1270-1276, 1992. [7] H. Alzaher, H. Elwan and M. Ismail, 2002, “A CMOS Highly Linear Channel Select Filter for 3G Multi-Standard Integrated Wireless Receivers," IEEE J. Solid-State Circuits, vol. 37, pp. 27-37, 2002. [8] R. Sallen, and E. Key, “A practical method of designing RC active filters,” IRE Trans. of Circuits Theory, vol. CT-2, pp. 77-85, Jan. 1955. [9] E. De Backer, J. Bauwelinck, C. Me´lange, E. Matei, P. Ossieur, X.-Z. Qiu, J. Vandewege and S. Horvath, “2.5 V 35 dBm IIP3 75 MHz sixth-order active RC filter,” Electron. Lett., vol. 44, pp. 466-467, 2008. [10] H. Alzaher, M. Al-Ghamdi, and M. Ismail, “A CMOS Low Power Bandpass IF Filter for Bluetooth,” IET Circuits, Devices & Systems, vol. 1, pp. 7 – 12, 2007.
(5)
[1]
Fig. 7 shows the simulation results of the filter frequency response. It is clear that the simulation results are in good agreement with the ideal response. Also, as expected, the frequency response starts rolling off at relatively high frequencies (i.e. the upper -3dB is 60MHz, approximately). VI. CONCLUSION Three possible topologies for realizing fully differential CF/CAs are presented. It is found that the circuit with least power consumption, Fig. 2(a), exhibits significantly frequency dependent common-mode gain. This prevents its use in high frequency applications. The circuit of Fig. 2(c) has the best input and output resistances. But its power consumption and hardware complexity are the highest, and its differential-mode bandwidth is narrowest. Although it provides extremely low common-mode gain, its value turns out to be frequency dependent. The circuit of Fig. 2(b) has
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I.
INTRODUCTION
The current follower (CF) and current amplifier (CA) are pure current–mode building blocks wherein the primary signal variable is current. A current follower is a current controlled current source with unity gain Ai=1. A current amplifier has a general current gain Ai=b. The current operational amplifier (COA) is obtained when current transfer Ai goes to infinity; see for example [1]-[3]. Unlike COAs, CFs/CAs can be used in open loop circuit topologies. Adjoint networks theorem can be applied to convert voltagemode circuits to their current-mode counterparts based on CFs or CAs [4]. This is to provide the advantages of lower power supply voltage operation and wider-band frequency applications. Also, such true current-mode elements have the potential advantage of providing wide signal swing. This results in achieving high linearity and possibly wide dynamic range [5]. Unfortunately, other presumed current-mode active elements such as the second-generation current conveyor (CCII) and the current feedback amplifier (CFA) employing voltage-mode followers lose most if not all of these potential. Fully differential architectures are essential to enhance the performance of mixed analog/digital systems in terms of supply noise rejection, dynamic range, and harmonic distortion and also to reduce the effect of coupling between various blocks [6]. The main objective of this work is to present several fully differential CF/CA topologies and to investigate their characteristics. The following section presents the design of low power class AB multi-output CF/CA. Section III presents three topologies and explains the advantages and disadvantages of each circuit. Simulation
II. LOW POWER SINGLE ENDED CF A CF/CA is a two terminal device which conveys an input current signal from a low impedance (ideally virtual ground) terminal (X), to a high impedance (ideally infinity) output terminal (Z). The CFs/CAs can be classified as positive (non-inverting), wherein input and output currents are both going in the same direction, and the negative (inverting) type, having the currents in opposite directions. A dual-output CF/CA having both positive Zp and negative Zn outputs is shown in Fig. 1. This circuit is a modified version of the circuit presented in [7]. Its operation can be explained as follows. Transistors M1 and M2 offer the required virtual ground needed at the input port X. This is achieved by forcing equal currents in both transistors. Hence, their source potentials will be equal since they share the same gate, provided they operate in the saturation region. Since the transconductance of a MOS transistor is small compared to a bipolar transistor, negative feedback must be incorporated to achieve low input impedance at the X terminal. The X terminal current is provided by the action of the class AB negative feedback loop formed by transistors M3, M4, M5 and M7. The feedback reduces the input impedance by the amount of feedback, yielding:
Fig. 1. A low power CMOS CF/CA with two complementary outputs.
The authors would like to thank King Abdulaziz City for Science and Technology (KACST) Project No: AT-25-62, for the financial support.
978-1-4244-3828-0/09/$25.00 ©2009 IEEE
results are provided in section IV. An application example demonstrating some advantages of the proposed fully differential CF is given in section V.
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rx ≈
1 g m1 ( g m 5 + g m 7 )(rds1 // rds10 )
(1)
where gm and rds are the transconductance and the output resistance of the MOSFET, respectively. The output resistance seen at the output terminal are rzp=rds6//rd8 and rzn=rds18//rds19. In reference to the current directions given in Fig. 1, it is clear that Izp=Izn=KIx where K is the ratio of the widths of the current mirroring transistors. Although selecting K=1 reduces the circuit from a CA to a CF, its bandwidth is maximized. This is due to the fact that as the area of a transistor is increased, its capacitance increases limiting high frequency operation. Thus, configuring the circuit of Fig. 1 as a CF exploits the entire possible bandwidth. In the remaining part of the paper the term CF will be mainly used, but discussions and principles are applicable to CA as well. III. FULLY DIFFERENTIAL TOPOLOGIES The fully differential CF (FDCF) is a four terminal device with two input currents (I1 and I2) and two output currents (Io1 and Io2). In general, the differential output current can be expressed as:
I o1 − I o 2 = I o = Adiff I diff + Acm I cm
(2)
single output stage used in COAs. The main problem with the concept presented in [1] and [2] is the required matching between different types of conveyors CCII+ and CCII-. This paper shows that extending this concept to fully differential outputs overcomes this drawback. The third topology shown in Fig. 2(c) avoids the use of dual-output CFs but requires four CFs (all having K=1). CF1 and CF3 must be of plus type to perform the required subtractions. It can be seen that all circuits ideally exhibit virtual ground at the input terminals. Also, it is clear that the power consumption and area increases, as we go from topology (a) to (c). However, the circuits of Fig. 2(b) and Fig. 2(c) have the advantage of equal (symmetrical) input resistances. In particular, Fig. 2(c) provides the least (best) input resistance, with a value of rx//rx//rzp, which is approximately one half the resistance of single ended CF. In addition, the circuits of Fig. 2(b) and Fig. 2(c) have the advantage of inherently equal (symmetrical) output resistances, where Fig. 2(c) offers higher (better) output resistance. Assuming perfect current transfer for the various CFs, it is easy to observe that the common-mode output is zero, while the differential gain is unity for circuits of Fig. 2(a) and (b). For the circuit of Fig. 2(c), it can be seen that Io1=I1b-I2a and Io2= I2b-I1a, thus the differential output can be expressed as Io= I1b-I2a-(I2b-I1a)=(I1b+I1a)-(I2a+I2b)=I1-I2.
where Adiff=Io/Ii when I1=-I2=Ii/2 and Acm=Io/Ii when I1=I2=Ii. Ideally, Adiff and Acm are unity and zero, respectively. This means that FDCF should not only have unity differential current-gain, but also zero common-mode current gain. In addition, the input impedances must be set to zero. This can be achieved by holding the two input voltages, V1 and V2, at virtual ground. Note that the FDCF is different from pseudo differential version, that requires balanced inputs (I1=-I2) to produce differential outputs. In this case, the common-mode signals are not cancelled. Three possible topologies of realizing FDCF based on CFs are depicted in Fig. 2. Note that the biasing transistors are shared during the implementation phase. Fig. 2(a) uses a CF of plus type to subtract I2 from I1, and a dual-output CF to provide the required two balanced outputs. In this case K must be unity and one half in the designs of CF1 and CF2, respectively, in order to set the differential gain to unity. This can be achieved easily by proper sizing of the current mirroring transistors. This concept was used in [3] as a differential input single output circuit to realize the input stage for a COA. Here this idea is extended to fully differential outputs and its common-mode rejection is analytically explored. Unfortunately, this work shows that the common-mode rejection of this circuit is significantly degraded as frequency increases. Fig. 2(b) employs two dual-output CFs and the subtractions are performed at the output terminals. Here K of one half in both CF is needed to provide unity differential gain. Note that similar realizations based on CCII were introduced in [1] and [2] to implement differential input
(a)
(b)
(c) Fig. 2. Three different FDCF topologies using single-ended CF
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The non-ideal performance of these circuits can be explored by assuming current transfer of αp and αn for the positive and negative outputs of the CFs, respectively. It can be shown that the differential-mode gains for the different circuits are given by:
Adiff a = (α p 2 + α n 2 )(α p1 + 1) / 2
3(a)
Adiffb = (α n1 + α n 2 + α p1 + α p 2 ) / 2
3(b)
respectively. However, Fig. 5 shows the high dependence between common-mode gain of the circuit shown in Fig. 2(a) and frequency, wherein highpass frequency response is observed as predicted. On the other hand, the circuit of Fig. 2(b) and (c) has demonstrated excellent common-mode responses, under good matching conditions. Fig. 2(b) shows slightly better response than Fig. 2(c), which is due to the
Adiffc = [α p2 β1 + α p4 β2 + α p3α p 4 (1− β1 ) + α p1α p 2 (1− β2 )]/ 2 3(c) where βi (ideally one half), for i= 1 and 2 in the circuit of Fig. 2(c), is used to represent the division weight between Iia and Iib with Iia=βiIi and Iib=(1- βi)Ii. The accuracy of the current division depends on the matching of input resistance of various devices. Also, it can be shown that the commonmode outputs for the various circuits can be expressed as follows:
Acma = (α p 2 + α n 2 )(α p1 − 1)
4(a)
Acmb = (α n1 − α n 2 ) + (α p1 − α p 2 )
4(b)
Acmc = (α p 2 β1 − α p 4 β 2 ) + [α p 3α p 4 (1 − β1 ) − α p1α p 2 (1 − β 2 )]
4(c)
Note that the ideal values of current transfers are αp1=1, αp2=αn2=0.5; αp1=αp2=αn1=αn2=0.5 and αp1=αp2=αp3=αp4=1, for the circuits of Fig. 2 (a), (b) and (c), respectively. It is clear from 4(a) that error in the value of CF1 gain, for the circuit of Fig. 2 (a), causes finite common-mode output. While the common-mode output 4(b), for the circuit of Fig. 2(b), is due to the difference between the gains of two devices of the same type (i.e. mismatch error). Also, Acm for the circuit of Fig. 2(c) is due to the mismatches between various CFs. More dangerously, it is observed that when current gain (αp1) of CF1 in Fig. 2(a) is represented by first order frequency dependent lowpass model, its common-mode gain exhibits highpass response. Consider the effect of the frequency response of CF1 (i.e. α p1 = 1/( s / ωo + 1) ), and assume CF2 is
Acma
ideal,
with
αp2= αn2=1/2, this leads to = − s /( s + ωo ) . This implies that the topology given
Fig. 3. Differential-mode DC operation for the three circuits.
Fig. 4. Differential-mode ac responses for the three circuits.
in Fig. 2(a) is unsuitable for high frequency applications. IV. SIMULATION RESULTS The design of CF/CA shown in Fig. 1 was revised and transistor aspect ratios were optimized using TSMC 0.18μm CMOS process. Throughout the post layout simulations, the supply voltages were set to ±1.5V, and biasing currents were IBP=40µA and ISB=10µA. The differential mode dc transfer characteristic is shown in Fig. 3. It can be seen from Fig. 3 that the three circuits have almost same DC response in the differential-mode. The ac responses of the three circuits are shown in Fig. 4 and Fig. 5. It can be seen from Fig. 4 that the circuits of Fig. 2(a), (b) and (c) exhibit differential-mode -3dB bandwidth of 57MHz, 77MHz and 36MHz,
Fig. 5. Common-mode ac responses for the three circuits.
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presence of less number of elementary blocks. In addition, Monte-Carlo analysis is used to investigate the effect of CFs mismatches on the common-mode rejection. Monte-Carlo analysis was performed varying current transfer of all CFs in 100 trials, according to Gaussian distribution, with several different standard deviations. It is found that the circuit of Fig. 2(b) exhibits average common-mode gain of -37.5dB, -45dB, -50dB, 56dB, and -65dB in the presence of mismatches of 2%, 1%, 0.5%, 0.2%, and 0.1%, respectively. Also, it is observed that Acmb is constant over the entire differential-mode bandwidth. On the other hand, it is observed that the common-mode gain is extremely low for the circuit of Fig. 2(c) (-110dB) even with 2% mismatch errors. However, Acmc turns out to be frequency dependent in the presence of mismatches. It increases as frequency increases, but it maintains an acceptable value of approximately -47dB at a frequency of 10MHz.
Fig. 6. Fully differential current-mode SK highpass filter.
V. APPLICATION EXAMPLE The Sallen-Key (SK) filter family requires only a single op-amp per biquad [8]. Hence, they are simple and attractive for low power applications. Since these filters are based on one active element, they also exhibit excellent noise and linearity performances. Using the op-amp as a voltage buffer exploits its entire bandwidth, permitting high frequency operation. However, they are implemented using either pseudo topologies with single ended voltage followers (VFs) [9] or sophisticated fully differential VFs [10]. Therefore, we propose the use of fully differential CF, for example Fig. 2(b) to provide simple solution for realizing the active element in the SK topology. Fig. 6 shows a fully differential version of the current-mode SK highpass filter, developed using adjoint networks theorem. It can be shown that the current transfer function of the filter is given by
H HP ( s ) =
s 2C1C2 R1 R2 s 2C1C2 R1 R2 + s (C1 + C2 ) R2 + 1
Fig. 7. Magnitude response of the filter shown in Fig. 7
the widest differential-mode bandwidth, symmetrical input and output resistances, and frequency independent commonmode gain, whose values can be reduced by improving the matching between two identical CFs. Also, note that the circuit of Fig 2(b) consumes slightly more supply current (3ISB), compared with its counterpart of Fig 2(a), therefore it can be concluded that the circuit of Fig 2(b) is the best candidate. REFERENCES E. Bruun, “A constant-bandwidth current-mode operational amplifier,” Electron. Lett., vol. 27, pp. 1673-1674, 1991. [2] T. Kaulberg, “A CMOS current-mode operational amplifier,” IEEE J. Solid-State Circuits, vol. 28, pp. 849-852, 1993. [3] M. Youssef, and A. Soliman, “A novel CMOS realization of differential input balanced output current operational amplifier and its applications,” Analog Integrated Circuits and Signal Processing, vol. 44, pp. 37-53, 2005. [4] G. W. Roberts, and A. S. Sedra, “All current-mode frequency selective circuits,” Electronics Letters, vol. 25, pp. 759-61, June 1989. [5] R. Zele, D. Allstot, and S. Fiez, “Fully balanced CMOS current-mode circuits,” IEEE J. Solid-State Circuits, vol. SC-28, pp. 569-575, 1993. [6] A. Durham, W. Redman-White, and J. Hughes, “High-linearity continuous time filter in 5-V VLSI CMOS,” IEEE J. Solid-State Circuits, vol. 27, pp. 1270-1276, 1992. [7] H. Alzaher, H. Elwan and M. Ismail, 2002, “A CMOS Highly Linear Channel Select Filter for 3G Multi-Standard Integrated Wireless Receivers," IEEE J. Solid-State Circuits, vol. 37, pp. 27-37, 2002. [8] R. Sallen, and E. Key, “A practical method of designing RC active filters,” IRE Trans. of Circuits Theory, vol. CT-2, pp. 77-85, Jan. 1955. [9] E. De Backer, J. Bauwelinck, C. Me´lange, E. Matei, P. Ossieur, X.-Z. Qiu, J. Vandewege and S. Horvath, “2.5 V 35 dBm IIP3 75 MHz sixth-order active RC filter,” Electron. Lett., vol. 44, pp. 466-467, 2008. [10] H. Alzaher, M. Al-Ghamdi, and M. Ismail, “A CMOS Low Power Bandpass IF Filter for Bluetooth,” IET Circuits, Devices & Systems, vol. 1, pp. 7 – 12, 2007.
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Fig. 7 shows the simulation results of the filter frequency response. It is clear that the simulation results are in good agreement with the ideal response. Also, as expected, the frequency response starts rolling off at relatively high frequencies (i.e. the upper -3dB is 60MHz, approximately). VI. CONCLUSION Three possible topologies for realizing fully differential CF/CAs are presented. It is found that the circuit with least power consumption, Fig. 2(a), exhibits significantly frequency dependent common-mode gain. This prevents its use in high frequency applications. The circuit of Fig. 2(c) has the best input and output resistances. But its power consumption and hardware complexity are the highest, and its differential-mode bandwidth is narrowest. Although it provides extremely low common-mode gain, its value turns out to be frequency dependent. The circuit of Fig. 2(b) has
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