Carbon nanotube field effect transistors for high performance analog ...
ARTICLE IN PRESS Microelectronics Journal 41 (2010) 395–402
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Carbon nanotube field effect transistors for high performance analog applications: An optimum design approach Fahad Ali Usmani, Mohammad Hasan n Department of Electronics Engineering, Aligarh Muslim University, Aligarh, India
a r t i c l e in fo
abstract
Article history: Received 26 June 2009 Received in revised form 11 April 2010 Accepted 26 April 2010 Available online 15 May 2010
There is a need to explore circuit designs in new emerging technologies for their rapid commercialization to extend Moore’s law beyond 22 nm technology node. Carbon nanotube based transistor (CNFET) has significant potential to replace CMOS in the future due to its better electrostatics and higher mobility. This paper presents a complete optimal design of an inverting amplifier in CMOS, CNFET and hybrid technologies. We investigate and conceptually explain the performance measure of the amplifier at 32 nm technology node in terms of operating voltage, number of carbon nanotubes (CNT), diameter and pitch (inter-nanotube distance) variations of carbon nanotubes in a CNFET transistor in pure and hybrid technologies for area, power and performance optimization. This paper also explores the scope, possibilities and challenges associated with pure CNFET and hybrid amplifiers. We have found that pure CNFET amplifier provided good amplification while hybrid pCNFET–nMOS amplifier offered excellent frequency response and pMOS–nCNFET amplifier gave better transient performance compared with planar CMOS. & 2010 Elsevier Ltd. All rights reserved.
Keywords: Single walled CNT Chirality Carbon nanotube field effect transistor (CNFET) CMOS Analog
1. Introduction CMOS technology is approaching its limits in the presence of challenges like extreme short-channel effects, lithographic limitations, process variations, leakage current and source-to-drain tunneling [1,2]. Many technological and device structure variations have been proposed in the literature like ultra-thin body single or multiple-gate FETs, FinFETs, dynamic threshold MOSFET, SOI FETs and strained silicon etc. to provide improvements in electrostatics over CMOS. Now in order to sustain Moore’s Law and to ensure further improvement in FET performance, it is necessary to look for alternatives like CNFETs that promise to deliver much better performance than existing MOSFETs. CNFET technology can also be easily clubbed with the bulk CMOS technology on a single chip and utilizes the same infrastructure [3]. They are being looked upon as promising devices due to lower leakage power with continued scaling. Since in CNFET, SiO2 surrounds the carbon nanotube which is the only path to allow current to flow showing a behavior similar to ultra-thin body FET. Moreover, high gate capacitance provides strong gate control of the channel potential by the use of high-k dielectrics such as HfO2 (typically 3 nm thick) for gate insulation, thereby, reducing shortchannel effects due to increased capacitive coupling [2]. In 1991, for the first time, multi-walled carbon nanotubes were discovered by Ijima [4] and later in 1998, their semiconducting
n
Corresponding author. E-mail addresses: [email protected] (F. Ali Usmani), mohd.hasan@ mail.amu.ac.in, [email protected] (M. Hasan). 0026-2692/$ - see front matter & 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2010.04.011
behavior was reported [5]. Thereafter, their conductive, structural, electrical, thermal properties, etc. were studied extensively and many possible applications such as in field emission displays, field-effect transistors, optical fibers, chemical sensors, etc. were experimentally demonstrated. This nanoscale alternative offers vast possibilities along with serious challenges like their commercial integration, growth and placement of CNTs, chirality control and enabling process and technologies [6]. The DC and AC performance of a CNFET has already been analyzed and measured [7,8]. There has been a lot of work available in the literature on the digital applications of CNFET but its analog applications have not been explored [9,10]. This paper investigates in detail for the first time the performance and reliability of pure and hybrid CMOS–CNFET technologies based analog amplifier and to propose their suitability in a wide range of high performance analog circuit and system applications. The paper also explores area, power and performance optimization of the amplifier. It begins with an overview of CNFET transistor and device design specifications in Section 2. Section 3 covers the optimum design of pure and hybrid inverting amplifiers. Section 4 discusses the comparison of pure and hybrid amplifiers at 32 nm technology node followed by conclusion in Section 5.
2. Carbon nanotube field effect transistor A single walled carbon nanotube (SWCNT) is a one-dimensional conductor, shown in Fig. 1(a), that can be either metallic or semiconducting depending upon the arrangement of carbon
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atoms decided by their Chirality, Ch (i.e. the direction in which the graphene sheet is rolled) whose magnitude and relationship with CNT diameter (DCNT) is given by Eqs. (1) and (2) respectively where ‘a’ is the graphene lattice constant (0.249 nm) and n1, n2 are positive integers that specify the chirality of the tube. qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Ch ¼ a n21 þn22 þ n1 n2 ð1Þ DCNT ¼ C h = p
ð2Þ
It also defines that SWCNT is a sheet of graphite which is rolled up and joined together along a wrapping vector Ch ¼n1.a1 + n2.a2, as shown in Fig. 1(b), where a1, a2 are unit vectors. A MOS-like carbon nanotube transistor (CNFET) is obtained by replacing the channel of a conventional MOSFET by a number of semiconducting carbon nanotubes, as shown in Fig. 2 and its cross-section in Fig. 3 [11]. The source and drain are the n + (or p+ ) doped semiconducting CNTs with Pd metal contacts for n (or p )-type CNFETs. Doped CNTs act as both the source/drain extension region and/or interconnects between two adjacent devices. It should be noted that CNT channel is undoped while all other regions are heavily doped [13]. The number of carbon nanotubes in the channel depends on the current drive requirement. The carrier transport between source and drain will now take place through these narrow carbon nanotubes. The operation principle of CNFET is similar to a traditional MOSFET. Since the electrons are only confined to the narrow nanotube, the mobility goes up substantially on account of ballistic transport as compared with the bulk MOSFET. CNFET has the potential of taking over in the post silicon era due to their exceptional electrical and structural characteristics such as quasi 1-D (ballistic) transport of electrons (and equally likely for holes), higher drive current (3–4 times than MOSFETs) and large transconductance, low intrinsic capacitance, near ideal sub-threshold slope, high temperature resilience and strong covalent bonding, etc. [11]. This strong covalent bonding allows the use of high-k dielectric gate material and considerable reduction in oxide thickness without any substantial degradation in performance. A CNFET exhibits unipolar behavior and operates on the principle of barrier height modulation by application of the gate potential. An additional advantage of the top gate structure apart from better current handling and reduced leakage current is that with only slight modification, it can be made suitable for high frequency operation, which is not possible with back-gated devices due to the large overlap capacitance between the gate, source, and drain [11]. CNFET offers superior carrier transport and conduction characteristics over silicon devices because of the
remarkable properties of SWCNTs which are actually derived from the unusual electronic structure of 2-D graphene sheet. Especially, the high mobility is largely due to lack of surface states and high current density could be attributed to the strong covalent bonding of atoms in the tube. The surface state problem is solved elegantly due to the absence of chemically reactive dangling bonds responsible for surface scattering. The CNT diameter, the width of the CNFET transistor (W), number of CNTs in the channel of a CNFET (N), inter-nanotube spacing (S) are related by Eq. (3). The Band gap energy (Sg) and
Fig. 2. 3D CNFET structure.
Wgate Pitch Dielectric ( ) (Kgate)
Drain Ldd Lg
(number of CNTs))
Gate t
Drain
Source Csub
Gate Lss
tubes
CNTs
Substrate
Source
Fig. 3. Schematic CNFET cross-section.
Fig. 1. (a) SWCNT (b) Graphite sheet in terms of Chirality, n1 and n2
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threshold voltage (Vth) of the intrinsic CNT channel are related by Eq. (4) where ‘acc’ is the carbon-to-carbon bond distance (0.1412 nm for graphite), ‘e’ is the unit electron charge and ‘t’ is the carbon-to-carbon bond energy (3.0 eV). W ¼ ðN1ÞS þDCNT
Sg ðeVÞ ¼
2acc t 0:84 eV ¼ 2 eVth DCNT ðnmÞ DCNT ðnmÞ
ð3Þ ð4Þ
The high performance Verilog-A Stanford model has been used for analyzing the performance of CNFET transistor [12]. The CNFET model successfully accounts for its device parasitics and practical non-idealities including the channel length dependence of current drive, the finite scattering mean free path, the source/ drain series resistance, the source/drain contact resistance, the geometry dependence of the gate-to-channel capacitance, the interconnect wiring capacitance, scattering and inter-CNT charge screening effects etc. apart from accurate predictions of dynamic and transient performance with more than 90% accuracy. Chirality control problem has been partially addressed during the current derivation and the chirality difference for SWCNTs with same diameter have been ignored for our purpose, in the range where the carrier energy is less than 1.0 eV for sub-1 V power supply circuit applications [13–16].
3. CMOS inverting amplifier CMOS inverting amplifier is a basic analog building block with simple architecture apart from uncomplicated design and ease of analysis. It offers much insight into the operational and design summary of more complex analog and mixed signal circuits. The widely used BSIMv4.6.1 Berkeley Predictive Technology Model has been used for the MOSFET at the 32 nm technology node. Operating environment is chosen under proper biasing for a capacitive load of 1 fF in addition to negligible intrinsic device capacitances ( 2–5 aF/nanotube) and parasitics (including fringe and overlap capacitances) as low as 0.1 fF/nanotube for a 32 nm CNFET device [17]. A typical CNFET with 4-nm-thick planar HfO2 (k1 ¼16) gate oxide and SiO2 (k2 ¼ 3.9) substrate, fabricated with Pd source/drain metal contacts and Al gate electrode is used in simulation [18]. Analysis assumes that CNFETs are made up of homogeneous and identical semiconducting CNTs that have the same chirality and the same doping level. For hybrid or pure technology designs, p- or/and n-type MOSFET has been replaced by the corresponding p- or/and ncNFET without changing their gate widths as given by Eq. (3). Thereafter, their analog performance metrics such as gain, bandwidth, gain-bandwidth product (GBP), slewing performance, settling time, average power dissipation, output resistance etc. and optimum device design specifications are investigated through HSPICEs simulations.
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minimum pitch to be greater than twice the diameter for same width as that of a CMOS design. Since below the minimum pitch, both the gate capacitance and the drive current of CNTs in the middle are smaller in comparison to those at the edges. This is due to the screening effect produced by adjacent CNTs which poses a maximum limit on the number of CNTs in the channel of a CNFET for optimal performance [15]. By studying the effect of parameter variations with supply voltage, VDD as depicted in Table 1, it was found that for best performance, the supply voltage must be set around 0.9 V. The lowering of supply voltage decreases the power consumption due to proportional scaling but it also affects the circuit slew rate and settling time. This is due to lower output swing and pronounced effect of parasitics which deteriorates the bandwidth of the amplifier. As expected, almost all other parameters improve but due to lower swing, robustness deteriorates. 3.1.2. Optimum number of CNTs (N) It is important to determine the number of CNTs to be used in an array in order to ensure sufficient current supply for driving fixed capacitive loads as single nanotube based transistor does not provide competitive performance over traditional silicon devices [18,19]. It can be inferred from Figs. 4 and 5 that with the increase in ‘N’, both gain and bandwidth improve somewhat parabolically. This is due to the significant increase in transconductance with the increase in number of nanotubes [20,21]. It is important to investigate the problem associated with large number of tubes in addition to geometrical constraints. Here, the current per tube IPERTUBE ( 20 mA) is constant owing to non-varying ‘S’ but laying of more tubes increases the net width ‘W’ and the on-current approximately given by Eq. (5) where gCNT is the
Table 1 Variations of parameters with supply voltage CNFET amplifier parameters
0.9 V
0.7 V
0.5 V
0.3 V
DC Gain 3 DB BW GBP Phase margin Slew rate Settling time (1%) Average power
18.22 10.88 94.47 273.66 34113 0.1 28.802
20.729 4.32 76.966 272.36 20342 0.1 10.926
22.119 1.851 42.389 269.82 8600 0.2 2.2882
20.305 0.4367 7.4131 274.98 774.6 0.9 0.1254
dB GHz GHz Degrees V/us ns lW
3.1. Pure CNFET based amplifier design The amplifier circuit is designed in terms of optimum structural device parameters namely number of perfectly aligned and uniformly spaced nanotubes (N), CNT diameter and uniform inter-nanotube spacing (Pitch, S) in addition to the selection of operating supply voltage. The effective channel length of a CNFET is adjusted for a 32 nm MOS technology (Lgeff ¼12.6 nm) and the widths of CNFET and MOSFET are chosen to be identical for a fair comparison. 3.1.1. Optimum supply voltage Consider a basic CNFET amplifier with device design parameters set to their default design values especially keeping the
Fig. 4. Variation of DC Gain with number of CNTs.
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Fig. 7. Variation of output resistance with number of CNTs. Fig. 5. Variation of bandwidth with number of CNTs.
Fig. 6. Variation of power consumption with number of CNTs.
Fig. 8. Variation of DC gain with CNT diameter.
transconductance per CNT, Ls is the source length (doped CNT region) and rs is the source resistance per unit length of doped CNT. It is worth noting that the total current drive in a CNFET depends both on the number of CNTs per device (‘N’) and the doped source/drain series resistance. The increase in transconductance due to large number of CNTs is much more than the increase in parasitics. This explains the increase in bandwidth with the number of CNTs.
3.1.3. Optimum CNT diameter (DCNT) Analytical results show that with the increase in diameter of the nanotube as shown in Figs. 8–11, the frequency response of CNFET amplifier improves. This is because the transconductance goes up with the increase in diameter of the nanotubes. The DC gain reduces with diameter due to the fact that the lowering of output resistance with diameter is more than the increase in its transconductance. The output current driving capability and slewing performance are enhanced along with the reduction in settling time with the increase in CNT diameter. This trend is observed because CNFET circuit performance and electrical behavior directly depends on the CNT diameter. Diameter is the main parameter that affects the on-current proportionally in a CNFET apart from barrier height at the S/D contact (or RS/D), chirality and oxide thickness but for larger diameters, current tends to saturate due to large screening and scattering effects [13,14,22]. Also, the power consumption of an amplifier goes up due to the smaller band gap and higher current drive. Moreover, the output resistance reduces for larger diameters as shown in Figs. 10 and 11. The bandwidth of the amplifier increases with diameter due to the reduction in gate-to-channel capacitance on account of enhanced CNT to CNT screening and higher value of transconductance [15]. The bandwidth is also affected severely with the increase in load capacitance.
ICNFET
NgCNT ðVDD Vth Þ 1 þ gCNT Ls rS
ð5Þ
Furthermore, transient performance is also enhanced with the increase in the number of tubes due to the corresponding increase in the total current and device speed [13]. The average power dissipation goes up due to fostered interactions among mobile carriers passing through the channel when more than one conducting path exists simultaneously. In addition, current driving capability of CNFET goes up with the large number of tubes which reduces the output resistance, thereby allowing greater fan-out as shown in Figs. 6 and 7. Hence, we conclude that the upper limit on the number of CNTs used is determined by the power-performance trade-off but still looking at the overall performance merits obtained, sufficient number of tubes must be chosen. The optimum value of ‘N’ comes out to be ‘10’.
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Hence, for low loads such as 1 fF in deep submicron, amplifier frequency response is better with unaltered DC gain performance. Therefore, opting for a suitable value of diameter is a compromise between conflicting requirements. Making a selection for the optimal diameter requires the cross-points obtained on the graphs which indicate the optimum value of diameter, corresponding to power limited, moderate bandwidth, high gain application to be around 1.5 nm i.e. chiral vector (19, 0). Moreover, a slight shift could also be observed when opting for optimizing one parameter over the other such as a diameter of 2.0 nm is best for high power, wide bandwidth and moderate gain applications.
Fig. 9. Variation of bandwidth with CNT diameter.
3.1.4. Optimum inter-nanotube spacing, pitch (S) It is clear from Figs. 12–15 that with the increase in pitch i.e. inter-tube spacing, the gain decreases while the bandwidth goes up. This is due to the fact that as CNTs are brought closer, the capacitance from the gate to each CNT channel decreases because each CNT can mirror a small amount of charge from the gate. Moreover, inter-CNT screening effects also tend to reduce the net dynamic gate capacitance and current carrying capability (i.e. drive current per CNT, IPER TUBE). It should not be confused with the current driving capability which now gets strengthened on account of large number of nanotubes for a given gate width. Further, an increase in slew rate is also observed and the output
Fig. 10. Variation of power consumption with CNT diameter. Fig. 12. Variation of DC gain with inter-CNT pitch.
Fig. 11. Variation of output resistance with CNT diameter.
Fig. 13. Variation of bandwidth with inter-CNT pitch.
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take over the ‘p’ and ‘n’ type devices. Once again, with similar analogy and results obtained for pure technology design (refer to Table 1), the optimum supply voltage is assumed to be 0.9 V in this case as well to ensure best overall performance [1].
Fig. 14. Variation of power consumption with inter-CNT pitch.
Fig. 15. Variation of output resistance with inter-CNT pitch.
settles down quickly with large spacing. This is attributed to lower parasitic effects but counteracted by reduced drive current on account of decreased CNT density. Additionally, with larger spacing, the number of current carrying CNTs decreases, thereby, reducing the universal density of states (DOS). This indirectly affects the transconductance given by Eq. (5) and hence explains the trend observed in gain [23,24]. The loss of current due to electrostatic nanotube–nanotube interaction is more than the reduction in load capacitance. Power dissipation goes up due to higher parasitics with the increase in pitch. Compact packing of tubes deteriorates the overall performance and so many tradeoffs are involved which make it difficult to go for an optimum choice of pitch ‘S’. From the plots of Figs. 12–15, we conclude that the optimum choice for pitch is around 10 nm. Going beyond this increases the parasitics without improving ION current, thereby, reducing the performance further [18].
3.2. Hybrid CMOS–CNFET configuration design Hybrid configurations are obtained using nCNFET as current sink and a conventional pMOS transistor as sourcing device or vice versa i.e. nMOS as the sinking device while pCNFET as the sourcing device. This study is useful for deeper analysis of performance delivered by two technologies when they separately
3.2.1. Choice of optimum number of carbon nanotubes Analytical results show that the DC gain decreases slightly while bandwidth improves appreciably with an increase in number of CNTs for both pMOS–nCNFET and pCNFET–nMOS configurations, as shown in Figs. 4 and 5. This is due to the fact that parallel CNTs increases the driving capability of the device but the individual nanotube ION current (i.e. operating current of the device, 20 mA) remains constant owing to constant pitch (center-to-centre distance of CNTs) [17]. With large number of nanotubes ‘N’, apart from higher power dissipation (due to enhanced mobile carrier interactions), area requirement also increases steadily. In contrast to increase in gain observed for pure CNFET amplifier, enhancing the pMOS width in hybrid configurations alongside to maintain the same width as that of nCNFET deteriorates the gain due to the increase in associated MOS parasitics of the source/drain region. This poses a limit on the number of nanotubes chosen to compensate for power-performance tradeoff. Variation in amplifier parameters with varying pCNFET nanotubes is similar to previous case with a difference that now output current driving capability of the device is much better at the cost of increased power dissipation with similar area requirements. This shows that pCNFET offers obvious advantages in terms of very high bandwidth than any other configuration. This is due to the fact that nMOS performs better than pMOS in terms of switching speed and low internal capacitance but the presence of a MOSFET decreases the gain than pure CNFET design due to its current saturation and other short-channel effects that pulls down its transconductance. Higher current drive in nMOS is also the reason behind the superior performance of pCNFET–nMOS over pMOS–nCNFET while pure CNFET design dominates due to the greater flexibility offered by the change in number of nanotubes. The amplifier is designed for large bandwidth, lower output resistance and better transient performance while trading-off both area and power slightly while optimizing ‘N’. Optimum ‘N’ comes out to be around ‘10’ for best performance with little area-power overhead. nMOS–pCNFET configuration offers best transient performance and better driving capability than pure CNFET design. 3.2.2. Choice of optimum CNT diameter For optimum value of ‘N’, we next consider the effect of variations in CNT diameter on circuit performance. It was found from Fig. 10 that large diameter deteriorates the power handling capability as CNTs become more conducting. Diameter is the main parameter that not only affects the source/drain series resistance but also the conductivity of the channel in a CNFET. This is also illustrated in Figs. 8–10 which show the large effect observed by diameter variations on pure technology design than hybrid ones. The bandwidth increases steadily with the increase in diameter due to substantial reduction in parasitic fringe capacitance but at the cost of inferior transient performance [25]. It is even better for nMOS based design because of higher current drive offered by it but at the cost of more power consumption than pMOS based design. High leakage currents and associated leakage power dissipation with nMOS accounts for the large average transient power consumption of the circuit [26]. Power consumption of the circuit is higher with decreasing band gap (or decreasing threshold voltage) due to the increased conduction of pCNFET (or nCNFET) and increased leakage [27]. It was found that without much deterioration in gain, output resistance is reduced sufficiently with increasing diameter due to
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enhanced current driving capabilities of CNTs (to a limited extent) in case the diameter equals 2 nm, thereby, maintaining a proper trade-off between ON and OFF currents e.g. a Ch (22,0) device has been shown to have best On-current while worst OFF current [28]. Since for CNTs of less than 1.3 nm in diameter, only the first subband is degenerate which results in a higher source/drain resistance and a smaller current drive and, therefore, lower speed as shown in Figs. 12–15. Finally, for further diameter increase, bandwidth begins to stabilize as CNFET becomes extremely leaky apart from large screening and scattering effects showing degradation in ION to IOFF current ratio. This results in the decrease of switching time leading to the early settling of the output. A possible solution to enhance the current ratio could be to use smaller length CNT but it comes at the cost of sacrificing the ON-current. 3.2.3. Choice for optimum inter-CNT spacing The key parameters variation for hybrid configurations with pitch is shown in Figs. 12–15. For hybrid configurations, we find that with increasing inter-CNT distance (pitch, S), both gain and frequency response slightly improve. This is due to the fact that as CNTs are brought closer, the capacitance from the gate to each CNT channel decreases because each CNT can mirror a small amount of charge from the gate (assumed to be confined uniformly over the tube). On the other hand, the current carrying capability i.e. IPERTUBE goes down because of screening/imaging effect of the gate charge by neighboring nanotubes in an array affecting the actual potential profile in gate region whereas the current drive is reinforced which highly depends upon the gateto-channel capacitance (Cgc, imaging, typically 1380 pF/mm) [29]. The gain stabilization occurs with increasing pitch due to the additional current provided by the MOSFET in hybrid configurations to compensate for the current loss in CNFET. This is not feasible in case of pure CNFET design because both CNFETs experience a net decrease in their transconductance. As pitch is further increased, the effective drain-source coupling deteriorates and not only width increases but power consumption also gets stabilized. This is due to the fact that only limited interaction is possible which was higher initially because little space was available for charge spreading. High bandwidth is observed in case of pCNFET–nMOS design as shown in Fig. 13. This is due to the dominance of nMOS characteristics initially over the pCNFET and thereafter, the expected balance is restored. Gain initially increases with the increase in width due to steady rise in transconductance at lower widths but at later stages, the transconductance is reduced due to unwanted screening and parasitic effects produced by the extra large width between CNTs leading to gain saturation. Finally, we conclude that for optimum performance without increasing area requirements, the pitch ‘S’ should be set around 15 nm which also provides better slewing performance. Going beyond this increases the parasitics without improving ION current, thereby, reducing the performance [17].
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Hence, there lies an appreciable area-performance trade-off which needs to be overcome when targeting a particular application. Final optimal design parameter values are tabulated in Table 2.
4. Performance comparison of hybrid with pure technology design The simulation results show that pure CNFET outperforms even the hybridized circuits for Gain due to quasi 1-D ballistic transport of electrons and holes (where carrier momentum is conserved), higher drive current (3–4 times than channel MOSFET, typically 42 mA) and large transconductance as expected [20,30,31]. Furthermore, performing scaling of the gate-tochannel capacitance through reductions in gate dielectric thickness and/or using even higher dielectric constant materials, along with reductions in gate length in CNFET is expected to give superior performance over conventional CMOS [29]. Moreover, it is also observed that in case of pMOS–nCNFET configuration, 3 dB bandwidth rises slowly with the increase in parameters like ‘N’, DCNT or S. This is due to the fact that this variation appears to be on account of passive participation of pMOS in current conduction and larger parasitics in comparison with pCNFET at the same place. The pCNFET–nMOS device is best suited for high bandwidth applications offering an increase of 332% in bandwidth and 395% in GBP over conventional CMOS. This exceptional performance seems to be due to good frequency characteristics of nMOS, higher current drive (also apparent from very low output resistance (328% lower)), reduced internal capacitances and parasitics. But unfortunately, it adversely affects the leakage power consumption of the device. On the other hand, it has been observed that pMOS–nCNFET device performs well as far as transient response is concerned. This configuration is suitable for fast switching applications with extremely high slew rate (163% higher) and very low settling times (50% lower) than conventional silicon technology. Furthermore, performance advantage over Si MOSFETs is even greater with shorter CNT channel length because of the smaller effective gate capacitance while having essentially the same drain current. Low power is once again offered by pure CNFET design due to its near 1-D channel, lower capacitance and reduced leakage as compared to other technologies while maintaining the same stability margins as given in Table 2. The CNFET based amplifier circuit is also simulated for different values of temperature ranging from 33 to 87 1C and several inferences have been drawn. It has been observed that higher temperature operation gives good frequency and transient response but enhanced power dissipation and gain reduction as expected while maintaining the same stability margins. This trend is due to the raised thermal energy of carriers which now have frequent collisions than at lower temperatures because of the
Table 2 Comparison of parameters of CNFET, HYBRID technology and Bulk MOSFET inverting amplifiers at 32 nm node Optimum parameters of 32 nm inverting amplifier at CL ¼ 1 fF
Pure CNFET with N ¼10, S ¼ 10 nm, DCNT¼ 1.5 nm
pMOS–nCNFET with N¼ 10, S¼ 15 nm, DCNT¼ 2 nm
pCNFET–nMOS with N¼10, S ¼15 nm, DCNT ¼2 nm
Pure Bulk MOSFET
DC Gain (dB) 3 DB BW (GHz) GBP (GHz) Phase margin Slew rate (V/ls) Settling time (1%) in ns Average power (lW) Output resistance (K)
29.607 1.4451 66.321 267.651 4688.3 0.7 1.5404 23.0675
17.955 3.0239 43.15 277.58 25523 0.1 8.5488 32.378
17.636 10.138 75.991 286.3 4913.6 0.3 15.296 8.661
11.12 2.3476 15.359 284.47 9718 0.2 2.3162 37.058
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reduction in mean free path. This leads to the reduction in current and transconductance [11]. Higher bandwidth is observed due to the decrease in effective charge screening by the gate because of steady loss of ballistic action (or charge loss) due to which each CNT could mirror a small amount of charge. This results in lower capacitance values. Additionally with an increase in thermal energy of carriers, mobile carrier interactions become prominent which accounts for higher leakage power dissipation at higher temperatures. It may also be noted that at low temperatures, CNFET exhibits a number of interesting quantum phenomena such as single-electron charging, quantum interference, Luttinger’s liquid behavior, etc. [32].
5. Conclusion This paper explores the scope, possibilities and challenges involved in replacing dominant silicon technology by the emerging CNT technology in the future for analog applications. This paper successfully investigated the merits and demerits of technology hybridization over conventional pure technologies in terms of key analog design parameters. We conclude that technology hybridization is extremely useful for a concerned application such as nMOS–pCNFET device confers better results in terms of bandwidth and output driving capability while pMOS– nCNFET offers excellent transient performance. Apart from the pros and cons of technology hybridization, area, power and performance tradeoffs are definitely involved. Additionally, diameter of CNT channel plays a vital role in deciding a particular kind of analog or digital application as conductivity and almost all other electronic properties are dependent on it. Hence, we conclude that higher diameter values (2.0 nm) are suitable for high power–high bandwidth applications and vice versa. References [1] Semiconductor Industry Association, International Technology Roadmap for Semiconductors-2005, Update: Overview and Summaries, 2005, Online available: /http://www.itrs.net/Links/2005ITRS/Home2005.htmS. [2] H.A. Javey, H. Kim, M. Brink, Q. Wang, A. Ural, J. Guo, P. McIntyre, P. McEuen, M. Lundstrom, H. Dai, High-k dielectrics for advanced carbon-nanotube transistors and logic gates, Nature Materials 1 (2002) 241–246. [3] D. Akinwande, S. Yasuda, B. Paul, S. Fujita, G. Close, H.-S.P. Wong, Monolithic integration of CMOS VLSI and carbon nanotubes for hybrid nanotechnology applications, IEEE Transactions on Nanotechnology 7 (5) (2008) 636–639. [4] S. Ijima, Helical microtubules of graphitic carbon, Nature 354 (1991) 56–58. [5] Sander J. Tans, Alwin R.M. Verschueren, Cees Dekker, Room-temperature transistor based on a single carbon nanotube, Nature 393 (1998) 49–52. [6] S. Han, X. Liu, C. Zhou, Template-Free directional growth of single-walled carbon nanotubes on a- and r-Plane Sapphire, Journal of American Chemical Society 127 (2005) 5294–5295. [7] Dinkar V. Singh, Keith A. Jenkins, J. Appenzeller, D. Neumayer, A. Grill, H.S.P.hilip Wong, Frequency response of top-gated carbon nanotube fieldeffect transistors, IEEE Transactions on Nanotechnology 3 (3) (2004). [8] I. Amlani., J. Lewis, K. Lee, R. Zhang, J. Deng, H.-S.P. Wong, First demonstration of AC gain from a single-walled carbon nanotube common-source amplifier, IEEE International Electron Devices Meeting (IEDM) (2006) 559–562 San Francisco, CA. [9] A.K. Kureshi, M. Hasan, Comparison of performance of Carbon nanotube FET and bulk CMOS based 6T SRAM cell in deep submicron, Microelectronics Journal 40 (6) (2009) 979–982.
[10] T. Agarwal, A. Sawhney, A.K. Kureshi, M. Hasan, Performance comparison of CNFET and CMOS based full adders at the 32 nm technology node, Proceedings of VLSI Design and Test Symposium (VDAT) (2008) 49–57 Bangalore, India. [11] Paul L. McEuen, Michael Fuhrer, Hongkun Park, Single-walled carbon nanotube electronics, IEEE Transactions on Nanotechnology 1 (1) (2002). [12] /https://www.stanford.edu/group/nanoelectronics/model_downloads. htmS. [13] J. Deng, H.S.P. Wong, A compact SPICE model for carbon nanotube field effect transistors including non-idealities and its application—Part II: full device model and circuit performance benchmarking, IEEE Transactions Electron Devices 54 (12) (2007) 3195–3205. [14] J. Deng, H.S.P. Wong, Modeling and analysis of planar gate capacitance for 1-d fet with multiple cylindrical conducting channels, IEEE Transactions Electron Devices 54 (2007) 2377–2385. [15] J. Deng, H.S.P. Wong, A compact SPICE model for carbon nanotube field effect transistors including non-idealities and its application—Part I: model of the intrinsic channel region, IEEE Transactions Electron Devices 54 (12) (2007) 3186. [16] S. Heinze, M. Radosavljevic, J. Tersoff, P. Avouris, Unexpected scaling of the performance of carbon nanotube Schottky-barrier transistors, Physical review B. Condensed Matter and Materials Physics 68 (23) (2003) 235418.1–235418.5. [17] A. Keshavarzi, A. Raychowdhury, J. Kurtin, K. Roy, Vivek De, Carbon nanotube field-effect transistors for high-performance digital circuits—transient analysis, parasitics, and scalability, IEEE Transactions on Electron Devices 53 (11) (2006). [18] A. Javey, J. Guo, D.B. Farmer, Q. Wang, E. Yenilmez, R.G. Gordon, M. Lundstrom, H. Dai, Self-Aligned ballistic molecular transistors and electrically parallel nanotube arrays, Nano Letters 4 (7) (2004) 1319–1322. [19] J. Deng, H.S.P. Wong, A circuit-compatible spice model for enhancement mode carbon nanotube field effect transistors, Proceeding of the International Conference on Simulation of Semiconductor Processes and Devices (2006) 166–169. [20] J. Appenzeller, Carbon nanotubes for high performance electronics (Invited paper), Proceedings of the IEEE 96 (2) (2008) 206. [21] J. Deng, N. Patil, K. Ryu, A. Badmaev, C. Zhou, S. Mitra, H.-S.P. Wong, Carbon nanotube transistor circuits: circuit-level performance benchmarking and design options for living with imperfections, International Solid State Circuits Conference (ISSCC) (2007) 70–71 San Francisco, CA. [22] A. Balijepalli, S. Sinha and Y. Cao, Compact modeling of carbon nanotube transistor for early stage process-design exploration, in: Proceedings of the 2007 International Symposium on Low Power Electronics and Design, Portland, USA, Aug. 2007, pp. 2–7. [23] S. Sinha, A. Balijepalli, Yu Cao, A simplified model of carbon nanotube transistor with applications to analog and digital design, in: Proceedings of the ninth International Symposium on Quality Electronic Design, 2008, pp. 502–507. [24] J.W. Mintmire, C.T. White, Universal density of states for carbon nanotubes, Physical Review Letters 81 (1998) 2506–2509. [25] R. Saito, G. Dresselhaus, M. Dresselhaus, Physical properties of carbon nanotubes, World Scientific Publishing Co. Inc. (1998). [26] H.P. Wong, David J. Frank, P. Solomon, C.J. Wann, J.J. Welser, Nanoscale CMOS, IEEE Proceedings 87 (4) (1999). [27] A. Raychowdhury, K. Roy, Carbon nanotube electronics: design of highperformance and low power digital circuits, IEEE Transactions on Circuits and Systems-I: Regular Papers 54 (11) (2007). [28] R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, M. Radosavljevic, Benchmarking Nanotechnology for high-performance and low-power logic transistor applications, IEEE Transactions on Nanotechnology 4 (2) (2005) 153–158. [29] S.J. Wind, J. Appenzeller, R. Martel, V. Derycke, Ph. Avouris, Vertical scaling of carbon nanotube field-effect transistors using top gate electrodes, Applied Physics Letters 80 (20) (2002). [30] J. Appenzeller, J. Knoch, V. Derycke, R. Martel, S. Wind, P. Avouris, Fieldmodulated carrier transport in carbon nanotube transistors, Physical Review Letters 89 (2002) 126 801/1–126 801/4. [31] A. Rauchowdhury, S. Mukhopadhyay, K. Roy, in: Modeling of Ballistic CNFETs for Efiicient Circuit Simulation, ICCAD, California, USA, 2003 Nov.11–13. [32] Z. Yao, C. Dekker, P. Avouris, Electrical transport through single-wall carbon nanotubes, in: M.S. Dresselhaus, G. Dresselhaus, P. Avouris (Eds.), Carbon Nanotubes; Topics in Applied Physics, vol. 80, Springer Verlag, Berlin, 2001, pp. 147–171.
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Microelectronics Journal journal homepage: www.elsevier.com/locate/mejo
Carbon nanotube field effect transistors for high performance analog applications: An optimum design approach Fahad Ali Usmani, Mohammad Hasan n Department of Electronics Engineering, Aligarh Muslim University, Aligarh, India
a r t i c l e in fo
abstract
Article history: Received 26 June 2009 Received in revised form 11 April 2010 Accepted 26 April 2010 Available online 15 May 2010
There is a need to explore circuit designs in new emerging technologies for their rapid commercialization to extend Moore’s law beyond 22 nm technology node. Carbon nanotube based transistor (CNFET) has significant potential to replace CMOS in the future due to its better electrostatics and higher mobility. This paper presents a complete optimal design of an inverting amplifier in CMOS, CNFET and hybrid technologies. We investigate and conceptually explain the performance measure of the amplifier at 32 nm technology node in terms of operating voltage, number of carbon nanotubes (CNT), diameter and pitch (inter-nanotube distance) variations of carbon nanotubes in a CNFET transistor in pure and hybrid technologies for area, power and performance optimization. This paper also explores the scope, possibilities and challenges associated with pure CNFET and hybrid amplifiers. We have found that pure CNFET amplifier provided good amplification while hybrid pCNFET–nMOS amplifier offered excellent frequency response and pMOS–nCNFET amplifier gave better transient performance compared with planar CMOS. & 2010 Elsevier Ltd. All rights reserved.
Keywords: Single walled CNT Chirality Carbon nanotube field effect transistor (CNFET) CMOS Analog
1. Introduction CMOS technology is approaching its limits in the presence of challenges like extreme short-channel effects, lithographic limitations, process variations, leakage current and source-to-drain tunneling [1,2]. Many technological and device structure variations have been proposed in the literature like ultra-thin body single or multiple-gate FETs, FinFETs, dynamic threshold MOSFET, SOI FETs and strained silicon etc. to provide improvements in electrostatics over CMOS. Now in order to sustain Moore’s Law and to ensure further improvement in FET performance, it is necessary to look for alternatives like CNFETs that promise to deliver much better performance than existing MOSFETs. CNFET technology can also be easily clubbed with the bulk CMOS technology on a single chip and utilizes the same infrastructure [3]. They are being looked upon as promising devices due to lower leakage power with continued scaling. Since in CNFET, SiO2 surrounds the carbon nanotube which is the only path to allow current to flow showing a behavior similar to ultra-thin body FET. Moreover, high gate capacitance provides strong gate control of the channel potential by the use of high-k dielectrics such as HfO2 (typically 3 nm thick) for gate insulation, thereby, reducing shortchannel effects due to increased capacitive coupling [2]. In 1991, for the first time, multi-walled carbon nanotubes were discovered by Ijima [4] and later in 1998, their semiconducting
n
Corresponding author. E-mail addresses: [email protected] (F. Ali Usmani), mohd.hasan@ mail.amu.ac.in, [email protected] (M. Hasan). 0026-2692/$ - see front matter & 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2010.04.011
behavior was reported [5]. Thereafter, their conductive, structural, electrical, thermal properties, etc. were studied extensively and many possible applications such as in field emission displays, field-effect transistors, optical fibers, chemical sensors, etc. were experimentally demonstrated. This nanoscale alternative offers vast possibilities along with serious challenges like their commercial integration, growth and placement of CNTs, chirality control and enabling process and technologies [6]. The DC and AC performance of a CNFET has already been analyzed and measured [7,8]. There has been a lot of work available in the literature on the digital applications of CNFET but its analog applications have not been explored [9,10]. This paper investigates in detail for the first time the performance and reliability of pure and hybrid CMOS–CNFET technologies based analog amplifier and to propose their suitability in a wide range of high performance analog circuit and system applications. The paper also explores area, power and performance optimization of the amplifier. It begins with an overview of CNFET transistor and device design specifications in Section 2. Section 3 covers the optimum design of pure and hybrid inverting amplifiers. Section 4 discusses the comparison of pure and hybrid amplifiers at 32 nm technology node followed by conclusion in Section 5.
2. Carbon nanotube field effect transistor A single walled carbon nanotube (SWCNT) is a one-dimensional conductor, shown in Fig. 1(a), that can be either metallic or semiconducting depending upon the arrangement of carbon
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atoms decided by their Chirality, Ch (i.e. the direction in which the graphene sheet is rolled) whose magnitude and relationship with CNT diameter (DCNT) is given by Eqs. (1) and (2) respectively where ‘a’ is the graphene lattice constant (0.249 nm) and n1, n2 are positive integers that specify the chirality of the tube. qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Ch ¼ a n21 þn22 þ n1 n2 ð1Þ DCNT ¼ C h = p
ð2Þ
It also defines that SWCNT is a sheet of graphite which is rolled up and joined together along a wrapping vector Ch ¼n1.a1 + n2.a2, as shown in Fig. 1(b), where a1, a2 are unit vectors. A MOS-like carbon nanotube transistor (CNFET) is obtained by replacing the channel of a conventional MOSFET by a number of semiconducting carbon nanotubes, as shown in Fig. 2 and its cross-section in Fig. 3 [11]. The source and drain are the n + (or p+ ) doped semiconducting CNTs with Pd metal contacts for n (or p )-type CNFETs. Doped CNTs act as both the source/drain extension region and/or interconnects between two adjacent devices. It should be noted that CNT channel is undoped while all other regions are heavily doped [13]. The number of carbon nanotubes in the channel depends on the current drive requirement. The carrier transport between source and drain will now take place through these narrow carbon nanotubes. The operation principle of CNFET is similar to a traditional MOSFET. Since the electrons are only confined to the narrow nanotube, the mobility goes up substantially on account of ballistic transport as compared with the bulk MOSFET. CNFET has the potential of taking over in the post silicon era due to their exceptional electrical and structural characteristics such as quasi 1-D (ballistic) transport of electrons (and equally likely for holes), higher drive current (3–4 times than MOSFETs) and large transconductance, low intrinsic capacitance, near ideal sub-threshold slope, high temperature resilience and strong covalent bonding, etc. [11]. This strong covalent bonding allows the use of high-k dielectric gate material and considerable reduction in oxide thickness without any substantial degradation in performance. A CNFET exhibits unipolar behavior and operates on the principle of barrier height modulation by application of the gate potential. An additional advantage of the top gate structure apart from better current handling and reduced leakage current is that with only slight modification, it can be made suitable for high frequency operation, which is not possible with back-gated devices due to the large overlap capacitance between the gate, source, and drain [11]. CNFET offers superior carrier transport and conduction characteristics over silicon devices because of the
remarkable properties of SWCNTs which are actually derived from the unusual electronic structure of 2-D graphene sheet. Especially, the high mobility is largely due to lack of surface states and high current density could be attributed to the strong covalent bonding of atoms in the tube. The surface state problem is solved elegantly due to the absence of chemically reactive dangling bonds responsible for surface scattering. The CNT diameter, the width of the CNFET transistor (W), number of CNTs in the channel of a CNFET (N), inter-nanotube spacing (S) are related by Eq. (3). The Band gap energy (Sg) and
Fig. 2. 3D CNFET structure.
Wgate Pitch Dielectric ( ) (Kgate)
Drain Ldd Lg
(number of CNTs))
Gate t
Drain
Source Csub
Gate Lss
tubes
CNTs
Substrate
Source
Fig. 3. Schematic CNFET cross-section.
Fig. 1. (a) SWCNT (b) Graphite sheet in terms of Chirality, n1 and n2
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threshold voltage (Vth) of the intrinsic CNT channel are related by Eq. (4) where ‘acc’ is the carbon-to-carbon bond distance (0.1412 nm for graphite), ‘e’ is the unit electron charge and ‘t’ is the carbon-to-carbon bond energy (3.0 eV). W ¼ ðN1ÞS þDCNT
Sg ðeVÞ ¼
2acc t 0:84 eV ¼ 2 eVth DCNT ðnmÞ DCNT ðnmÞ
ð3Þ ð4Þ
The high performance Verilog-A Stanford model has been used for analyzing the performance of CNFET transistor [12]. The CNFET model successfully accounts for its device parasitics and practical non-idealities including the channel length dependence of current drive, the finite scattering mean free path, the source/ drain series resistance, the source/drain contact resistance, the geometry dependence of the gate-to-channel capacitance, the interconnect wiring capacitance, scattering and inter-CNT charge screening effects etc. apart from accurate predictions of dynamic and transient performance with more than 90% accuracy. Chirality control problem has been partially addressed during the current derivation and the chirality difference for SWCNTs with same diameter have been ignored for our purpose, in the range where the carrier energy is less than 1.0 eV for sub-1 V power supply circuit applications [13–16].
3. CMOS inverting amplifier CMOS inverting amplifier is a basic analog building block with simple architecture apart from uncomplicated design and ease of analysis. It offers much insight into the operational and design summary of more complex analog and mixed signal circuits. The widely used BSIMv4.6.1 Berkeley Predictive Technology Model has been used for the MOSFET at the 32 nm technology node. Operating environment is chosen under proper biasing for a capacitive load of 1 fF in addition to negligible intrinsic device capacitances ( 2–5 aF/nanotube) and parasitics (including fringe and overlap capacitances) as low as 0.1 fF/nanotube for a 32 nm CNFET device [17]. A typical CNFET with 4-nm-thick planar HfO2 (k1 ¼16) gate oxide and SiO2 (k2 ¼ 3.9) substrate, fabricated with Pd source/drain metal contacts and Al gate electrode is used in simulation [18]. Analysis assumes that CNFETs are made up of homogeneous and identical semiconducting CNTs that have the same chirality and the same doping level. For hybrid or pure technology designs, p- or/and n-type MOSFET has been replaced by the corresponding p- or/and ncNFET without changing their gate widths as given by Eq. (3). Thereafter, their analog performance metrics such as gain, bandwidth, gain-bandwidth product (GBP), slewing performance, settling time, average power dissipation, output resistance etc. and optimum device design specifications are investigated through HSPICEs simulations.
397
minimum pitch to be greater than twice the diameter for same width as that of a CMOS design. Since below the minimum pitch, both the gate capacitance and the drive current of CNTs in the middle are smaller in comparison to those at the edges. This is due to the screening effect produced by adjacent CNTs which poses a maximum limit on the number of CNTs in the channel of a CNFET for optimal performance [15]. By studying the effect of parameter variations with supply voltage, VDD as depicted in Table 1, it was found that for best performance, the supply voltage must be set around 0.9 V. The lowering of supply voltage decreases the power consumption due to proportional scaling but it also affects the circuit slew rate and settling time. This is due to lower output swing and pronounced effect of parasitics which deteriorates the bandwidth of the amplifier. As expected, almost all other parameters improve but due to lower swing, robustness deteriorates. 3.1.2. Optimum number of CNTs (N) It is important to determine the number of CNTs to be used in an array in order to ensure sufficient current supply for driving fixed capacitive loads as single nanotube based transistor does not provide competitive performance over traditional silicon devices [18,19]. It can be inferred from Figs. 4 and 5 that with the increase in ‘N’, both gain and bandwidth improve somewhat parabolically. This is due to the significant increase in transconductance with the increase in number of nanotubes [20,21]. It is important to investigate the problem associated with large number of tubes in addition to geometrical constraints. Here, the current per tube IPERTUBE ( 20 mA) is constant owing to non-varying ‘S’ but laying of more tubes increases the net width ‘W’ and the on-current approximately given by Eq. (5) where gCNT is the
Table 1 Variations of parameters with supply voltage CNFET amplifier parameters
0.9 V
0.7 V
0.5 V
0.3 V
DC Gain 3 DB BW GBP Phase margin Slew rate Settling time (1%) Average power
18.22 10.88 94.47 273.66 34113 0.1 28.802
20.729 4.32 76.966 272.36 20342 0.1 10.926
22.119 1.851 42.389 269.82 8600 0.2 2.2882
20.305 0.4367 7.4131 274.98 774.6 0.9 0.1254
dB GHz GHz Degrees V/us ns lW
3.1. Pure CNFET based amplifier design The amplifier circuit is designed in terms of optimum structural device parameters namely number of perfectly aligned and uniformly spaced nanotubes (N), CNT diameter and uniform inter-nanotube spacing (Pitch, S) in addition to the selection of operating supply voltage. The effective channel length of a CNFET is adjusted for a 32 nm MOS technology (Lgeff ¼12.6 nm) and the widths of CNFET and MOSFET are chosen to be identical for a fair comparison. 3.1.1. Optimum supply voltage Consider a basic CNFET amplifier with device design parameters set to their default design values especially keeping the
Fig. 4. Variation of DC Gain with number of CNTs.
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Fig. 7. Variation of output resistance with number of CNTs. Fig. 5. Variation of bandwidth with number of CNTs.
Fig. 6. Variation of power consumption with number of CNTs.
Fig. 8. Variation of DC gain with CNT diameter.
transconductance per CNT, Ls is the source length (doped CNT region) and rs is the source resistance per unit length of doped CNT. It is worth noting that the total current drive in a CNFET depends both on the number of CNTs per device (‘N’) and the doped source/drain series resistance. The increase in transconductance due to large number of CNTs is much more than the increase in parasitics. This explains the increase in bandwidth with the number of CNTs.
3.1.3. Optimum CNT diameter (DCNT) Analytical results show that with the increase in diameter of the nanotube as shown in Figs. 8–11, the frequency response of CNFET amplifier improves. This is because the transconductance goes up with the increase in diameter of the nanotubes. The DC gain reduces with diameter due to the fact that the lowering of output resistance with diameter is more than the increase in its transconductance. The output current driving capability and slewing performance are enhanced along with the reduction in settling time with the increase in CNT diameter. This trend is observed because CNFET circuit performance and electrical behavior directly depends on the CNT diameter. Diameter is the main parameter that affects the on-current proportionally in a CNFET apart from barrier height at the S/D contact (or RS/D), chirality and oxide thickness but for larger diameters, current tends to saturate due to large screening and scattering effects [13,14,22]. Also, the power consumption of an amplifier goes up due to the smaller band gap and higher current drive. Moreover, the output resistance reduces for larger diameters as shown in Figs. 10 and 11. The bandwidth of the amplifier increases with diameter due to the reduction in gate-to-channel capacitance on account of enhanced CNT to CNT screening and higher value of transconductance [15]. The bandwidth is also affected severely with the increase in load capacitance.
ICNFET
NgCNT ðVDD Vth Þ 1 þ gCNT Ls rS
ð5Þ
Furthermore, transient performance is also enhanced with the increase in the number of tubes due to the corresponding increase in the total current and device speed [13]. The average power dissipation goes up due to fostered interactions among mobile carriers passing through the channel when more than one conducting path exists simultaneously. In addition, current driving capability of CNFET goes up with the large number of tubes which reduces the output resistance, thereby allowing greater fan-out as shown in Figs. 6 and 7. Hence, we conclude that the upper limit on the number of CNTs used is determined by the power-performance trade-off but still looking at the overall performance merits obtained, sufficient number of tubes must be chosen. The optimum value of ‘N’ comes out to be ‘10’.
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Hence, for low loads such as 1 fF in deep submicron, amplifier frequency response is better with unaltered DC gain performance. Therefore, opting for a suitable value of diameter is a compromise between conflicting requirements. Making a selection for the optimal diameter requires the cross-points obtained on the graphs which indicate the optimum value of diameter, corresponding to power limited, moderate bandwidth, high gain application to be around 1.5 nm i.e. chiral vector (19, 0). Moreover, a slight shift could also be observed when opting for optimizing one parameter over the other such as a diameter of 2.0 nm is best for high power, wide bandwidth and moderate gain applications.
Fig. 9. Variation of bandwidth with CNT diameter.
3.1.4. Optimum inter-nanotube spacing, pitch (S) It is clear from Figs. 12–15 that with the increase in pitch i.e. inter-tube spacing, the gain decreases while the bandwidth goes up. This is due to the fact that as CNTs are brought closer, the capacitance from the gate to each CNT channel decreases because each CNT can mirror a small amount of charge from the gate. Moreover, inter-CNT screening effects also tend to reduce the net dynamic gate capacitance and current carrying capability (i.e. drive current per CNT, IPER TUBE). It should not be confused with the current driving capability which now gets strengthened on account of large number of nanotubes for a given gate width. Further, an increase in slew rate is also observed and the output
Fig. 10. Variation of power consumption with CNT diameter. Fig. 12. Variation of DC gain with inter-CNT pitch.
Fig. 11. Variation of output resistance with CNT diameter.
Fig. 13. Variation of bandwidth with inter-CNT pitch.
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take over the ‘p’ and ‘n’ type devices. Once again, with similar analogy and results obtained for pure technology design (refer to Table 1), the optimum supply voltage is assumed to be 0.9 V in this case as well to ensure best overall performance [1].
Fig. 14. Variation of power consumption with inter-CNT pitch.
Fig. 15. Variation of output resistance with inter-CNT pitch.
settles down quickly with large spacing. This is attributed to lower parasitic effects but counteracted by reduced drive current on account of decreased CNT density. Additionally, with larger spacing, the number of current carrying CNTs decreases, thereby, reducing the universal density of states (DOS). This indirectly affects the transconductance given by Eq. (5) and hence explains the trend observed in gain [23,24]. The loss of current due to electrostatic nanotube–nanotube interaction is more than the reduction in load capacitance. Power dissipation goes up due to higher parasitics with the increase in pitch. Compact packing of tubes deteriorates the overall performance and so many tradeoffs are involved which make it difficult to go for an optimum choice of pitch ‘S’. From the plots of Figs. 12–15, we conclude that the optimum choice for pitch is around 10 nm. Going beyond this increases the parasitics without improving ION current, thereby, reducing the performance further [18].
3.2. Hybrid CMOS–CNFET configuration design Hybrid configurations are obtained using nCNFET as current sink and a conventional pMOS transistor as sourcing device or vice versa i.e. nMOS as the sinking device while pCNFET as the sourcing device. This study is useful for deeper analysis of performance delivered by two technologies when they separately
3.2.1. Choice of optimum number of carbon nanotubes Analytical results show that the DC gain decreases slightly while bandwidth improves appreciably with an increase in number of CNTs for both pMOS–nCNFET and pCNFET–nMOS configurations, as shown in Figs. 4 and 5. This is due to the fact that parallel CNTs increases the driving capability of the device but the individual nanotube ION current (i.e. operating current of the device, 20 mA) remains constant owing to constant pitch (center-to-centre distance of CNTs) [17]. With large number of nanotubes ‘N’, apart from higher power dissipation (due to enhanced mobile carrier interactions), area requirement also increases steadily. In contrast to increase in gain observed for pure CNFET amplifier, enhancing the pMOS width in hybrid configurations alongside to maintain the same width as that of nCNFET deteriorates the gain due to the increase in associated MOS parasitics of the source/drain region. This poses a limit on the number of nanotubes chosen to compensate for power-performance tradeoff. Variation in amplifier parameters with varying pCNFET nanotubes is similar to previous case with a difference that now output current driving capability of the device is much better at the cost of increased power dissipation with similar area requirements. This shows that pCNFET offers obvious advantages in terms of very high bandwidth than any other configuration. This is due to the fact that nMOS performs better than pMOS in terms of switching speed and low internal capacitance but the presence of a MOSFET decreases the gain than pure CNFET design due to its current saturation and other short-channel effects that pulls down its transconductance. Higher current drive in nMOS is also the reason behind the superior performance of pCNFET–nMOS over pMOS–nCNFET while pure CNFET design dominates due to the greater flexibility offered by the change in number of nanotubes. The amplifier is designed for large bandwidth, lower output resistance and better transient performance while trading-off both area and power slightly while optimizing ‘N’. Optimum ‘N’ comes out to be around ‘10’ for best performance with little area-power overhead. nMOS–pCNFET configuration offers best transient performance and better driving capability than pure CNFET design. 3.2.2. Choice of optimum CNT diameter For optimum value of ‘N’, we next consider the effect of variations in CNT diameter on circuit performance. It was found from Fig. 10 that large diameter deteriorates the power handling capability as CNTs become more conducting. Diameter is the main parameter that not only affects the source/drain series resistance but also the conductivity of the channel in a CNFET. This is also illustrated in Figs. 8–10 which show the large effect observed by diameter variations on pure technology design than hybrid ones. The bandwidth increases steadily with the increase in diameter due to substantial reduction in parasitic fringe capacitance but at the cost of inferior transient performance [25]. It is even better for nMOS based design because of higher current drive offered by it but at the cost of more power consumption than pMOS based design. High leakage currents and associated leakage power dissipation with nMOS accounts for the large average transient power consumption of the circuit [26]. Power consumption of the circuit is higher with decreasing band gap (or decreasing threshold voltage) due to the increased conduction of pCNFET (or nCNFET) and increased leakage [27]. It was found that without much deterioration in gain, output resistance is reduced sufficiently with increasing diameter due to
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enhanced current driving capabilities of CNTs (to a limited extent) in case the diameter equals 2 nm, thereby, maintaining a proper trade-off between ON and OFF currents e.g. a Ch (22,0) device has been shown to have best On-current while worst OFF current [28]. Since for CNTs of less than 1.3 nm in diameter, only the first subband is degenerate which results in a higher source/drain resistance and a smaller current drive and, therefore, lower speed as shown in Figs. 12–15. Finally, for further diameter increase, bandwidth begins to stabilize as CNFET becomes extremely leaky apart from large screening and scattering effects showing degradation in ION to IOFF current ratio. This results in the decrease of switching time leading to the early settling of the output. A possible solution to enhance the current ratio could be to use smaller length CNT but it comes at the cost of sacrificing the ON-current. 3.2.3. Choice for optimum inter-CNT spacing The key parameters variation for hybrid configurations with pitch is shown in Figs. 12–15. For hybrid configurations, we find that with increasing inter-CNT distance (pitch, S), both gain and frequency response slightly improve. This is due to the fact that as CNTs are brought closer, the capacitance from the gate to each CNT channel decreases because each CNT can mirror a small amount of charge from the gate (assumed to be confined uniformly over the tube). On the other hand, the current carrying capability i.e. IPERTUBE goes down because of screening/imaging effect of the gate charge by neighboring nanotubes in an array affecting the actual potential profile in gate region whereas the current drive is reinforced which highly depends upon the gateto-channel capacitance (Cgc, imaging, typically 1380 pF/mm) [29]. The gain stabilization occurs with increasing pitch due to the additional current provided by the MOSFET in hybrid configurations to compensate for the current loss in CNFET. This is not feasible in case of pure CNFET design because both CNFETs experience a net decrease in their transconductance. As pitch is further increased, the effective drain-source coupling deteriorates and not only width increases but power consumption also gets stabilized. This is due to the fact that only limited interaction is possible which was higher initially because little space was available for charge spreading. High bandwidth is observed in case of pCNFET–nMOS design as shown in Fig. 13. This is due to the dominance of nMOS characteristics initially over the pCNFET and thereafter, the expected balance is restored. Gain initially increases with the increase in width due to steady rise in transconductance at lower widths but at later stages, the transconductance is reduced due to unwanted screening and parasitic effects produced by the extra large width between CNTs leading to gain saturation. Finally, we conclude that for optimum performance without increasing area requirements, the pitch ‘S’ should be set around 15 nm which also provides better slewing performance. Going beyond this increases the parasitics without improving ION current, thereby, reducing the performance [17].
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Hence, there lies an appreciable area-performance trade-off which needs to be overcome when targeting a particular application. Final optimal design parameter values are tabulated in Table 2.
4. Performance comparison of hybrid with pure technology design The simulation results show that pure CNFET outperforms even the hybridized circuits for Gain due to quasi 1-D ballistic transport of electrons and holes (where carrier momentum is conserved), higher drive current (3–4 times than channel MOSFET, typically 42 mA) and large transconductance as expected [20,30,31]. Furthermore, performing scaling of the gate-tochannel capacitance through reductions in gate dielectric thickness and/or using even higher dielectric constant materials, along with reductions in gate length in CNFET is expected to give superior performance over conventional CMOS [29]. Moreover, it is also observed that in case of pMOS–nCNFET configuration, 3 dB bandwidth rises slowly with the increase in parameters like ‘N’, DCNT or S. This is due to the fact that this variation appears to be on account of passive participation of pMOS in current conduction and larger parasitics in comparison with pCNFET at the same place. The pCNFET–nMOS device is best suited for high bandwidth applications offering an increase of 332% in bandwidth and 395% in GBP over conventional CMOS. This exceptional performance seems to be due to good frequency characteristics of nMOS, higher current drive (also apparent from very low output resistance (328% lower)), reduced internal capacitances and parasitics. But unfortunately, it adversely affects the leakage power consumption of the device. On the other hand, it has been observed that pMOS–nCNFET device performs well as far as transient response is concerned. This configuration is suitable for fast switching applications with extremely high slew rate (163% higher) and very low settling times (50% lower) than conventional silicon technology. Furthermore, performance advantage over Si MOSFETs is even greater with shorter CNT channel length because of the smaller effective gate capacitance while having essentially the same drain current. Low power is once again offered by pure CNFET design due to its near 1-D channel, lower capacitance and reduced leakage as compared to other technologies while maintaining the same stability margins as given in Table 2. The CNFET based amplifier circuit is also simulated for different values of temperature ranging from 33 to 87 1C and several inferences have been drawn. It has been observed that higher temperature operation gives good frequency and transient response but enhanced power dissipation and gain reduction as expected while maintaining the same stability margins. This trend is due to the raised thermal energy of carriers which now have frequent collisions than at lower temperatures because of the
Table 2 Comparison of parameters of CNFET, HYBRID technology and Bulk MOSFET inverting amplifiers at 32 nm node Optimum parameters of 32 nm inverting amplifier at CL ¼ 1 fF
Pure CNFET with N ¼10, S ¼ 10 nm, DCNT¼ 1.5 nm
pMOS–nCNFET with N¼ 10, S¼ 15 nm, DCNT¼ 2 nm
pCNFET–nMOS with N¼10, S ¼15 nm, DCNT ¼2 nm
Pure Bulk MOSFET
DC Gain (dB) 3 DB BW (GHz) GBP (GHz) Phase margin Slew rate (V/ls) Settling time (1%) in ns Average power (lW) Output resistance (K)
29.607 1.4451 66.321 267.651 4688.3 0.7 1.5404 23.0675
17.955 3.0239 43.15 277.58 25523 0.1 8.5488 32.378
17.636 10.138 75.991 286.3 4913.6 0.3 15.296 8.661
11.12 2.3476 15.359 284.47 9718 0.2 2.3162 37.058
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reduction in mean free path. This leads to the reduction in current and transconductance [11]. Higher bandwidth is observed due to the decrease in effective charge screening by the gate because of steady loss of ballistic action (or charge loss) due to which each CNT could mirror a small amount of charge. This results in lower capacitance values. Additionally with an increase in thermal energy of carriers, mobile carrier interactions become prominent which accounts for higher leakage power dissipation at higher temperatures. It may also be noted that at low temperatures, CNFET exhibits a number of interesting quantum phenomena such as single-electron charging, quantum interference, Luttinger’s liquid behavior, etc. [32].
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