Combinational Logic
Digital Logic Design Combinational Logic
Module 2: Combinational Logic - Analysis Wakerly: Chapter 4 (part 1) Digital Logic Design: ECEN 3233 Dr. Keith A. Teague Spring 2003 Read Chapter 4, through Sec. 4.2 1
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Digital Logic Design Combinational Logic
Outline Amplification on the Concepts of Module 1: • Multiple Design Representations Truth Tables Gate descriptions •Logic Functions and Switches Not, AND, OR, NAND, NOR, XOR, XNOR • Gate Logic Laws and Theorems of Boolean Algebra Two Level Canonical Forms
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Boolean Algebra
Digital Logic Design Combinational Logic
• Sometimes called “switching algebra” – Deals with Boolean values: 0,1
• Positive-logic convention – Analog voltages LOW, HIGH Æ 0,1 – Negative logic is seldom used
• Signal values are denoted by variables – X, Y, Z, FRED, ERROR_L, etc. – These should usually be descriptive (like variables in a program), but for our uses it’s easier to keep them short!
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A Boolean Algebra
Digital Logic Design Combinational Logic
Algebraic structure consisting of: set of elements B binary operations {+, •} unary operation {'} such that the following axioms hold: 1.
The set B contains at least two elements, a, b, such that a is not equal to b
2. Closure: for every a,b in the set B, (i) a + b is in B (ii) a • b is in B 3. Commutative Laws: for every a,b in B, (i) a + b = b + a (ii) a • b = b • a 4. Identities: 0, 1 in B (i) a + 0 = a (ii) a • 1 = a 2003
5. Distributive Laws: (i) a + (b • c) = (a + b) • (a + c) (ii) a • (b + c) = a • b + a • c 6. Complement: (i) a + a' = 1 (ii) a • a' = 0 4
Digital Logic Design
Boolean Algebra Combinational Logic B = {0,1}, + = OR, • = AND, ' = NOT is a Boolean Algebra Must verify that the axioms hold: E.g., Commutative Law: 0 + 1 = 1 + 0? 0 • 1 = 1 • 0? 1=1 0=0 Theorem: any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using ', +, • Description If X = 0 then X ' = 1 If X = 1 then X ' = 0
Description Z = 1 if X and Y are both 1
Gates X
Truth Table X
X Y
Z
Description Z = 1 if X or Y (or both) are 1
X 0 1
X 1 0
NOT
Truth Table X Y Z 0 0 0 0 1 0 1 0 0 1 1 1
AND
Truth T able X Y
Z
X 0 0 1 1
Y 0 1 0 1
Z 0 1 1 1
OR
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More definitions
Digital Logic Design Combinational Logic
• Literal: a variable or its complement – X, X′, FRED′, CS_L
• Expression: literals combined by AND, OR, parentheses, complementation – – – –
X+Y P⋅Q⋅R A+B⋅C ((FRED ⋅ Z′) + CS_L ⋅ A ⋅ B′ ⋅ C + Q5) ⋅ RESET′
• Equation: Variable = expression – P = ((FRED ⋅ Z′) + CS_L ⋅ A ⋅ B′ ⋅ C + Q5) ⋅ RESET′
• Complete: The set of operators AND, OR and NOT is called complete since any Boolean function can be represented using only these operators. Other operators, or sets of operators, are also complete. 2003
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Laws of Boolean Algebra
Digital Logic Design Combinational Logic
Duality: a dual of a Boolean expression is derived by replacing AND operations by ORs, OR operations by ANDs, constant 0s by 1s, and 1s by 0s (literals are left unchanged). Any statement that is true for an expression is also true for its dual! Useful Laws/Theorems of Boolean Algebra: Operations with 0 and 1: 1D. X • 1 = X 1. X + 0 = X 2D. X • 0 = 0 2. X + 1 = 1 Idempotent Law: 3. X + X = X
3D. X • X = X
Involution Law: 4. (X')' = X Laws of Complementarity: 5. X + X' = 1
5D. X • X' = 0
Commutative Law: 6. X + Y = Y + X
6D. X • Y = Y • X
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Laws of Boolean Algebra (cont) Associative Laws: 7. (X + Y) + Z = X + (Y + Z) =X+Y+Z Distributive Laws: 8. X • (Y+ Z) = (X • Y) + (X • Z)
Digital Logic Design Combinational Logic
7D. (X • Y) • Z = X • (Y • Z) =X•Y•Z 8D. X + (Y• Z) = (X + Y) • (X + Z)
Simplification Theorems (combining, covering): 9. X • Y + X • Y' = X 9D. (X + Y) • (X + Y') = X 10. X + X • Y = X 10D. X • (X + Y) = X 11. (X + Y') • Y = X • Y 11D. (X • Y') + Y = X + Y DeMorgan's Law: 12. (X + Y + Z + ...)' = X' • Y' • Z' • ... 12D. (X • Y • Z • ...) ' = X' + Y' + Z' + ... 13. {F(X1,X2,...,Xn,0,1,+,•)}' = {F(X1',X2',...,Xn',1,0,•,+)} Duality: 14. (X + Y + Z + ...) D = X • Y • Z • ...
14D. (X •FY • Z • ...)D = X + Y + Z + ...
15. {F(X1,X2,...,Xn,0,1,+,•)}D = {F(X1,X2,...,Xn,1,0,•,+)} Theorems for Multiplying and Factoring: 16. (X + Y) • (X' + Z) = X • Z + X' • Y 16D. X • Y + X' • Z = (X + Z) • (X' + Y) Consensus Theorem: 17. (X • Y) + (Y • Z) + (X' • Z) = X • Y + X' • Z 2003
17D. (X + Y) • (Y + Z) • (X' + Z) = (X + Y) • (X' + Z) 8
Digital Logic Design Combinational Logic
Laws of Boolean Algebra Proving theorems via axioms of Boolean Algebra: E.g., prove the theorem: X • Y + X • Y' = X distributive law (8)
X • Y + X •Y' = X • (Y + Y')
complementary law (5)
X • (Y + Y')
= X • (1)
identity (1D)
X • (1)
=X
E.g., prove the theorem: X + X • Y
= X
identity (1D)
X + X•Y
= X•1 + X•Y
distributive law (8)
X • 1 + X • Y = X • (1 + Y)
identity (2)
X • (1 + Y)
= X • (1)
identity (1)
X • (1)
= X
Parentheses and operator precedence are important - parentheses are used to group operations - multiplication (AND) has precedence over addition (OR) 9
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Digital Logic Design Combinational Logic
NAND, NOR, XOR, XNOR 16 functions of two variables: X Y 0 0 0 1 1 0 1 1
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
X• Y
X
NAND
NOR
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Y
X+Y
Y
Description Z = 1 if X is 0 or Y is 0
Description Z = 1 if both X and Y are 0
X, X', Y, Y', X•Y, X+Y, 0, 1 only half of the possible functions 1
X
Gates X Y
Truth T able X Y Z 0 0 1 0 1 1 1 0 1 1 1 0
Z
Gates X Y
Truth T able Z
X 0 0 1 1
Y 0 1 0 1
Z 1 0 0 0
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Digital Logic Design Combinational Logic
NAND, NOR
NAND, NOR gates far outnumber AND, OR in typical designs - easier to construct in the underlying transistor technologies Any Boolean expression can be implemented by NAND, NOR, NOT gates In fact, NOT is superfluous (NOT = NAND or NOR with both inputs tied together) X 0
Y 0
X NOR Y 1
X 0
Y X NAND Y 0 1
1
1
0
1
1
0
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Digital Logic Design Combinational Logic
NAND, NOR DeMorgan's Law (X + Y)' = X' • Y' NOR is equivalent to AND with inputs complemented
(X • Y)' = X' + Y' NAND is equivalent to OR with inputs complemented
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X 0 0 1 1
Y 0 1 0 1
X 1 1 0 0
Y 1 0 1 0
X 0 0 1 1
Y 0 1 0 1
X 1 1 0 0
Y 1 0 1 0
X +Y 1 0 0 0
X•Y 1 0 0 0
X•Y X +Y 1 1 1 1 1 1 0 0
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DeMorgan Symbol Equivalence
Digital Logic Design Combinational Logic
NAND Equivalence
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DeMorgan Symbol Equivalence
Digital Logic Design Combinational Logic
Likewise for OR -
NOR Equivalence
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Digital Logic Design Combinational Logic
DeMorgan Symbols / Logical Equivalence
It is sometimes useful to make substitutions using these identities.
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Digital Logic Design Combinational Logic
XOR, XNOR
XOR: X or Y but not both ("inequality", "difference") XNOR: X and Y are the same ("equality", "coincidence") Description Z = 1 if X has a different value than Y
Description Z = 1 if X has the same value as Y
Gates
Gates
X
Z
Y Truth T able
Z
Y Truth T able
X 0 0 1 1
Y 0 1 0 1
(a) XOR
X ⊕ Y = X Y' + X' Y 2003
X
Z 0 1 1 0
X 0 0 1 1
Y 0 1 0 1
Z 1 0 0 1
(b) XNOR
X ⊕ Y = X Y + X' Y' 16
Digital Logic Design Combinational Logic
DeMorgan’s Law
DeMorgan's DeMorgan'sLaw Lawcan canbe beused usedto toconvert convertAND/OR AND/ORexpressions expressions to toOR/AND OR/ANDexpressions expressions Example: Z = A' B' C + A' B C + A B' C + A B C' Z' = (A + B + C') • (A + B' + C') • (A' + B + C') • (A' + B' + C)
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Digital Logic Design Combinational Logic
Example f(A,B,C,D) = AB’C + (A’ + B + D) (ABD’ + B’)
Find f’
f’(A,B,C,D) = [ AB’C + (A’ + B + D) (ABD’ + B’) ]’ Use DeMorgan’s Law - then simplify = ( AB’C )’ [ ( A’ + B + D )’ + ( ABD’ + B’ )’ ] = (A’ + B + C’ ) [ AB’D’ + (( ABD’ )’ B) ] = (A’ + B + C’ ) [ AB’D’ + (A’ + B’ + D ) B ] = (A’ + B + C’ ) [ AB’D’ + A’B + B’B + BD ]
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Digital Logic Design Combinational Logic
Example (continued) From previous slide -
f’(A,B,C,D) = (A’ + B + C’ ) [ AB’D’ + A’B + B’B + BD ]
= A’AB’D’ + A’A’B + A’BD + BAB’D’ + BA’B + BBD + C’AB’D’ + C’A’B + C’BD
= A’B + A’BD + A’B + BD + AB’C’D’ + A’BC’ + BC’D
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Digital Logic Design Combinational Logic
Example (continued) From previous slide -
f’(A,B,C,D) = A’B + A’BD + A’B + BD + AB’C’D’ + A’BC’ + BC’D A’BD + BD = BD
simplification (#10)
A’B + A’B = A’B
idempotent (#3)
f’(A,B,C,D) = A’B + BD + AB’C’D’ + A’BC’ + BC’D A’B + A’BC’ = A’B
simplification (#10)
BD + BC’D = BD
simplification (#10)
f’(A,B,C,D) = A’B + BD + AB’C’D’ This is the simplified Boolean expression for f’.
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Even more definitions (Sec. 4.1.6)
Digital Logic Design Combinational Logic
Standard Representations of Logic Functions - terminology • Product term – a single literal or a logical product (AND) of two or more literals. • Sum-of-products expression – a logical sum of product terms. (SOP) • Sum term – a single literal or a logical sum of two or more literals. • Product-of-sums expression – a logical product of sum terms. (POS) • Normal term – a product or sum term in which no variable appears more than once. Non-normal terms can always be simplified to normal terms using Boolean algebra. • Minterm (n variables) – a normal product term with n literals. There are 2^n such product terms. • Maxterm (n variables) – a normal sum term with n literals. There are 2^n such sum terms.
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Combinational Analysis
Digital Logic Design Combinational Logic
How can we analyze the operation of a particular circuit? We might use (exhaustive) input test vectors and observe the outputs -
Tedious! But might be good for automated testing. - could construct an automated test apparatus to generate the inputs and check the corresponding outputs 2003
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Signal Expressions
Digital Logic Design Combinational Logic
Let’s use Boolean algebra instead to determine a logical equation
Assign each signal line a logic expression
This is a multilevel (3-level) circuit (the inverters at the input don’t count)
• “Multiply” out: F = ((X + Y′) ⋅ Z) + (X′ ⋅ Y ⋅ Z′) = (X ⋅ Z) + (Y′ ⋅ Z) + (X′ ⋅ Y ⋅ Z′)
Å A sum of products representation
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New circuit, but same function
Digital Logic Design Combinational Logic
This is a two-level AND-OR circuit
This is the same circuit as before, realized from the sum of products form of the Boolean equation – it looks different now but implements the same logical relationship!
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“Add out” the logic function
Digital Logic Design Combinational Logic
See Boolean Theorem 8D in the previous table (or T8’ in the text) – this is the dual of distributivity (logical addition distributes over logical multiplication)
• Circuit:
This is a two-level OR-AND circuit 25
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Shortcut: Symbol Substitution
Digital Logic Design Combinational Logic
Consider a new circuit using NAND and NOR gates Use DeMorgan symbols to produce a new equivalent circuit – the “bubbles” represent complementation – then simplify
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Different circuit, same function
Digital Logic Design Combinational Logic
Simplification produces an equivalent circuit – additional manipulation would produce others (SOP and POS forms, for example)
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Another Example
Digital Logic Design Combinational Logic
Conclusion: there is more than one way to map an expression to gates 2003
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Digital Logic Design Combinational Logic
Logic Functions: Rationale for Simplification
Logic Minimization: reduce complexity of the gate level implementation • reduce number of literals (gate inputs) • reduce number of gates • reduce number of levels of gates
• fewer inputs implies faster gates in some technologies • fan-ins (number of gate inputs) are limited in some technologies • fewer levels of gates implies reduced signal propagation delays • minimum delay configuration typically requires more gates (fewer levels) • number of gates (or gate packages) influences manufacturing costs
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Digital Logic Design Combinational Logic
Three Alternative Gate Realizations A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Z 0 1 0 1 0 1 1 0
0 1 0 1 0 1 A
B
C
Two-Level Realization (inverters don't count)
0 Z1
0 Z2
0
Multi-Level Realization Advantage: Reduced Gate Fan-ins Complex Gate: XOR Advantage: Fewest Gates
Z3
TTL Package Counts: Z1 - three packages (1x 6-inverters, 1x 3-input AND, 1x 3-input OR) Z2 - three packages (1x 6-inverters, 1x 2-input AND, 1x 2-input OR) Z3 - two packages (1x 2-input AND, 1x 2-input XOR) This simple example doesn’t really show the true story! 2003
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Truth table vs. minterms & maxterms
Digital Logic Design Combinational Logic
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Gate Logic: 2-Level Canonical Forms
Digital Logic Design Combinational Logic
¾Truth table is the unique signature of a Boolean function ¾Many alternative expressions (and gate realizations) may have the same truth table ¾Canonical form: standard form for a Boolean expression provides a unique algebraic signature (SOP or POS)
Sum of Products Form also known as disjunctive normal form, or minterm expansion A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
F 0 0 0 1 1 1 1 1
F 1 1 1 0 0 0 0 0
011 100 101 110 111 F = A' B C + A B' C' + A B' C + A B C' + A B C
F' = A' B' C' + A' B' C + A' B C' 2003
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Gate Logic: Two Level Canonical Forms Sum of Products A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Minterms A B C = m0 A B C = m1 A B C = m2 A B C = m3 A B C = m4 A B C = m5 A B C = m6 A B C = m7
Shorthand Notation for Minterms of 3 Variables
Digital Logic Design Combinational Logic
product term / minterm: ANDed product of literals in which each variable appears exactly once, in true or complemented form (but not both!) F in canonical form: F(A,B,C) = Σm(3,4,5,6,7) = m3 + m4 + m5 + m6 + m7 = A' B C + A B' C' + A B' C + A B C' + A B C canonical form/minimal form F = A B' (C + C') + A' B C + A B (C' + C) = A B' + A' B C + A B = A (B' + B) + A' B C
B F
C A
= A + A' B C =A + BC
2-Level AND/OR Realization
F’ = (A + B C)' = A' (B' + C') = A' B' + A' C' 33
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Gate Logic: 2 Level Canonical Forms
Digital Logic Design Combinational Logic
Product of Sums / Conjunctive Normal Form / Maxterm Expansion A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Maxterms A + B + C = M0 A + B + C = M1 A + B + C = M2 A + B + C = M3 A + B + C = M4 A + B + C = M5 A + B + C = M6 A + B + C = M7
Maxterm: ORed sum of literals in which each variable appears exactly once in either true or complemented form, but not both! Maxterm form: Find truth table rows where F is 0 0 in input column implies true literal 1 in input column implies complemented literal
Maxterm Shorthand Notation for a Function of Three Variables F(A,B,C) = ΠM(0,1,2) = (A + B + C) (A + B + C') (A + B' + C) F’(A,B,C) = ΠM(3,4,5,6,7) = (A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C')
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Gate Logic: Two Level Canonical Forms
Digital Logic Design Combinational Logic
Sum of Products, Product of Sums, and DeMorgan's Law F' = A' B' C' + A' B' C + A' B C' Apply DeMorgan's Law to obtain F: (F')' = (A' B' C' + A' B' C + A' B C')' F = (A + B + C) (A + B + C') (A + B' + C)
F' = (A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C') Apply DeMorgan's Law to obtain F: (F')' = {(A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C')}' F = A' B C + A B' C' + A B' C + A B C' + A B C
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Gate Logic: Two-Level Canonical Forms
Digital Logic Design Combinational Logic
Four Alternative Implementations of F: A
B
Canonical Sum of Products F1
C
Minimized Sum of Products F2
Canonical Products of Sums F3
Minimized Products of Sums
F4
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Gate Logic: Two-Level Canonical Forms Mapping Between Forms 1.
Digital Logic Design Combinational Logic
Minterm to Maxterm conversion: rewrite minterm shorthand using maxterm shorthand replace minterm indices with the indices not already used E.g., F(A,B,C) = Σm(3,4,5,6,7) = ΠM(0,1,2)
2.
Maxterm to Minterm conversion: rewrite maxterm shorthand using minterm shorthand replace maxterm indices with the indices not already used E.g., F(A,B,C) = ΠM(0,1,2) = Σm(3,4,5,6,7)
3.
Minterm expansion of F to Minterm expansion of F': in minterm shorthand form, list the indices not already used in F E.g., F(A,B,C) = Σm(3,4,5,6,7) = ΠM(0,1,2)
4.
F'(A,B,C) = Σm(0,1,2) = ΠM(3,4,5,6,7)
Minterm expansion of F to Maxterm expansion of F': rewrite in Maxterm form, using the same indices as F E.g., F(A,B,C) = Σm(3,4,5,6,7) = ΠM(0,1,2)
F'(A,B,C) = ΠM(3,4,5,6,7) = Σm(0,1,2) 37
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Digital Logic Design
Incompletely Specified Functions Combinational Logic n •n input functions have 2 possible input configurations •for a given function, not all input configurations may be possible •this fact can be exploited during circuit minimization! E.g., Binary Coded Decimal Digit Increment by 1 BCD digits encode the decimal digits 0 - 9 in the bit patterns 00002 - 10012 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
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B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
W 0 0 0 0 0 0 0 1 1 0 X X X X X X
X 0 0 0 1 1 1 1 0 0 0 X X X X X X
Y 0 1 1 0 0 1 1 0 0 0 X X X X X X
Z 1 0 1 0 1 0 1 0 1 0 X X X X X X
Off-set of W On-set of W Don't care (DC) set of W
These input patterns should never be encountered in practice associated output values are "Don't Cares" 38
Incompletely Specified Functions
Digital Logic Design Combinational Logic
Don't Cares and Canonical Forms Canonical Representations of the BCD Increment by 1 Function: Z = m0 + m2 + m4 + m6 + m8 + d10 + d11 + d12 + d13 + d14 + d15 Z = Σm(0, 2, 4, 6, 8) + d(10, 11, 12 ,13, 14, 15)
Z = M1 • M3 • M5 • M7 • M9 • D10 • D11 • D12 • D13 • D14 • D15 Z= ΠM(1, 3, 5, 7, 9) • D(10, 11, 12, 13, 14 ,15)
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Module 2: Combinational Logic - Analysis Wakerly: Chapter 4 (part 1) Digital Logic Design: ECEN 3233 Dr. Keith A. Teague Spring 2003 Read Chapter 4, through Sec. 4.2 1
2003
Digital Logic Design Combinational Logic
Outline Amplification on the Concepts of Module 1: • Multiple Design Representations Truth Tables Gate descriptions •Logic Functions and Switches Not, AND, OR, NAND, NOR, XOR, XNOR • Gate Logic Laws and Theorems of Boolean Algebra Two Level Canonical Forms
2003
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Boolean Algebra
Digital Logic Design Combinational Logic
• Sometimes called “switching algebra” – Deals with Boolean values: 0,1
• Positive-logic convention – Analog voltages LOW, HIGH Æ 0,1 – Negative logic is seldom used
• Signal values are denoted by variables – X, Y, Z, FRED, ERROR_L, etc. – These should usually be descriptive (like variables in a program), but for our uses it’s easier to keep them short!
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A Boolean Algebra
Digital Logic Design Combinational Logic
Algebraic structure consisting of: set of elements B binary operations {+, •} unary operation {'} such that the following axioms hold: 1.
The set B contains at least two elements, a, b, such that a is not equal to b
2. Closure: for every a,b in the set B, (i) a + b is in B (ii) a • b is in B 3. Commutative Laws: for every a,b in B, (i) a + b = b + a (ii) a • b = b • a 4. Identities: 0, 1 in B (i) a + 0 = a (ii) a • 1 = a 2003
5. Distributive Laws: (i) a + (b • c) = (a + b) • (a + c) (ii) a • (b + c) = a • b + a • c 6. Complement: (i) a + a' = 1 (ii) a • a' = 0 4
Digital Logic Design
Boolean Algebra Combinational Logic B = {0,1}, + = OR, • = AND, ' = NOT is a Boolean Algebra Must verify that the axioms hold: E.g., Commutative Law: 0 + 1 = 1 + 0? 0 • 1 = 1 • 0? 1=1 0=0 Theorem: any Boolean function that can be expressed as a truth table can be written as an expression in Boolean Algebra using ', +, • Description If X = 0 then X ' = 1 If X = 1 then X ' = 0
Description Z = 1 if X and Y are both 1
Gates X
Truth Table X
X Y
Z
Description Z = 1 if X or Y (or both) are 1
X 0 1
X 1 0
NOT
Truth Table X Y Z 0 0 0 0 1 0 1 0 0 1 1 1
AND
Truth T able X Y
Z
X 0 0 1 1
Y 0 1 0 1
Z 0 1 1 1
OR
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More definitions
Digital Logic Design Combinational Logic
• Literal: a variable or its complement – X, X′, FRED′, CS_L
• Expression: literals combined by AND, OR, parentheses, complementation – – – –
X+Y P⋅Q⋅R A+B⋅C ((FRED ⋅ Z′) + CS_L ⋅ A ⋅ B′ ⋅ C + Q5) ⋅ RESET′
• Equation: Variable = expression – P = ((FRED ⋅ Z′) + CS_L ⋅ A ⋅ B′ ⋅ C + Q5) ⋅ RESET′
• Complete: The set of operators AND, OR and NOT is called complete since any Boolean function can be represented using only these operators. Other operators, or sets of operators, are also complete. 2003
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Laws of Boolean Algebra
Digital Logic Design Combinational Logic
Duality: a dual of a Boolean expression is derived by replacing AND operations by ORs, OR operations by ANDs, constant 0s by 1s, and 1s by 0s (literals are left unchanged). Any statement that is true for an expression is also true for its dual! Useful Laws/Theorems of Boolean Algebra: Operations with 0 and 1: 1D. X • 1 = X 1. X + 0 = X 2D. X • 0 = 0 2. X + 1 = 1 Idempotent Law: 3. X + X = X
3D. X • X = X
Involution Law: 4. (X')' = X Laws of Complementarity: 5. X + X' = 1
5D. X • X' = 0
Commutative Law: 6. X + Y = Y + X
6D. X • Y = Y • X
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Laws of Boolean Algebra (cont) Associative Laws: 7. (X + Y) + Z = X + (Y + Z) =X+Y+Z Distributive Laws: 8. X • (Y+ Z) = (X • Y) + (X • Z)
Digital Logic Design Combinational Logic
7D. (X • Y) • Z = X • (Y • Z) =X•Y•Z 8D. X + (Y• Z) = (X + Y) • (X + Z)
Simplification Theorems (combining, covering): 9. X • Y + X • Y' = X 9D. (X + Y) • (X + Y') = X 10. X + X • Y = X 10D. X • (X + Y) = X 11. (X + Y') • Y = X • Y 11D. (X • Y') + Y = X + Y DeMorgan's Law: 12. (X + Y + Z + ...)' = X' • Y' • Z' • ... 12D. (X • Y • Z • ...) ' = X' + Y' + Z' + ... 13. {F(X1,X2,...,Xn,0,1,+,•)}' = {F(X1',X2',...,Xn',1,0,•,+)} Duality: 14. (X + Y + Z + ...) D = X • Y • Z • ...
14D. (X •FY • Z • ...)D = X + Y + Z + ...
15. {F(X1,X2,...,Xn,0,1,+,•)}D = {F(X1,X2,...,Xn,1,0,•,+)} Theorems for Multiplying and Factoring: 16. (X + Y) • (X' + Z) = X • Z + X' • Y 16D. X • Y + X' • Z = (X + Z) • (X' + Y) Consensus Theorem: 17. (X • Y) + (Y • Z) + (X' • Z) = X • Y + X' • Z 2003
17D. (X + Y) • (Y + Z) • (X' + Z) = (X + Y) • (X' + Z) 8
Digital Logic Design Combinational Logic
Laws of Boolean Algebra Proving theorems via axioms of Boolean Algebra: E.g., prove the theorem: X • Y + X • Y' = X distributive law (8)
X • Y + X •Y' = X • (Y + Y')
complementary law (5)
X • (Y + Y')
= X • (1)
identity (1D)
X • (1)
=X
E.g., prove the theorem: X + X • Y
= X
identity (1D)
X + X•Y
= X•1 + X•Y
distributive law (8)
X • 1 + X • Y = X • (1 + Y)
identity (2)
X • (1 + Y)
= X • (1)
identity (1)
X • (1)
= X
Parentheses and operator precedence are important - parentheses are used to group operations - multiplication (AND) has precedence over addition (OR) 9
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Digital Logic Design Combinational Logic
NAND, NOR, XOR, XNOR 16 functions of two variables: X Y 0 0 0 1 1 0 1 1
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
X• Y
X
NAND
NOR
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Y
X+Y
Y
Description Z = 1 if X is 0 or Y is 0
Description Z = 1 if both X and Y are 0
X, X', Y, Y', X•Y, X+Y, 0, 1 only half of the possible functions 1
X
Gates X Y
Truth T able X Y Z 0 0 1 0 1 1 1 0 1 1 1 0
Z
Gates X Y
Truth T able Z
X 0 0 1 1
Y 0 1 0 1
Z 1 0 0 0
10
Digital Logic Design Combinational Logic
NAND, NOR
NAND, NOR gates far outnumber AND, OR in typical designs - easier to construct in the underlying transistor technologies Any Boolean expression can be implemented by NAND, NOR, NOT gates In fact, NOT is superfluous (NOT = NAND or NOR with both inputs tied together) X 0
Y 0
X NOR Y 1
X 0
Y X NAND Y 0 1
1
1
0
1
1
0
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Digital Logic Design Combinational Logic
NAND, NOR DeMorgan's Law (X + Y)' = X' • Y' NOR is equivalent to AND with inputs complemented
(X • Y)' = X' + Y' NAND is equivalent to OR with inputs complemented
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X 0 0 1 1
Y 0 1 0 1
X 1 1 0 0
Y 1 0 1 0
X 0 0 1 1
Y 0 1 0 1
X 1 1 0 0
Y 1 0 1 0
X +Y 1 0 0 0
X•Y 1 0 0 0
X•Y X +Y 1 1 1 1 1 1 0 0
12
DeMorgan Symbol Equivalence
Digital Logic Design Combinational Logic
NAND Equivalence
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DeMorgan Symbol Equivalence
Digital Logic Design Combinational Logic
Likewise for OR -
NOR Equivalence
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Digital Logic Design Combinational Logic
DeMorgan Symbols / Logical Equivalence
It is sometimes useful to make substitutions using these identities.
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Digital Logic Design Combinational Logic
XOR, XNOR
XOR: X or Y but not both ("inequality", "difference") XNOR: X and Y are the same ("equality", "coincidence") Description Z = 1 if X has a different value than Y
Description Z = 1 if X has the same value as Y
Gates
Gates
X
Z
Y Truth T able
Z
Y Truth T able
X 0 0 1 1
Y 0 1 0 1
(a) XOR
X ⊕ Y = X Y' + X' Y 2003
X
Z 0 1 1 0
X 0 0 1 1
Y 0 1 0 1
Z 1 0 0 1
(b) XNOR
X ⊕ Y = X Y + X' Y' 16
Digital Logic Design Combinational Logic
DeMorgan’s Law
DeMorgan's DeMorgan'sLaw Lawcan canbe beused usedto toconvert convertAND/OR AND/ORexpressions expressions to toOR/AND OR/ANDexpressions expressions Example: Z = A' B' C + A' B C + A B' C + A B C' Z' = (A + B + C') • (A + B' + C') • (A' + B + C') • (A' + B' + C)
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Digital Logic Design Combinational Logic
Example f(A,B,C,D) = AB’C + (A’ + B + D) (ABD’ + B’)
Find f’
f’(A,B,C,D) = [ AB’C + (A’ + B + D) (ABD’ + B’) ]’ Use DeMorgan’s Law - then simplify = ( AB’C )’ [ ( A’ + B + D )’ + ( ABD’ + B’ )’ ] = (A’ + B + C’ ) [ AB’D’ + (( ABD’ )’ B) ] = (A’ + B + C’ ) [ AB’D’ + (A’ + B’ + D ) B ] = (A’ + B + C’ ) [ AB’D’ + A’B + B’B + BD ]
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Digital Logic Design Combinational Logic
Example (continued) From previous slide -
f’(A,B,C,D) = (A’ + B + C’ ) [ AB’D’ + A’B + B’B + BD ]
= A’AB’D’ + A’A’B + A’BD + BAB’D’ + BA’B + BBD + C’AB’D’ + C’A’B + C’BD
= A’B + A’BD + A’B + BD + AB’C’D’ + A’BC’ + BC’D
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Digital Logic Design Combinational Logic
Example (continued) From previous slide -
f’(A,B,C,D) = A’B + A’BD + A’B + BD + AB’C’D’ + A’BC’ + BC’D A’BD + BD = BD
simplification (#10)
A’B + A’B = A’B
idempotent (#3)
f’(A,B,C,D) = A’B + BD + AB’C’D’ + A’BC’ + BC’D A’B + A’BC’ = A’B
simplification (#10)
BD + BC’D = BD
simplification (#10)
f’(A,B,C,D) = A’B + BD + AB’C’D’ This is the simplified Boolean expression for f’.
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Even more definitions (Sec. 4.1.6)
Digital Logic Design Combinational Logic
Standard Representations of Logic Functions - terminology • Product term – a single literal or a logical product (AND) of two or more literals. • Sum-of-products expression – a logical sum of product terms. (SOP) • Sum term – a single literal or a logical sum of two or more literals. • Product-of-sums expression – a logical product of sum terms. (POS) • Normal term – a product or sum term in which no variable appears more than once. Non-normal terms can always be simplified to normal terms using Boolean algebra. • Minterm (n variables) – a normal product term with n literals. There are 2^n such product terms. • Maxterm (n variables) – a normal sum term with n literals. There are 2^n such sum terms.
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Combinational Analysis
Digital Logic Design Combinational Logic
How can we analyze the operation of a particular circuit? We might use (exhaustive) input test vectors and observe the outputs -
Tedious! But might be good for automated testing. - could construct an automated test apparatus to generate the inputs and check the corresponding outputs 2003
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Signal Expressions
Digital Logic Design Combinational Logic
Let’s use Boolean algebra instead to determine a logical equation
Assign each signal line a logic expression
This is a multilevel (3-level) circuit (the inverters at the input don’t count)
• “Multiply” out: F = ((X + Y′) ⋅ Z) + (X′ ⋅ Y ⋅ Z′) = (X ⋅ Z) + (Y′ ⋅ Z) + (X′ ⋅ Y ⋅ Z′)
Å A sum of products representation
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New circuit, but same function
Digital Logic Design Combinational Logic
This is a two-level AND-OR circuit
This is the same circuit as before, realized from the sum of products form of the Boolean equation – it looks different now but implements the same logical relationship!
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“Add out” the logic function
Digital Logic Design Combinational Logic
See Boolean Theorem 8D in the previous table (or T8’ in the text) – this is the dual of distributivity (logical addition distributes over logical multiplication)
• Circuit:
This is a two-level OR-AND circuit 25
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Shortcut: Symbol Substitution
Digital Logic Design Combinational Logic
Consider a new circuit using NAND and NOR gates Use DeMorgan symbols to produce a new equivalent circuit – the “bubbles” represent complementation – then simplify
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Different circuit, same function
Digital Logic Design Combinational Logic
Simplification produces an equivalent circuit – additional manipulation would produce others (SOP and POS forms, for example)
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Another Example
Digital Logic Design Combinational Logic
Conclusion: there is more than one way to map an expression to gates 2003
28
Digital Logic Design Combinational Logic
Logic Functions: Rationale for Simplification
Logic Minimization: reduce complexity of the gate level implementation • reduce number of literals (gate inputs) • reduce number of gates • reduce number of levels of gates
• fewer inputs implies faster gates in some technologies • fan-ins (number of gate inputs) are limited in some technologies • fewer levels of gates implies reduced signal propagation delays • minimum delay configuration typically requires more gates (fewer levels) • number of gates (or gate packages) influences manufacturing costs
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Digital Logic Design Combinational Logic
Three Alternative Gate Realizations A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Z 0 1 0 1 0 1 1 0
0 1 0 1 0 1 A
B
C
Two-Level Realization (inverters don't count)
0 Z1
0 Z2
0
Multi-Level Realization Advantage: Reduced Gate Fan-ins Complex Gate: XOR Advantage: Fewest Gates
Z3
TTL Package Counts: Z1 - three packages (1x 6-inverters, 1x 3-input AND, 1x 3-input OR) Z2 - three packages (1x 6-inverters, 1x 2-input AND, 1x 2-input OR) Z3 - two packages (1x 2-input AND, 1x 2-input XOR) This simple example doesn’t really show the true story! 2003
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Truth table vs. minterms & maxterms
Digital Logic Design Combinational Logic
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Gate Logic: 2-Level Canonical Forms
Digital Logic Design Combinational Logic
¾Truth table is the unique signature of a Boolean function ¾Many alternative expressions (and gate realizations) may have the same truth table ¾Canonical form: standard form for a Boolean expression provides a unique algebraic signature (SOP or POS)
Sum of Products Form also known as disjunctive normal form, or minterm expansion A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
F 0 0 0 1 1 1 1 1
F 1 1 1 0 0 0 0 0
011 100 101 110 111 F = A' B C + A B' C' + A B' C + A B C' + A B C
F' = A' B' C' + A' B' C + A' B C' 2003
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Gate Logic: Two Level Canonical Forms Sum of Products A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Minterms A B C = m0 A B C = m1 A B C = m2 A B C = m3 A B C = m4 A B C = m5 A B C = m6 A B C = m7
Shorthand Notation for Minterms of 3 Variables
Digital Logic Design Combinational Logic
product term / minterm: ANDed product of literals in which each variable appears exactly once, in true or complemented form (but not both!) F in canonical form: F(A,B,C) = Σm(3,4,5,6,7) = m3 + m4 + m5 + m6 + m7 = A' B C + A B' C' + A B' C + A B C' + A B C canonical form/minimal form F = A B' (C + C') + A' B C + A B (C' + C) = A B' + A' B C + A B = A (B' + B) + A' B C
B F
C A
= A + A' B C =A + BC
2-Level AND/OR Realization
F’ = (A + B C)' = A' (B' + C') = A' B' + A' C' 33
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Gate Logic: 2 Level Canonical Forms
Digital Logic Design Combinational Logic
Product of Sums / Conjunctive Normal Form / Maxterm Expansion A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
Maxterms A + B + C = M0 A + B + C = M1 A + B + C = M2 A + B + C = M3 A + B + C = M4 A + B + C = M5 A + B + C = M6 A + B + C = M7
Maxterm: ORed sum of literals in which each variable appears exactly once in either true or complemented form, but not both! Maxterm form: Find truth table rows where F is 0 0 in input column implies true literal 1 in input column implies complemented literal
Maxterm Shorthand Notation for a Function of Three Variables F(A,B,C) = ΠM(0,1,2) = (A + B + C) (A + B + C') (A + B' + C) F’(A,B,C) = ΠM(3,4,5,6,7) = (A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C')
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Gate Logic: Two Level Canonical Forms
Digital Logic Design Combinational Logic
Sum of Products, Product of Sums, and DeMorgan's Law F' = A' B' C' + A' B' C + A' B C' Apply DeMorgan's Law to obtain F: (F')' = (A' B' C' + A' B' C + A' B C')' F = (A + B + C) (A + B + C') (A + B' + C)
F' = (A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C') Apply DeMorgan's Law to obtain F: (F')' = {(A + B' + C') (A' + B + C) (A' + B + C') (A' + B' + C) (A' + B' + C')}' F = A' B C + A B' C' + A B' C + A B C' + A B C
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Gate Logic: Two-Level Canonical Forms
Digital Logic Design Combinational Logic
Four Alternative Implementations of F: A
B
Canonical Sum of Products F1
C
Minimized Sum of Products F2
Canonical Products of Sums F3
Minimized Products of Sums
F4
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Gate Logic: Two-Level Canonical Forms Mapping Between Forms 1.
Digital Logic Design Combinational Logic
Minterm to Maxterm conversion: rewrite minterm shorthand using maxterm shorthand replace minterm indices with the indices not already used E.g., F(A,B,C) = Σm(3,4,5,6,7) = ΠM(0,1,2)
2.
Maxterm to Minterm conversion: rewrite maxterm shorthand using minterm shorthand replace maxterm indices with the indices not already used E.g., F(A,B,C) = ΠM(0,1,2) = Σm(3,4,5,6,7)
3.
Minterm expansion of F to Minterm expansion of F': in minterm shorthand form, list the indices not already used in F E.g., F(A,B,C) = Σm(3,4,5,6,7) = ΠM(0,1,2)
4.
F'(A,B,C) = Σm(0,1,2) = ΠM(3,4,5,6,7)
Minterm expansion of F to Maxterm expansion of F': rewrite in Maxterm form, using the same indices as F E.g., F(A,B,C) = Σm(3,4,5,6,7) = ΠM(0,1,2)
F'(A,B,C) = ΠM(3,4,5,6,7) = Σm(0,1,2) 37
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Digital Logic Design
Incompletely Specified Functions Combinational Logic n •n input functions have 2 possible input configurations •for a given function, not all input configurations may be possible •this fact can be exploited during circuit minimization! E.g., Binary Coded Decimal Digit Increment by 1 BCD digits encode the decimal digits 0 - 9 in the bit patterns 00002 - 10012 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
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B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
W 0 0 0 0 0 0 0 1 1 0 X X X X X X
X 0 0 0 1 1 1 1 0 0 0 X X X X X X
Y 0 1 1 0 0 1 1 0 0 0 X X X X X X
Z 1 0 1 0 1 0 1 0 1 0 X X X X X X
Off-set of W On-set of W Don't care (DC) set of W
These input patterns should never be encountered in practice associated output values are "Don't Cares" 38
Incompletely Specified Functions
Digital Logic Design Combinational Logic
Don't Cares and Canonical Forms Canonical Representations of the BCD Increment by 1 Function: Z = m0 + m2 + m4 + m6 + m8 + d10 + d11 + d12 + d13 + d14 + d15 Z = Σm(0, 2, 4, 6, 8) + d(10, 11, 12 ,13, 14, 15)
Z = M1 • M3 • M5 • M7 • M9 • D10 • D11 • D12 • D13 • D14 • D15 Z= ΠM(1, 3, 5, 7, 9) • D(10, 11, 12, 13, 14 ,15)
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