D Converter Testing on
1
Alternate Test Methodology for High Speed A/D Converter Testing on Low Cost Tester Shalabh Goyal, Abhijit Chatterjee Georgia Institute of Technology Email: [email protected]
Abstract—This paper proposes a test methodology for dynamic specification testing of high-speed A/D converters on a low cost tester using alternate test approach. Dynamic specification testing of high-speed A/D converters requires high-speed ATE, the cost of which can be prohibitively high. In the proposed approach regression-based mapping functions are generated using specification data of the device from bench testing. During production testing, dynamic specifications of the device are estimated on a low cost ATE using alternate test set-up and the predeveloped mapping functions. As opposed to the conventional method of dynamic specification testing of A/D converters, proposed approach does not require a spectrally pure sinusoidal input signal and estimates device SNR in presence of sampling clock jitter. The simulation results of the proposed approach achieved the specification estimation error of < 4%.
A
I . INTRODUCTION
s the need for speed and accuracy in data conversion systems is increasing, high speed-high resolution A/D converters are designed. Testing these high speed-high resolution devices require even faster and more accurate tester circuitry. A/D converters are tested for dynamic specifications because of there importance in high-speed applications such as digital communications, ultrasound imaging, instrumentation, and IF digitization. Dynamic specification testing of high-speed A/D converters requires fast and precise tester circuitry. The cost of the testers that could perform these high-speed tests (dynamic specification tests) is very high and it drives the IC cost higher. A. Conventional Dynamic Test Methodology In the conventional method for measuring the dynamic specifications of an A/D converter, a high-speed sinusoidal signal (close to the nyquist frequency) is applied to the input of the A/D converter. The A/D converter is clocked with a low jitter clock and frequency spectrum of the digital output of the A/D converter is used to measure various dynamic specifications of the A/D converter. The input frequency is chosen such that the coherent sampling condition is met. This is important in order to prevent power leakage into adjacent frequency bins while constructing frequency spectrum using a finite point FFT.
Alternatively, a suitable windowing technique can be applied to the output, if incoherent sampling is performed, to minimize spectral leakage. B. Issues in High-Speed A/D Converter Testing Testing high-speed A/D converters for dynamic specifications need high-speed and precise tester circuitry. The tester should be able to source a high-frequency input signal to the DUT. Also, as the SNR of the device measured at the output depends on the input signal SNR, the tester should be capable of generating spectrally pure sinusoidal waves. Sampling clock jitter also limits the SNR measurements. EQ1 shows the best SNR performance that can be measured while using a clock with rms jitter ! rms and input frequency equal to
!in 1 SNR (dB) = 20 * log( ) 2"#in! rms
EQ 1
This shows that, for measuring the dynamic performance of a 1Gsps A/D converter, where the input frequency is close to 500MHz, a clock with 1ps rms jitter could measure the SNR close to 50dB. The ideal A/D converter SNR for an n-bit device is given by SNRideal (dB) = 6.02 * n + 1.76 EQ2 It means the SNR for an 8 bit device is close to 50dB. For higher-resolution high-speed A/D converters subpicosecond clock jitter performance is needed. Such clocks, if available, are very costly to be used in production environment. Thus, there is a need to develop a test methodology that can ease the tester resource requirements in production testing of high-speed A/D converters. C. Previous Work In past, various test approaches (built-in and built-off test approaches) have been proposed for dynamic testing of A/D converters. In [1],[2] a low-resolution sinusoidal wave is passed through a bank of filters to generate a spectrally pure sinusoidal wave used for dynamic specification tests. The FFT of the captured response is used to calculate the test specifications. The authors in [3] propose to use sophisticated DSP techniques for testing A/D converters. In their approach, a logic analyzer is used with custom designed software to read the digital data directly form the A/D converter output to perform further processing.
2 However, for high speed devices there arises a need for synchronized low-jitter clocks running at multi-gigahertz frequencies. To determine the instantaneous value of the dynamic specifications, the authors in [4] have proposed to use wavelet transforms to compute the non-idealities. Using the built-in-self-test approach [5], which uses two imprecise sinusoidal waves having spectral dependence to determine the device dynamic performance could result in design and reliability issues at higher frequencies. Most of the above mentioned approaches assume the existence of analog sources that can source high frequency analog signals. This paper presents a novel methodology to ease the tester resource requirements when testing highspeed A/D converters. The paper is organized as follows. Section II gives a brief review of the alternate test strategy. Section III explains the proposed low cost test strategy. Section IV describes the validation of the proposed approach and highlights the results. Section VI concludes the paper. II. ALTERNATE TESTING CONCEPTS Alternate test methodology is based on the concept that, due to process variations, the specifications of a DUT vary in a correlated manner with the measurements made on the DUT in presence of an appropriate input test stimulus. If such a correlation exists between the specifications and the measurement space, a mapping function can be built from the measurement space to the specification space. Once such a mapping function is known, all the DUT specifications can be estimated from the measurements using the mapping functions on the application of a single test stimulus. There is a need though, to generate a specially crafted test stimulus such that maximum correlation between device specifications and measurements is observed. Alternate testing has already been applied to analog and mixed signal devices [7], [8], [9] with the goal of test time reduction.
Fig 1. Alternate Testing Concept III. PROPOSED LOW COST TEST METHODOLOGY In this section the proposed test methodology to measure the dynamic specifications of high speed A/D converters using a low cost tester is illustrated. The proposed test methodology is based on the alternate testing approach. The goal here though is to apply alternate testing methodology to ease the tester resource
requirements rather than achieving test time reduction. In the proposed approach, specification data for initial N devices is obtained from the bench testing using conventional test set-up. Bench testing generally uses high performance equipment to obtain accurate device specifications. These devices are then measured using an alternate test set-up (Fig 2) on a low cost tester. The output of the devices is under-sampled and stored for building the mapping functions. A set of mapping functions or models is then developed using Multivariate Adaptive Regression Splines (MARS) to map the measurements obtained from the alternate test set-up to the specifications obtained from the bench testing data. The following is the equation relating the specifications to the measurements. Si = !i * M EQ 3 where, Si is the ith specification of the device, !i is the model for the ith specification and M is the measurement vector. Thus, a model is developed using the same measurement vector for every specification that needs to be determined.
Fig 2. Single Mixer Alternate Test Set-up Specification testing of subsequent devices requires measurement on the alternate test set-up using a low cost tester. The specifications of the devices are then estimated using the measurements and the corresponding predeveloped models. The flow diagram of the proposed strategy is given in Fig 3. A. Alternate Test Set-up Alternate test set-up requires an on-board mixer (Fig2). A low frequency test stimulus is sourced from the tester and is up-converted using the on-board mixer. The LO frequency is also generated from the tester to avoid synchronization issues (the input signal, A/D clock and the output sampling clock needs to be synchronized). An external source is used to provide high-speed clock to the A/D converter DUT. The external clocking source can be synchronized to the tester using a BNC cable at 10MHz. The output of the high-speed A/D converter is undersampled at a lower frequency Fus, where,
3 Specifications of initial N devices are measured using conventional test set-up
A.1 Up-converting Mixer Modeling The up-converting mixer was modeled in the time domain by a third order polynomial. The conversion gain, LO leakage, noise factor and IIP3 of a commercially available device were used to simulate the mixer. EQ 6 gives the output of the mixer in time-domain.
Measurement data is taken for same set of N devices on alternate test set-up
Model/Mapping Functions are built from measurements to specifications using MARS Subsequent devices are measured on the alternate test set-up and models are used to estimate the specifications Fig 3. Flow Diagram of the Proposed Test Methodology
Fus =
Fs < Fmax n
n =2,4,8….
EQ 4
Fs = A/D sampling frequency Fmax = Maximum Tester Sampling Frequency B. Alternate Test Stimulus Generation A frequency tone close to the nyquist frequency of the A/D converter sampling frequency needs to be generated to excite the worst-case non-linearity in the device. The proposed approach uses an up-conversion mixer to generate such high frequency input tones from a low speed tester. The input to the IF port of the mixer is a sinusoidal signal from the tester. The LO frequency to the mixer is also generated from the low cost tester to avoid synchronization issues. The IF and LO tones are generated* such that the up-converted tone falls at the frequency at which the dynamic specifications of the device needs to be measured. ! IN = ! IF + ! LO EQ 5 where,
! IF and ! LO are the IF and LO frequency tones and ! IN is the frequency at which the dynamic specifications of the device needs to be measured. Thus it is possible to generate an input tone at 2 times the maximum frequency capability of the tester (if ! IF and ! LO are kept equal to ! MAX , where ! MAX is the maximum frequency output of the tester). If the A/D converter nyquist frequency is more than 2 times the maximum tester frequency, a series of mixers can be used to up-convert the output of the first mixer. IV. VALIDATION OF PROPOSED APPROACH A. Simulation Validation The components were modeled and the proposed approach was simulated in MATLAB. The following subsections describe the modeling of the components and simulation of the alternate test set-up.
O(t) = A0*I(t)3 +A1*I(t)2 +A2*I(t) +A3 + N(t) EQ 6 Where, A2 = 10(Conversion Gain)/20 A0 = 4* A2 /3*(IIP3)2 A1 = A3 =0 I(t) = ACin(t)*LO(t) + LOfeed(t) ACin(t) is the low frequency input from the tester LO(t) is the local oscillator sinusoidal signal LOfeed(t) is the LO leakage power N(t) is the output noise which is calculated based on Noise Factor and input noise floor. The following were the specifications of the mixer that was modeled. Conversion Gain: 4.5 dB IIP3: 24 dBm LO Leakage: -23 dB NF: 10.5 dB A.2 A/D Converter Modeling The A/D converter transfer function was modeled by random differential non-linearity* (DNL) characteristics. The sampling frequency of the A/D converter modeled was 1Gsps and resolution was 8 bit. Flash architecture was assumed and the code-widths were randomly varied from the ideal value of 1 LSB to insert non-ideality in the device. A.3 Simulation of the Alternate Test Set-Up The device-under-test (DUT) was chosen to be an 8-bit 1Gsps A/D converter. 100 such devices were simulated to validate the proposed approach. The input frequency for testing the dynamic specifications was chosen to be, close to the Nyquist frequency, at 490.11MHz. The input frequency of the DUT was chosen in order to meet the coherent sampling condition. The output of the low cost tester was an IF tone at ! IF = 240.11MHz and a LO frequency tone at
! LO = 250 MHz. 2nd and 3rd harmonics
from the low cost tester were assumed to be at -60dBc. The IF and LO frequency sinusoidal signals were fed to the mixer. Fig 5 shows the frequency spectrum of the test stimulus that was applied to the A/D converter DUT. The sampling clock in hardware can be generated by an external clocking source that is synchronized with the tester using a BNC cable via 10MHz signal from the tester. The sampling *As opposed to conventional methodology, here a spectrally pure input signal is not required. All that is required is a tone at the nyquist frequency of the A/D converter to excite the high frequency non-linearity effects. **this modeling should not be confused with the static A/D converter modeling. The DNL characteristic of an A/D converter is different at low frequencies. We do not need a DNL model of the A/D converter that varies with frequency because the input frequency is not varied in the proposed test strategy.
4 clock jitter was assumed to be Gaussian distributed with 10ps standard deviation. The frequency spectrum of the input signal to the A/D converter DUT shows the presence of multiple tones. Frequency Spectrum of the Test Stimulus to DUT
B. Hardware Validation The proposed methodology is currently verified in hardware. A 14 bit 40Msps National Semiconductor device is used to validate the methodology. The input was a multitone signal to simulate the mixer effect. The input signal was sourced from a 12bit DAC. The preliminary hardware data shows maximum prediction error in SNR specifications of about 3dB.
20 0 -20 -40
Power dBm
SFDR 1.70dB 0.46dB Second Harmonic 3.29dB 0.70dB Third Harmonic 1.70dB 0.46dB THD 1.56dB 0.44dB Table 2 Results summary for Two Mixer
-60 -80 -100 -120
V. CONCLUSION
-140 -160
0
0.5
1
1.5
2 2.5 3 Frequency in Hz
3.5
4
4.5
5 8
x 10
Fig 4. Frequency Spectrum of the test stimulus to the DUT The output of the A/D converter was under-sampled at a sampling frequency of 250Msps. The under-sampled output of the A/D converter was stored for model building. The conventional specification testing was then done on first 60 simulated A/D converter devices. A set of models, one corresponding to each specification, mapping measurements to the specifications was then built using non-linear regression splines (MARS). The proposed approach was then validated on the rest 40 simulated devices. The device response was measured on the simulated alternate test set-up and the pre-developed models were used to estimate the accurate specifications. The maximum and the average error in estimation of the specifications using the proposed approach are shown in Table1. The average error in prediction is less than 2%. THD was calculated by summing power of first 8 harmonics. Maximum Average Error Error SNR 0.7dBc 0.37dB SFDR 1.6dB 0.70dB Second Harmonic 2.38dB 1.08dB Third Harmonic 1.60dB 0.70dB THD 1.69dB 0.72dB Table 1 Results summary for Single Mixer Similar validation methodology was used for two mixer set-up where the frequencies sourced from the tester were ! IF =145.05MHz and ! LO =100MHz. The output of the first mixer was filtered using a 2nd order band-pass filter and then self-mixed to generate a tone at 490.11MHz. Table 2 shows the result summary for this simulation experiment.
SNR
Maximum Error 0.43dBc
Average Error 0.18dB
This paper describes a novel approach to test high speed A/D converters. The alternate testing methodology is used to ease the tester resource requirements in testing highspeed, high-resolution A/D converters. The main contribution of the proposed approach is that it enables the measurement of true device SNR in presence of sampling clock jitter. Hardware verification is currently going on using a National Semiconductor 14 bit A/D converter. The preliminary results show a maximum 3dB prediction error in SNR measurements. REFERENCES [1] Mielke J.A., “Frequency domain testing of ADCs”, IEEE Design & Test of Computers, vol. 13 , no. 1 , Spring 1996, pp. 64 – 69. [2] McLeod D.A., “Dynamic testing of analogue to digital converters”, International Conference on Analogue to Digital and Digital to Analogue Conversion, 17-19 September 1991, pp. 29 – 35. [3] Yuan Tzu Ting, Li Wei Chao, Wei Chung Chao, “A practical implementation of dynamic testing of an AD converter”, Proceedings of the Fifth Asian Test Symposium, 20-22 November 1996, pp. 238 – 243. [4] Yamaguchi T., Soma M., “Dynamic testing of ADCs using wavelet transforms”, International Test Conference, 1-6 November 1997, pp.379 – 388. [5] Zhongjun Yu, Degang Chen, Geiger R., “Accurate testing of ADC's spectral performance using imprecise sinusoidal excitations”, Proceedings of the 2004 International Symposium on Circuits and Systems,vol. 1,23-26 May 2004, pp. 645-648. [6] Appnote on testing dynamic parameters of high speed A/D conerters http://www.maxim-ic.com/appnotes.cfm/ appnote_number/728 [7] P.N. Variyam et. al. “Prediction of analog performance parameters using fast transient testing”, IEEE Trans. CAD of integrated circuits and systems, March 02, pp. 349-361. [8] P.N. Variyam and Abhijit Chatterjee, “Enhancing test effectiveness for analog circuits using synthesized measurements”, Proc. VLSI Test Symposium, 1998, pp. 132-137. [9] Ganesh Srinivasan, Shalabh Goyal, Abhijit Chatterjee, “Enhancing Alternate Test Performance of Analog Circuits Using Reconfiguration for Testability”, Asian Test Symposium, 2004. [10] J. H. Friedman, “Multivariate Adaptive Regression Splines”, The Annals of Statistics,vol. 19, no.1, 1991, pp. 1141.
Alternate Test Methodology for High Speed A/D Converter Testing on Low Cost Tester Shalabh Goyal, Abhijit Chatterjee Georgia Institute of Technology Email: [email protected]
Abstract—This paper proposes a test methodology for dynamic specification testing of high-speed A/D converters on a low cost tester using alternate test approach. Dynamic specification testing of high-speed A/D converters requires high-speed ATE, the cost of which can be prohibitively high. In the proposed approach regression-based mapping functions are generated using specification data of the device from bench testing. During production testing, dynamic specifications of the device are estimated on a low cost ATE using alternate test set-up and the predeveloped mapping functions. As opposed to the conventional method of dynamic specification testing of A/D converters, proposed approach does not require a spectrally pure sinusoidal input signal and estimates device SNR in presence of sampling clock jitter. The simulation results of the proposed approach achieved the specification estimation error of < 4%.
A
I . INTRODUCTION
s the need for speed and accuracy in data conversion systems is increasing, high speed-high resolution A/D converters are designed. Testing these high speed-high resolution devices require even faster and more accurate tester circuitry. A/D converters are tested for dynamic specifications because of there importance in high-speed applications such as digital communications, ultrasound imaging, instrumentation, and IF digitization. Dynamic specification testing of high-speed A/D converters requires fast and precise tester circuitry. The cost of the testers that could perform these high-speed tests (dynamic specification tests) is very high and it drives the IC cost higher. A. Conventional Dynamic Test Methodology In the conventional method for measuring the dynamic specifications of an A/D converter, a high-speed sinusoidal signal (close to the nyquist frequency) is applied to the input of the A/D converter. The A/D converter is clocked with a low jitter clock and frequency spectrum of the digital output of the A/D converter is used to measure various dynamic specifications of the A/D converter. The input frequency is chosen such that the coherent sampling condition is met. This is important in order to prevent power leakage into adjacent frequency bins while constructing frequency spectrum using a finite point FFT.
Alternatively, a suitable windowing technique can be applied to the output, if incoherent sampling is performed, to minimize spectral leakage. B. Issues in High-Speed A/D Converter Testing Testing high-speed A/D converters for dynamic specifications need high-speed and precise tester circuitry. The tester should be able to source a high-frequency input signal to the DUT. Also, as the SNR of the device measured at the output depends on the input signal SNR, the tester should be capable of generating spectrally pure sinusoidal waves. Sampling clock jitter also limits the SNR measurements. EQ1 shows the best SNR performance that can be measured while using a clock with rms jitter ! rms and input frequency equal to
!in 1 SNR (dB) = 20 * log( ) 2"#in! rms
EQ 1
This shows that, for measuring the dynamic performance of a 1Gsps A/D converter, where the input frequency is close to 500MHz, a clock with 1ps rms jitter could measure the SNR close to 50dB. The ideal A/D converter SNR for an n-bit device is given by SNRideal (dB) = 6.02 * n + 1.76 EQ2 It means the SNR for an 8 bit device is close to 50dB. For higher-resolution high-speed A/D converters subpicosecond clock jitter performance is needed. Such clocks, if available, are very costly to be used in production environment. Thus, there is a need to develop a test methodology that can ease the tester resource requirements in production testing of high-speed A/D converters. C. Previous Work In past, various test approaches (built-in and built-off test approaches) have been proposed for dynamic testing of A/D converters. In [1],[2] a low-resolution sinusoidal wave is passed through a bank of filters to generate a spectrally pure sinusoidal wave used for dynamic specification tests. The FFT of the captured response is used to calculate the test specifications. The authors in [3] propose to use sophisticated DSP techniques for testing A/D converters. In their approach, a logic analyzer is used with custom designed software to read the digital data directly form the A/D converter output to perform further processing.
2 However, for high speed devices there arises a need for synchronized low-jitter clocks running at multi-gigahertz frequencies. To determine the instantaneous value of the dynamic specifications, the authors in [4] have proposed to use wavelet transforms to compute the non-idealities. Using the built-in-self-test approach [5], which uses two imprecise sinusoidal waves having spectral dependence to determine the device dynamic performance could result in design and reliability issues at higher frequencies. Most of the above mentioned approaches assume the existence of analog sources that can source high frequency analog signals. This paper presents a novel methodology to ease the tester resource requirements when testing highspeed A/D converters. The paper is organized as follows. Section II gives a brief review of the alternate test strategy. Section III explains the proposed low cost test strategy. Section IV describes the validation of the proposed approach and highlights the results. Section VI concludes the paper. II. ALTERNATE TESTING CONCEPTS Alternate test methodology is based on the concept that, due to process variations, the specifications of a DUT vary in a correlated manner with the measurements made on the DUT in presence of an appropriate input test stimulus. If such a correlation exists between the specifications and the measurement space, a mapping function can be built from the measurement space to the specification space. Once such a mapping function is known, all the DUT specifications can be estimated from the measurements using the mapping functions on the application of a single test stimulus. There is a need though, to generate a specially crafted test stimulus such that maximum correlation between device specifications and measurements is observed. Alternate testing has already been applied to analog and mixed signal devices [7], [8], [9] with the goal of test time reduction.
Fig 1. Alternate Testing Concept III. PROPOSED LOW COST TEST METHODOLOGY In this section the proposed test methodology to measure the dynamic specifications of high speed A/D converters using a low cost tester is illustrated. The proposed test methodology is based on the alternate testing approach. The goal here though is to apply alternate testing methodology to ease the tester resource
requirements rather than achieving test time reduction. In the proposed approach, specification data for initial N devices is obtained from the bench testing using conventional test set-up. Bench testing generally uses high performance equipment to obtain accurate device specifications. These devices are then measured using an alternate test set-up (Fig 2) on a low cost tester. The output of the devices is under-sampled and stored for building the mapping functions. A set of mapping functions or models is then developed using Multivariate Adaptive Regression Splines (MARS) to map the measurements obtained from the alternate test set-up to the specifications obtained from the bench testing data. The following is the equation relating the specifications to the measurements. Si = !i * M EQ 3 where, Si is the ith specification of the device, !i is the model for the ith specification and M is the measurement vector. Thus, a model is developed using the same measurement vector for every specification that needs to be determined.
Fig 2. Single Mixer Alternate Test Set-up Specification testing of subsequent devices requires measurement on the alternate test set-up using a low cost tester. The specifications of the devices are then estimated using the measurements and the corresponding predeveloped models. The flow diagram of the proposed strategy is given in Fig 3. A. Alternate Test Set-up Alternate test set-up requires an on-board mixer (Fig2). A low frequency test stimulus is sourced from the tester and is up-converted using the on-board mixer. The LO frequency is also generated from the tester to avoid synchronization issues (the input signal, A/D clock and the output sampling clock needs to be synchronized). An external source is used to provide high-speed clock to the A/D converter DUT. The external clocking source can be synchronized to the tester using a BNC cable at 10MHz. The output of the high-speed A/D converter is undersampled at a lower frequency Fus, where,
3 Specifications of initial N devices are measured using conventional test set-up
A.1 Up-converting Mixer Modeling The up-converting mixer was modeled in the time domain by a third order polynomial. The conversion gain, LO leakage, noise factor and IIP3 of a commercially available device were used to simulate the mixer. EQ 6 gives the output of the mixer in time-domain.
Measurement data is taken for same set of N devices on alternate test set-up
Model/Mapping Functions are built from measurements to specifications using MARS Subsequent devices are measured on the alternate test set-up and models are used to estimate the specifications Fig 3. Flow Diagram of the Proposed Test Methodology
Fus =
Fs < Fmax n
n =2,4,8….
EQ 4
Fs = A/D sampling frequency Fmax = Maximum Tester Sampling Frequency B. Alternate Test Stimulus Generation A frequency tone close to the nyquist frequency of the A/D converter sampling frequency needs to be generated to excite the worst-case non-linearity in the device. The proposed approach uses an up-conversion mixer to generate such high frequency input tones from a low speed tester. The input to the IF port of the mixer is a sinusoidal signal from the tester. The LO frequency to the mixer is also generated from the low cost tester to avoid synchronization issues. The IF and LO tones are generated* such that the up-converted tone falls at the frequency at which the dynamic specifications of the device needs to be measured. ! IN = ! IF + ! LO EQ 5 where,
! IF and ! LO are the IF and LO frequency tones and ! IN is the frequency at which the dynamic specifications of the device needs to be measured. Thus it is possible to generate an input tone at 2 times the maximum frequency capability of the tester (if ! IF and ! LO are kept equal to ! MAX , where ! MAX is the maximum frequency output of the tester). If the A/D converter nyquist frequency is more than 2 times the maximum tester frequency, a series of mixers can be used to up-convert the output of the first mixer. IV. VALIDATION OF PROPOSED APPROACH A. Simulation Validation The components were modeled and the proposed approach was simulated in MATLAB. The following subsections describe the modeling of the components and simulation of the alternate test set-up.
O(t) = A0*I(t)3 +A1*I(t)2 +A2*I(t) +A3 + N(t) EQ 6 Where, A2 = 10(Conversion Gain)/20 A0 = 4* A2 /3*(IIP3)2 A1 = A3 =0 I(t) = ACin(t)*LO(t) + LOfeed(t) ACin(t) is the low frequency input from the tester LO(t) is the local oscillator sinusoidal signal LOfeed(t) is the LO leakage power N(t) is the output noise which is calculated based on Noise Factor and input noise floor. The following were the specifications of the mixer that was modeled. Conversion Gain: 4.5 dB IIP3: 24 dBm LO Leakage: -23 dB NF: 10.5 dB A.2 A/D Converter Modeling The A/D converter transfer function was modeled by random differential non-linearity* (DNL) characteristics. The sampling frequency of the A/D converter modeled was 1Gsps and resolution was 8 bit. Flash architecture was assumed and the code-widths were randomly varied from the ideal value of 1 LSB to insert non-ideality in the device. A.3 Simulation of the Alternate Test Set-Up The device-under-test (DUT) was chosen to be an 8-bit 1Gsps A/D converter. 100 such devices were simulated to validate the proposed approach. The input frequency for testing the dynamic specifications was chosen to be, close to the Nyquist frequency, at 490.11MHz. The input frequency of the DUT was chosen in order to meet the coherent sampling condition. The output of the low cost tester was an IF tone at ! IF = 240.11MHz and a LO frequency tone at
! LO = 250 MHz. 2nd and 3rd harmonics
from the low cost tester were assumed to be at -60dBc. The IF and LO frequency sinusoidal signals were fed to the mixer. Fig 5 shows the frequency spectrum of the test stimulus that was applied to the A/D converter DUT. The sampling clock in hardware can be generated by an external clocking source that is synchronized with the tester using a BNC cable via 10MHz signal from the tester. The sampling *As opposed to conventional methodology, here a spectrally pure input signal is not required. All that is required is a tone at the nyquist frequency of the A/D converter to excite the high frequency non-linearity effects. **this modeling should not be confused with the static A/D converter modeling. The DNL characteristic of an A/D converter is different at low frequencies. We do not need a DNL model of the A/D converter that varies with frequency because the input frequency is not varied in the proposed test strategy.
4 clock jitter was assumed to be Gaussian distributed with 10ps standard deviation. The frequency spectrum of the input signal to the A/D converter DUT shows the presence of multiple tones. Frequency Spectrum of the Test Stimulus to DUT
B. Hardware Validation The proposed methodology is currently verified in hardware. A 14 bit 40Msps National Semiconductor device is used to validate the methodology. The input was a multitone signal to simulate the mixer effect. The input signal was sourced from a 12bit DAC. The preliminary hardware data shows maximum prediction error in SNR specifications of about 3dB.
20 0 -20 -40
Power dBm
SFDR 1.70dB 0.46dB Second Harmonic 3.29dB 0.70dB Third Harmonic 1.70dB 0.46dB THD 1.56dB 0.44dB Table 2 Results summary for Two Mixer
-60 -80 -100 -120
V. CONCLUSION
-140 -160
0
0.5
1
1.5
2 2.5 3 Frequency in Hz
3.5
4
4.5
5 8
x 10
Fig 4. Frequency Spectrum of the test stimulus to the DUT The output of the A/D converter was under-sampled at a sampling frequency of 250Msps. The under-sampled output of the A/D converter was stored for model building. The conventional specification testing was then done on first 60 simulated A/D converter devices. A set of models, one corresponding to each specification, mapping measurements to the specifications was then built using non-linear regression splines (MARS). The proposed approach was then validated on the rest 40 simulated devices. The device response was measured on the simulated alternate test set-up and the pre-developed models were used to estimate the accurate specifications. The maximum and the average error in estimation of the specifications using the proposed approach are shown in Table1. The average error in prediction is less than 2%. THD was calculated by summing power of first 8 harmonics. Maximum Average Error Error SNR 0.7dBc 0.37dB SFDR 1.6dB 0.70dB Second Harmonic 2.38dB 1.08dB Third Harmonic 1.60dB 0.70dB THD 1.69dB 0.72dB Table 1 Results summary for Single Mixer Similar validation methodology was used for two mixer set-up where the frequencies sourced from the tester were ! IF =145.05MHz and ! LO =100MHz. The output of the first mixer was filtered using a 2nd order band-pass filter and then self-mixed to generate a tone at 490.11MHz. Table 2 shows the result summary for this simulation experiment.
SNR
Maximum Error 0.43dBc
Average Error 0.18dB
This paper describes a novel approach to test high speed A/D converters. The alternate testing methodology is used to ease the tester resource requirements in testing highspeed, high-resolution A/D converters. The main contribution of the proposed approach is that it enables the measurement of true device SNR in presence of sampling clock jitter. Hardware verification is currently going on using a National Semiconductor 14 bit A/D converter. The preliminary results show a maximum 3dB prediction error in SNR measurements. REFERENCES [1] Mielke J.A., “Frequency domain testing of ADCs”, IEEE Design & Test of Computers, vol. 13 , no. 1 , Spring 1996, pp. 64 – 69. [2] McLeod D.A., “Dynamic testing of analogue to digital converters”, International Conference on Analogue to Digital and Digital to Analogue Conversion, 17-19 September 1991, pp. 29 – 35. [3] Yuan Tzu Ting, Li Wei Chao, Wei Chung Chao, “A practical implementation of dynamic testing of an AD converter”, Proceedings of the Fifth Asian Test Symposium, 20-22 November 1996, pp. 238 – 243. [4] Yamaguchi T., Soma M., “Dynamic testing of ADCs using wavelet transforms”, International Test Conference, 1-6 November 1997, pp.379 – 388. [5] Zhongjun Yu, Degang Chen, Geiger R., “Accurate testing of ADC's spectral performance using imprecise sinusoidal excitations”, Proceedings of the 2004 International Symposium on Circuits and Systems,vol. 1,23-26 May 2004, pp. 645-648. [6] Appnote on testing dynamic parameters of high speed A/D conerters http://www.maxim-ic.com/appnotes.cfm/ appnote_number/728 [7] P.N. Variyam et. al. “Prediction of analog performance parameters using fast transient testing”, IEEE Trans. CAD of integrated circuits and systems, March 02, pp. 349-361. [8] P.N. Variyam and Abhijit Chatterjee, “Enhancing test effectiveness for analog circuits using synthesized measurements”, Proc. VLSI Test Symposium, 1998, pp. 132-137. [9] Ganesh Srinivasan, Shalabh Goyal, Abhijit Chatterjee, “Enhancing Alternate Test Performance of Analog Circuits Using Reconfiguration for Testability”, Asian Test Symposium, 2004. [10] J. H. Friedman, “Multivariate Adaptive Regression Splines”, The Annals of Statistics,vol. 19, no.1, 1991, pp. 1141.
