D converter with 16â18 bit ... - CiteSeerX
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INTEGRATION, the VLSI journal 39 (2005) 48–61 www.elsevier.com/locate/vlsi
A versatile Nyquist-rate A/D converter with 16–18 bit performance for sensor readout applications Pieter Rombouts, Ludo Weyten Electronics and Information Systems Lab., Ghent University, St.-Pietersnieuwstraat 41, 9000 Gent, Belgium Received 29 June 2004; received in revised form 2 December 2004; accepted 17 December 2004
Abstract This work presents an ADC core for sensor readout applications. To achieve a high resolution combined with Nyquist-rate A/D conversion, it employs the extended counting technique (IEEE Trans. Circuits Syst. I, 42(11) (1995) 904). By making the number of counting steps programmable, the circuit allows to trade conversion speed for accuracy. In its nominal (lowest-accuracy) mode a conversion requires 71 clock cycles and achieves 16-bit performance in a conversion time of 50 ms: In the slowest, highest-accuracy mode it achieves 18-bit performance in a conversion time of 365 ms: To achieve this in a CMOS process that only provides nonlinear capacitors, a nonlinearity correction is investigated. It is shown that this can be approximated by inverting the voltage to charge relationship of the capacitors at the output of the converter. This was implemented as a simple third-order correction, which can easily be done in software. If this correction is omitted, the DNL of the convertor is nearly unchanged but its INL is affected. The circuit’s power consumption is 5 mW. The silicon area including all control and reconstruction logic is 1:3 mm2 : r 2005 Elsevier B.V. All rights reserved. Keywords: Analog-to-digital conversion; Switched-capacitor circuits
Corresponding author. Tel.: ++32 9 264 3393; fax: ++32 9 264 89 18.
E-mail address: [email protected] (P. Rombouts). 0167-9260/$ - see front matter r 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.vlsi.2004.12.002
ARTICLE IN PRESS P. Rombouts, L. Weyten / INTEGRATION, the VLSI journal 39 (2005) 48–61
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1. Introduction This work presents an ADC core for use in sensor readout applications. While the circuit is intended as a ‘‘general purpose’’ IP-block to be embedded in various systems on a chip, the application domain imposes some special requirements. These include a high resolution of 16 bits or more with guaranteed monotonicity. Also, the offset should be low. On the other hand, the conversion speed is rather low: most envisaged applications can tolerate a conversion time of 50 ms or more. Another desired feature is that the ADC should operate at Nyquist-rate. This is desirable, because in sensor readout applications, Nyquist-rate operation is more intuitive than oversampled operation. Some further considerations on this will be discussed in Section 2.4. Extended counting seems a promising candidate to fullfill these requirements [1–4]. This technique is a blend of first-order SD modulation with its potential of high resolution but too low speed on the one hand [5] and algorithmic conversion with its higher speed but too low accuracy on the other hand [6]. The resulting ADC operates at Nyquist rate. Moreover, the reconstruction logic is considerably less complex than the decimation filter that would be required for a SD modulation ADC. This is particularly relevant for sensor readout where often a conservative (lowcost) technology is used: e.g. in this design 0:6 mm CMOS. As will be demonstrated, the resulting circuit is quite compact, even in such a rather old technology. In previously described extended counting converters, the linearity was limited to about 15-bit [3,4]. In this work, the viability of extended counting A/D conversion for up to 18-bit performance is demonstrated. This ADC core will be embedded in significantly larger chips. Therefore, the overhead of additional process steps may be considerable and, hence, it is desirable that the ADC can be implemented in the basic form of the target process. Unfortunately this way, no linear capacitors are available. Hence, the A/D converter circuit has to cope with considerable capacitor nonlinearity. This does not affect the monotonicity. However, the integral nonlinearity (INL) is affected, which may be unacceptable in some applications. To overcome this problem, an efficient digital correction technique is investigated in this work and its applicability and limitations are discussed.
2. ADC architecture 2.1. Extended counting The ADC architecture is based on the extended counting technique described in [1,3]. Here we will review the basics of this technique. It is a compromise between 1st-order SD modulation with its high accuracy but relatively low speed on the one hand and algorithmic A/D conversion with its higher speed but lower accuracy on the other hand [1]. For one A/D conversion the converter passes through 2 modes. In the first mode the system operates as a resettable first-order SD modulator to convert the most significant bits. This mode is called the ‘counting conversion’. Then in a second mode the same hardware is used to convert the least significant bits by an algorithmic A/D conversion technique. This mode is called the ‘extended conversion’. Both the counting as well as the extended conversion mode will take several clock cycles.
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P. Rombouts, L. Weyten / INTEGRATION, the VLSI journal 39 (2005) 48–61 C1
C1
C2
C2
Vin
comp.
OA Vi-1
Di-1Vref
OA
Di-1
First Phase
Vi
Second Phase
Fig. 1. Circuit configuration during both phases of a counting conversion step.
We shall discuss now the approach for a DC input voltage V in : During the first part of a conversion the system will be in the counting conversion mode. The circuit configuration during the counting conversion is depicted in Fig. 1. It consists of a switched-capacitor integrator and a comparator. In reality the circuits are fully differential, but for simplicity the discussion is done for a single-ended equivalent. After an initial reset the normal operation in each step consists of two phases. In the first phase of the ith step, the input voltage is sampled on the input capacitor C 2 : The internal state V i1 of the conversion algorithm is held across the capacitor C 1 : Meanwhile, the comparator decides the code Di1 based on this internal state V i1 : In the second phase the top plate of capacitor C 2 is switched to the opamp’s inverting input node while the bottom plate is switched to plus or minus the reference voltage V ref depending on the value of the code Di1 : This way the internal state (the voltage across C 1 ) is updated to V i as V i ¼ V i1 þ
C2 ðV in Di1 V ref Þ. C1
(1)
This is the typical way a first-order SD modulator is implemented in switched capacitor technology. Each conversion starts with a reset and hence V 0 ¼ 0: Thus we obtain the final output voltage V count after the N steps of the counting conversion [3]: V count ¼ N
N X C2 C2 V in V ref Di . C1 C1 i¼1
(2)
To reconstruct the input voltage V in ; Eq. (2) can be rewritten as P V ref N i¼1 Di þ ðC 1 =C 2 ÞV count . (3) V in ¼ N We see that the input voltage V in can be reconstructed from the known values of the Di codes and from the (as yet undetermined) value of the voltage V count : After the counting steps, the system goes into the extended conversion mode where the voltage V count is measured by the more efficient but less accurate algorithmic A/D conversion technique described in [6]. This is achieved by rearranging the operational amplifier and capacitors [3]. We shall make abstraction of the extended conversion and assume that it results in a digital approximation Dext ðV count Þ of the residue voltage V count : Errors during the extended conversion are modelled by an additive error term : This error is an unknown function of the residue voltage V count : Typically it is caused by circuit imperfections. Then we can write Dext ðV count Þ ¼
V count þ OðÞ. V ref
(4)
ARTICLE IN PRESS P. Rombouts, L. Weyten / INTEGRATION, the VLSI journal 39 (2005) 48–61
Together with Eq. (3) this allows to obtain the digital output DðV in Þ: PN Di þ ðC 1 =C 2 ÞDext ðV count Þ . DðV in Þ ¼ i¼1 N By combining Eqs. (3)–(5) it can then be shown that the digital output DðV in Þ equals DðV in Þ ¼
V in OðÞ þ . N V ref |ffl{zffl}
51
(5)
(6)
ADC error
This equation indicates the main property of the extended counting conversion technique, i.e. the errors due to circuit imperfections are divided by N, the number of counting steps. This clearly illustrates the speed-accuracy trade off: if we want to decrease the error, N must be large, but this increases the conversion time. 2.2. Architectural choices In the target process for our design, the accuracy of the algorithmic conversion is limited to 10–11 bit due to capacitor mismatch. However, the design goal was to achieve better than 16-bit performance. Therefore, the counting conversion should relax the accuracy requirements on the extended conversion with a factor of 32–64. To guarantee this the minimum number of counting steps N was first chosen equal to 64 according to Eq. (6). To increase the versatility of the ADC core, the number of steps in the counting phase was made user-selectable: 64, 128, 256 or 512. This way the user can select between a lower speed and a higher accuracy or the other way round. 2.3. Time-varying input In the analysis above it was assumed that the input signal is kept constant during a complete conversion cycle. However, if the input signal changes during the conversion cycle, this results in a constant delay filter-effect [3] due to the averaging which is inherent in this A/D conversion technique. More precisely, Eq. (6) should be replaced by PN1 V in ðt0 þ iT clk Þ , (7) D ¼ i¼0 NV ref where the ADC error was neglected. T clk is the period of the ADC clock. In the frequency domain this gives a sinc filter effect. Obviously, this effect disappears if the ADC is preceded by a sample and hold. For slowly varying signals it can be neglected as well. 2.4. Advantages over SD modulation Currently, SD modulation A/D converters are the most popular A/D converters for relatively low-speed, high-accuracy signal processing applications. However the approach in this work has some distinct advantages for the case of sensor readout applications. This is due to the fact that this A/D converter essentially converts one sample at a time. For example this ADC can be kept in sleep-mode (low-power shut-down), convert 1 sample (or a limited number of samples) upon a
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‘‘start conversion signal’’, wait for the result and then decide whether additional conversions are needed. This way the conversion frequency can easily be adapted, while the conversion time for 1 A/D conversion remains fixed. For instance, in surveillance applications a rate of 1 sample per second may be sufficient during normal operation, while a higher observation frequency may be needed once an anomalous event is detected. Moreover, even the number of count-steps, and hence also the accuracy, can be adapted on a sample per sample basis. These types of adaptation are rarely needed in signal processing applications, but can certainly be useful in sensor readout applications.
3. Capacitor nonlinearity 3.1. Basic phenomenon The target process in its basic form does not provide highly linear capacitors. An analog option with a poly2 layer is available and would provide highly linear capacitors. However, in this work we have investigated how to achieve the targeted performance without the additional cost of the analog option. This means that we have to use nonlinear capacitors and, hence, the charge QðV Þ that is sampled on a capacitor is not a linear function of the voltage V across it: QðV Þ ¼ Cf ðV ÞaCV .
(8)
To investigate what changes if the capacitors in the circuit are nonlinear, we should reconsider the circuit-level configuration of the converter during the counting conversion (Fig. 1). Again we will first assume that the input voltage V in is constant. It was shown in [7] that the charge-transfer operation of switched-capacitor circuits itself is not affected by the nonlinearity of the capacitors. Hence, it is useful to think of the A/D converter in terms of charges instead of voltages. This is illustrated in Fig. 2. Here, the charge Qin on the input capacitor is considered as the input signal and the charge Qi on the feedback capacitor represents the internal state of the conversion algorithm. Since the charge transfer operation is unaffected, nonlinearity of the capacitors does not influence the signal processing operation of the circuit, when thinking in terms of charges. Therefore, a similar equation as (6) can be developed for the charges DðQin Þ ¼
Qin OðÞ þ , N count Qref |fflffl{zfflffl}
(9)
ADC error
Qi-1
Qin
C1 C2
C2 Vin
Qi
Di-1Qref
C1
comp.
OA
Di-1Vref
OA
Vi-1
Vi
Di-1
First Phase
Second Phase
Fig. 2. Circuit configuration during the counting conversion with charge signals.
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Vin
f( )
53
Digital
Qin
ADC
D
f -1( )
Dcorr
Nonlinearity correction
Fig. 3. Switched-capacitor A/D converter with nonlinear capacitors.
where Qref corresponds to the reference charge C 2 f ðV ref Þ: This implies that the output of a switched-capacitor analog (charge) to digital conversion is not affected by capacitor nonlinearity. From these elements we can conclude that the effect of nonlinear capacitors only appears where charges are translated into voltages, i.e. at the input of the converter. From a signal processing perspective this is described by the diagram of Fig. 3. 3.2. Simple digital correction technique If we neglect the errors of the A/D converter itself, the output of the analog (charge) to digital conversion equals D¼
Qin f ðV in Þ ¼ . Qref f ðV ref Þ
(10)
Then this capacitor nonlinearity can be inverted at the output of the converter to cancel its effect. This is represented in Fig. 3. Evidently, this requires that the voltage to charge function f ðÞ is known exactly. In the target process, a poly0-poly1 capacitor is available. Normally it is used to implement EEPROM. This capacitor is used in the circuits described here. It exhibits a pronounced 1st- and 2nd-order voltage coefficient. For our case, where the circuit is implemented fully differential, the effect of the 1st-order voltage coefficient will be rejected. Hence, without the compensation technique of Fig. 3, the linearity would be limited by the 2nd-order voltage coefficient. Still this would not affect the monotonicity of the circuit. For our case, the function f ðV in Þ becomes Qin ¼ Cf ðV in Þ ¼ CV in ð1 þ aV 2in Þ.
(11)
To obtain the corrected digital output Dcorr ; this function should be inverted. Since the error is small, the correction may be very well approximated by the following simplified relationship: Dcorr ¼ D bD3 ,
(12) 2
1
where b equals af ðV ref Þ : This approximation of the inverse function f will be accurate to 5th order. Note that the correction of Eq. (12) can easily be done by the microprocessor, which performs the processing on the ADC output data. Hence, application of the correction scheme may be a viable alternative over the use of the poly2 option. An important limitation of this correction technique is that it requires knowledge of the a coefficient. The simplest solution here is to use the nominal value of this coefficient. Alternatively,
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Vin(t)
f( )
Qin(t)
fSAMPLE Qin(i Tclk)
Reconstruction filter
D(i TSAMPLE)
ADC
Fig. 4. Switched-capacitor A/D converter with nonlinear capacitors.
this value may be determined during wafer testing and written in EEPROM, which is available. Finally, more complex schemes with adaptive estimation [8,9] of the a coefficient are thinkable but out of the scope of this work. For the rest we will assume that the a coefficient is known.
4. The effectiveness of the correction technique for rapidly changing input signals It is important to note that the correction scheme outlined above (Fig. 3) is only correct for signals that are constant during the entire conversion cycle. If the input signal cannot be considered constant during a conversion cycle, Eq. (9) and Fig. 3 are not valid because they neglect the filtering and downsampling effect of the reconstruction logic, which was already discussed in Section 2.3. In Fig. 4 the signal processing diagram for the AD converter with nonlinear input capacitors is shown where these effects are included. The most important deviation from the diagram of Fig. 3 is due to the filtering inherent to the reconstruction. Let us e.g. assume that we have an input tone with a certain amplitude. This tone will be filtered according to Eq. (7) and hence exhibit a different amplitude at the output of the converter. Moreover, for our case of a third-order nonlinearity, there will also be a distortion tone. This distortion tone is at higher frequency and hence the attenuation will be stronger for this distortion tone than for the original tone. Hence, for a single tone input signal with frequency f, the correction scheme of Fig. 3 will not completely cancel the third harmonic (HD3 ) but instead suppress it according to HD3 / Hð3f Þ Hðf Þ3 ,
(13)
where Hðf Þ is the transfer function of the reconstruction filter. This relationship is plotted in Fig. 12, together with the actually measured third harmonic. Similar expressions can be obtained for two-tone inputs and in principle for multi-tone inputs as well.
5. CMOS implementation The circuit was implemented in a standard double-metal 0:6 mm CMOS process. The main building blocks (shown in Fig. 1) are the operational amplifier and the comparator. The operational amplifier (Fig. 5) is a conventional folded cascode design with gain boost amplifiers [10]. The gain boosters are needed to achieve an adequate DC-gain, which was 110 dB according to simulation. An NMOS input stage was used, although the 1=f noise performance of the NMOS-transistors is considerably worse than their PMOS counterparts. This is acceptable
ARTICLE IN PRESS P. Rombouts, L. Weyten / INTEGRATION, the VLSI journal 39 (2005) 48–61
Vbias,2
55
Vbias,2
Vout–
Vin+
Vin–
Vout+
Vbias,1 CMFB
CMFB
Fig. 5. Opamp. C
Vin–
C –
+
+
–
C Vin+
(a)
C
Vout+ C C
φ1 φ2
Vout– C
(b)
Fig. 6. (a) Schematic of the chopper and (b) its associate timing.
because the offset requirement on the A/D conversion imposes the use of a chopping technique [11], which nearly eliminates the effect of the opamp’s 1=f noise. The details of the chopping circuit and the associated timing are shown in Fig. 6. The comparator is implemented as a pre-amplifier followed by a latch. The pre-amplifier is a simple NMOS differential pair loaded with ordinary and cross-coupled PMOS mirrors, very similar to what was used in [3,4]. Fig. 7 shows a microscope photograph of the ADC core, which was incorporated in a test chip. The silicon area of the core itself (including all logic) is slightly less than 1:3 mm2 : This includes storage registers and testability features such as a boundary scanpad. It does not include the nonlinearity correction of Eq. (12).
Fig. 7. Microphotograph of the core rectangle.
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6. Experimental results We received 5 samples of the test chips, all of which were functional with very similar performance. An operational amplifier circuit with phase error compensation similar to [12] was used to drive the differential input of the circuit. Commercially available audio operational amplifiers were used for this purpose. The measurements described here were performed with the nominal 1.42 MHz clock and 3.3 V supply voltage (see Table 1). However, it was verified that the design has nearly identical performance for supply voltages ranging from 2.7 to 5 V. 6.1. Static measurements Fig. 8 shows the INL (estimated from a code-density test according to [13]) for the fastest conversion time of 50 ms; where N count ¼ 64: Here, the ADC-output was truncated to 16-bit. The plot corresponds to the case without correction of the 2nd-order voltage coefficient and clearly shows the third-order nonlinearity which is caused by capacitor nonlinearity as explained above. From this measurement the 2nd-order voltage coefficient a of the capacitors can be determined by fitting the data to Eq. (11). This procedure was repeated for the 5 available test chips. All these measurements gave nearly identical estimations of the 2nd-order voltage coefficient which turned Table 1 Nominal ADC conditions Clock frequency Supply voltage Common mode voltage Nominal reference voltages Nominal input voltage range
1.42 MHz 3.3 V 1.65 V (halfway supply) 1:5 V differential 1:5 V differential
6
INL (LSB@16bit)
4
2 0 –2
–4 –6
–4
–3
–2
–1
0
1
Output code
2
3
4 x 104
Fig. 8. INL with the output truncated to 16-bit reconstructed from a code-density test for 64 counting steps without correction of the 2nd-order voltage coefficient.
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6
6
4
4
INL (LSB@16bit)
INL (LSB@16bit)
out to be 0:18%=V 2 for this batch of test chips. The nominal 2nd-order voltage coefficient for the process was 0:13%=V 2 : The case where the voltage-coefficient correction of Eq. (12) was applied is shown in Fig. 9. Here, two cases are distinguished. In the first case, shown in Fig. 9(a), the nominal value of a is used. The resulting INL is within 2 LSB: In the second case, shown in Fig. 9(b), the actual (fitted) value of a is used. The resulting INL is within 1:5 LSB: This case corresponds to what can be expected when the optional (linear) poly2-poly1 capacitors are used. From the same test also the DNL (not shown) was estimated and it was found that the DNL is within 0:8 and þ0:4 LSB in this accuracy mode. The DNL was nearly identical for the cases with or without correction of the capacitor nonlinearity. In the highest accuracy mode with 512 counting steps and a corresponding conversion time of 365 ms; the INL at the 18-bit level was measured as well. It is shown in Fig. 10(a) for the case with the nonlinearity correction of Eq. (12) where the actual value of a was used. Here the INL is within 1:7 LSB: The plot without nonlinearity correction is not shown, but of course in this case the INL is dominated by a 3rd-order nonlinearity leading to an INL within 16 LSB: In the case where the correction is performed with the nominal value of a; the INL is within 4:6 LSB: The DNL is plotted on Fig. 10(b) and is within 0:55 and +0.25 LSB. The DNL plot for the case without correction for the capacitor nonlinearity looks identical.
2 0 –2 –4 –6 –4
–3
–2
–1
(a)
0
1
2
3
Output code
x 10
0 –2 –4 –6 –4
4 4
2
–3
(b)
–2
–1
0
1
4
3
2
Output code
x 104
2
0.3
1.5
0.2
DNL (LSB@18bit)
INL (LSB@18bit)
Fig. 9. INL with the output truncated to 16-bit reconstructed from a code-density test for 64 counting steps with correction of the 2nd-order voltage coefficient (a) with the nominal value of a and (b) with the actual value of a:
1 0.5 0 –0.5 –1 –1.5 –2 –1.5
(a)
0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5
–1
–0.5
0
0.5
Output code
1
–0.6 –1.5
1.5 5
x 10
(b)
–1
–0.5
0
0.5
Output code
1
1.5 5
x 10
Fig. 10. (a) INL and (b) DNL with the output truncated to 18-bit reconstructed from a code-density test for 512 counting steps with correction of the 2nd-order voltage coefficient.
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Analog and digital power consumption of the ADC core were measured separately: 4.4 mW analog and 0.4 mW by the controller, the reconstruction logic and the clock and switch drivers. This makes a total of slightly less than 5 mW in total, independent of the accuracy mode. 6.2. Low-frequency measurements The converter is not intended for applications with rapidly changing input signals. Moreover, as outlined in Section 4, the correction scheme for the capacitor nonlinearity is not very effective for input signals with a variation that is fast compared to the sampling frequency. However, dynamic measurements with relatively slowly varying signals can easily be done. For this purpose a sinusoidal signal was applied at the input of the converter. Fig. 11 shows a typical spectrum (32 K FFT) for the lowest accuracy mode (N count ¼ 64 counting steps) where the converter operates at 20 KS/s. Fig. 11(a) corresponds to the case without correction of the capacitor nonlinearity. The 0:6 dB input signal has a frequency of about 1 KHz. The plot is normalized to full scale. In this figure no 1=f -noise can be observed, which confirms the well-behaved performance of the chopper. As expected, the capacitor nonlinearity causes a pronounced third harmonic ð82:5 dBcÞ: This measurement provides an alternative way to determine the 2nd-order voltage coefficient a of the capacitors. This can be done by fitting a sine wave, that is distorded according to Eq. (11), to the measured data. This procedure was repeated for the 5 available testchips at various supply and reference voltages and in all the implemented accuracy modes. Also here all the measurements gave nearly identical estimations of the 2nd-order voltage coefficient, which was consistent with the static measurement. Fig. 11(b) shows the FFT result for the case where the error correction scheme of Fig. 3 uses the actual (estimated) voltage coefficient. Now the third harmonic is reduced to 107 dBc and does not affect the signal-to-noise (SNR) and distortion ratio which is 91 dB in this case. For the case where the correction is done with the nominal 2nd-order voltage coefficient, the third harmonic becomes 94 dBc and the signal-to-noise and distortion ratio SNDR ¼ 89 dB: Unfortunately, no data on the stability and process variation of the 2nd-order voltagecoefficient are available. Based on our measurements we can already conclude that a deviation of 30% from the nominal value is not impossible. In the lowest accuracy mode of this converter, this would affect the performance of the correction scheme only to a limited extent. Hence, its 0
0 SNR = 91 dB SNDR = 83 dB THD = 83 dB
–40
HD2 (–107 dBc)
–80 –100 –120
–40 –60 –100 –120 –140
–160
–160 0
2
4
6
Frequency (kHz)
8
–180
10
(b)
HD2 HD3 (–107 dBc) (–107 dBc)
–80
–140 –180
(a)
HD3 (-83 dBc)
–60
SNR = 91 dB SNDR = 91 dB THD = 103 dB
–20
Spectrum (dB)
Spectrum (dB)
–20
0
2
4
6
8
10
Frequency (kHz)
Fig. 11. FFT-result in the lowest-accuracy mode (64 counting steps) at 20 kSample=s (a) without and (b) with correction of the 2nd-order voltage coefficient.
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Table 2 ADC dynamic performance in various accuracy modes Number of counting steps N
64
128
256
512
Sampling frequency Peak SNR Peak SNDR Peak SNDR (with correction) DR DR (from short-circuit)
20 kHz 91 dB 86 dB 91 dB 93 dB 95 dB
10.5 kHz 96 dB 89 dB 95 dB 97 dB 100 dB
5.4 kHz 100 dB 92 dB 99 dB 101 dB 106 dB
2.7 kHz 104 dB 96 dB 102 dB 105 dB 110 dB
Table 3 ADC sensitivities to power and common mode voltages Common-mode input voltage range
1.3–2.0 V
CMRR (at 1 kHz)
74 dB
PSRR (at 1 kHz)
95 dB
application even with the nominal coefficient may be a viable alternative over the use of the poly2 option. To determine the dynamic range (DR), the peak SNR and the peak SNDR, a complete set of dynamic measurements was performed for each accuracy mode (number of counting steps) both with and without the nonlinearity correction scheme. All these results are tabulated in Table 2. The dynamic range can also be determined by a measurement with short-circuited inputs. This figure is also mentioned in Table 2. It turns out that it is always larger than the dynamic range from the signal measurement. This difference is attributed in part to noise from the driving amplifiers and in part to kickback from the switched input capacitor to the output of the driving operational amplifier, both of which do not occur in the case of the short-circuit measurement. The short-circuit measurements on the 5 test chips revealed a small systematic offset of +1.6 LSB at 16 bit with a standard deviation of 0.5 LSB at 16 bit, nearly independent of the number of counting steps. The ADCs sensitivities to power and common mode voltages were measured as well and are tabulated in Table 3. 6.3. Rapidly changing input signals For completeness the third harmonic was also measured as a function of the input frequency. This was done by applying a sine wave with an amplitude of 0:3 dB of the full scale at the input of the converter. The amplitude of the residual third harmonic after applying the nonlinearity correction is shown in Fig. 12. The theoretical curve according to Eq. (13) is shown as well. The
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Third harmonic (dB)
–90 Calculated according eq. (13)
–95
–100
–105
–110
1/16
1/8
1/4
1/2
Frequency (1/Fsample)
Fig. 12. Third harmonic vs. fundamental frequency.
plot corresponds to the nominal accuracy mode with 64 counting steps. It is obvious from the figure that the effectiveness of the correction technique decreases for higher input frequencies. For low frequencies the measurement is limited by the accuracy of the distortion of the used (lowdistortion) generator.
7. Conclusion In this paper we have presented a versatile ADC core for sensor readout applications. To achieve a high resolution combined with a Nyquist-rate conversion it employs the extended counting technique [1]. It is shown that this technique is capable of realizing up to 18 bits of resolution. To the authors’ knowledge, this is the highest accuracy that has been reported for an extended counting ADC until now. To achieve this performance without linear capacitors, a nonlinearity correction is required. It is shown that this can be performed by inverting the voltage to charge relationship of the capacitors. This was approximated by a simple third-order correction, which is easily implemented in software on the microcontroller that processes the data. A drawback of this approach is that it requires knowledge of the capacitor’s voltage coefficient. Next to this, the technique is only effective for slowly varying signals, but this is not a limitation for the target applications. If the nonlinearity correction is omitted, the monotonicity (DNL) and noise performance (SNR and DR) of the convertor remain unchanged but its linearity performance (SNDR and INL) is affected.
Acknowledgements The authors wish to thank Ronny Grosfeld, Kenneth Verstraete, Jerome Casters and Rudi De Winter of Melexis for technical discussions and for initiating this design project.
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References [1] C. Jansson, A high-resolution, compact, and low-power ADC suitable for array implementation in standard CMOS, IEEE Trans. Circuits Syst.-I 42 (11) (1995) 904–912. [2] J. Markus, J. Silva, G.C. Temes, Theory and applications of incremental Delta Sigma converters, IEEE Trans. Circuits Syst.-I 51 (4) (2004) 678–690. [3] P. Rombouts, W. De Wilde, L. Weyten, A 13.5-bit 1.2 V micropower extended counting A/D converter, IEEE J. Solid-State Circuits 36 (2) (2001) 176–183. [4] J. De Maeyer, P. Rombouts, L. Weyten, A double sampling extended counting ADC, IEEE J. Solid-State Circuits 39 (3) (2004) 411–418. [5] J. Robert, G.C. Temes, V. Valencic, R. Dessoulavy, P. Deval, A 16-bit low-voltage CMOS A/D converter, IEEE J. Solid-State Circuits 22 (2) (1987) 157–163. [6] K. Nagaraj, Efficient circuit configurations for algorithmic analog to digital converters, IEEE Trans Circuits Syst.II: Analog Digital Signal Process. 40 (12) (1993) 777–785. [7] H. Yoshizawa, P. Ferguson, G. Temes, MOSFET-only switched-capacitor circuits in digital CMOS technology, IEEE J. Solid-State Circuits 34 (6) (1999) 734–747. [8] I. Galton, Digital cancellation of D/A converter noise in pipelined A/D converters, IEEE Trans. Circuits Syst.-I 47 (3) (2000) 185–196. [9] B. Murmann, B.E. Boser, A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification, IEEE J. SolidState Circuits 38 (12) (2003) 2040–2050. [10] E. Sackinger, W. Guggenbuhl, A high-swing high-impedance MOS cascode circuit, IEEE J. Solid-State Circuits 25 (1) (1990) 289–298. [11] C. Enz, G. Temes, Circuit techniques for reducing the effects of opAmp imperfections: autozeroing, correlated double sampling, and chopper stabilization, Proceedings of The IEEE 84 (11) (November 1996) 1584–1614. [12] D. Baert, Circuit for the generation of balanced output signals, IEEE Trans. Instrum. Meas. 48 (6) (1999) 1108–1110. [13] J. Doernberg, H.S. Lee, D.A. Hodges, Full-speed testing of A/D Converters, IEEE J. Solid-State Circuits 19 (6) (1984) 820–827.
INTEGRATION, the VLSI journal 39 (2005) 48–61 www.elsevier.com/locate/vlsi
A versatile Nyquist-rate A/D converter with 16–18 bit performance for sensor readout applications Pieter Rombouts, Ludo Weyten Electronics and Information Systems Lab., Ghent University, St.-Pietersnieuwstraat 41, 9000 Gent, Belgium Received 29 June 2004; received in revised form 2 December 2004; accepted 17 December 2004
Abstract This work presents an ADC core for sensor readout applications. To achieve a high resolution combined with Nyquist-rate A/D conversion, it employs the extended counting technique (IEEE Trans. Circuits Syst. I, 42(11) (1995) 904). By making the number of counting steps programmable, the circuit allows to trade conversion speed for accuracy. In its nominal (lowest-accuracy) mode a conversion requires 71 clock cycles and achieves 16-bit performance in a conversion time of 50 ms: In the slowest, highest-accuracy mode it achieves 18-bit performance in a conversion time of 365 ms: To achieve this in a CMOS process that only provides nonlinear capacitors, a nonlinearity correction is investigated. It is shown that this can be approximated by inverting the voltage to charge relationship of the capacitors at the output of the converter. This was implemented as a simple third-order correction, which can easily be done in software. If this correction is omitted, the DNL of the convertor is nearly unchanged but its INL is affected. The circuit’s power consumption is 5 mW. The silicon area including all control and reconstruction logic is 1:3 mm2 : r 2005 Elsevier B.V. All rights reserved. Keywords: Analog-to-digital conversion; Switched-capacitor circuits
Corresponding author. Tel.: ++32 9 264 3393; fax: ++32 9 264 89 18.
E-mail address: [email protected] (P. Rombouts). 0167-9260/$ - see front matter r 2005 Elsevier B.V. All rights reserved. doi:10.1016/j.vlsi.2004.12.002
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1. Introduction This work presents an ADC core for use in sensor readout applications. While the circuit is intended as a ‘‘general purpose’’ IP-block to be embedded in various systems on a chip, the application domain imposes some special requirements. These include a high resolution of 16 bits or more with guaranteed monotonicity. Also, the offset should be low. On the other hand, the conversion speed is rather low: most envisaged applications can tolerate a conversion time of 50 ms or more. Another desired feature is that the ADC should operate at Nyquist-rate. This is desirable, because in sensor readout applications, Nyquist-rate operation is more intuitive than oversampled operation. Some further considerations on this will be discussed in Section 2.4. Extended counting seems a promising candidate to fullfill these requirements [1–4]. This technique is a blend of first-order SD modulation with its potential of high resolution but too low speed on the one hand [5] and algorithmic conversion with its higher speed but too low accuracy on the other hand [6]. The resulting ADC operates at Nyquist rate. Moreover, the reconstruction logic is considerably less complex than the decimation filter that would be required for a SD modulation ADC. This is particularly relevant for sensor readout where often a conservative (lowcost) technology is used: e.g. in this design 0:6 mm CMOS. As will be demonstrated, the resulting circuit is quite compact, even in such a rather old technology. In previously described extended counting converters, the linearity was limited to about 15-bit [3,4]. In this work, the viability of extended counting A/D conversion for up to 18-bit performance is demonstrated. This ADC core will be embedded in significantly larger chips. Therefore, the overhead of additional process steps may be considerable and, hence, it is desirable that the ADC can be implemented in the basic form of the target process. Unfortunately this way, no linear capacitors are available. Hence, the A/D converter circuit has to cope with considerable capacitor nonlinearity. This does not affect the monotonicity. However, the integral nonlinearity (INL) is affected, which may be unacceptable in some applications. To overcome this problem, an efficient digital correction technique is investigated in this work and its applicability and limitations are discussed.
2. ADC architecture 2.1. Extended counting The ADC architecture is based on the extended counting technique described in [1,3]. Here we will review the basics of this technique. It is a compromise between 1st-order SD modulation with its high accuracy but relatively low speed on the one hand and algorithmic A/D conversion with its higher speed but lower accuracy on the other hand [1]. For one A/D conversion the converter passes through 2 modes. In the first mode the system operates as a resettable first-order SD modulator to convert the most significant bits. This mode is called the ‘counting conversion’. Then in a second mode the same hardware is used to convert the least significant bits by an algorithmic A/D conversion technique. This mode is called the ‘extended conversion’. Both the counting as well as the extended conversion mode will take several clock cycles.
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P. Rombouts, L. Weyten / INTEGRATION, the VLSI journal 39 (2005) 48–61 C1
C1
C2
C2
Vin
comp.
OA Vi-1
Di-1Vref
OA
Di-1
First Phase
Vi
Second Phase
Fig. 1. Circuit configuration during both phases of a counting conversion step.
We shall discuss now the approach for a DC input voltage V in : During the first part of a conversion the system will be in the counting conversion mode. The circuit configuration during the counting conversion is depicted in Fig. 1. It consists of a switched-capacitor integrator and a comparator. In reality the circuits are fully differential, but for simplicity the discussion is done for a single-ended equivalent. After an initial reset the normal operation in each step consists of two phases. In the first phase of the ith step, the input voltage is sampled on the input capacitor C 2 : The internal state V i1 of the conversion algorithm is held across the capacitor C 1 : Meanwhile, the comparator decides the code Di1 based on this internal state V i1 : In the second phase the top plate of capacitor C 2 is switched to the opamp’s inverting input node while the bottom plate is switched to plus or minus the reference voltage V ref depending on the value of the code Di1 : This way the internal state (the voltage across C 1 ) is updated to V i as V i ¼ V i1 þ
C2 ðV in Di1 V ref Þ. C1
(1)
This is the typical way a first-order SD modulator is implemented in switched capacitor technology. Each conversion starts with a reset and hence V 0 ¼ 0: Thus we obtain the final output voltage V count after the N steps of the counting conversion [3]: V count ¼ N
N X C2 C2 V in V ref Di . C1 C1 i¼1
(2)
To reconstruct the input voltage V in ; Eq. (2) can be rewritten as P V ref N i¼1 Di þ ðC 1 =C 2 ÞV count . (3) V in ¼ N We see that the input voltage V in can be reconstructed from the known values of the Di codes and from the (as yet undetermined) value of the voltage V count : After the counting steps, the system goes into the extended conversion mode where the voltage V count is measured by the more efficient but less accurate algorithmic A/D conversion technique described in [6]. This is achieved by rearranging the operational amplifier and capacitors [3]. We shall make abstraction of the extended conversion and assume that it results in a digital approximation Dext ðV count Þ of the residue voltage V count : Errors during the extended conversion are modelled by an additive error term : This error is an unknown function of the residue voltage V count : Typically it is caused by circuit imperfections. Then we can write Dext ðV count Þ ¼
V count þ OðÞ. V ref
(4)
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Together with Eq. (3) this allows to obtain the digital output DðV in Þ: PN Di þ ðC 1 =C 2 ÞDext ðV count Þ . DðV in Þ ¼ i¼1 N By combining Eqs. (3)–(5) it can then be shown that the digital output DðV in Þ equals DðV in Þ ¼
V in OðÞ þ . N V ref |ffl{zffl}
51
(5)
(6)
ADC error
This equation indicates the main property of the extended counting conversion technique, i.e. the errors due to circuit imperfections are divided by N, the number of counting steps. This clearly illustrates the speed-accuracy trade off: if we want to decrease the error, N must be large, but this increases the conversion time. 2.2. Architectural choices In the target process for our design, the accuracy of the algorithmic conversion is limited to 10–11 bit due to capacitor mismatch. However, the design goal was to achieve better than 16-bit performance. Therefore, the counting conversion should relax the accuracy requirements on the extended conversion with a factor of 32–64. To guarantee this the minimum number of counting steps N was first chosen equal to 64 according to Eq. (6). To increase the versatility of the ADC core, the number of steps in the counting phase was made user-selectable: 64, 128, 256 or 512. This way the user can select between a lower speed and a higher accuracy or the other way round. 2.3. Time-varying input In the analysis above it was assumed that the input signal is kept constant during a complete conversion cycle. However, if the input signal changes during the conversion cycle, this results in a constant delay filter-effect [3] due to the averaging which is inherent in this A/D conversion technique. More precisely, Eq. (6) should be replaced by PN1 V in ðt0 þ iT clk Þ , (7) D ¼ i¼0 NV ref where the ADC error was neglected. T clk is the period of the ADC clock. In the frequency domain this gives a sinc filter effect. Obviously, this effect disappears if the ADC is preceded by a sample and hold. For slowly varying signals it can be neglected as well. 2.4. Advantages over SD modulation Currently, SD modulation A/D converters are the most popular A/D converters for relatively low-speed, high-accuracy signal processing applications. However the approach in this work has some distinct advantages for the case of sensor readout applications. This is due to the fact that this A/D converter essentially converts one sample at a time. For example this ADC can be kept in sleep-mode (low-power shut-down), convert 1 sample (or a limited number of samples) upon a
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‘‘start conversion signal’’, wait for the result and then decide whether additional conversions are needed. This way the conversion frequency can easily be adapted, while the conversion time for 1 A/D conversion remains fixed. For instance, in surveillance applications a rate of 1 sample per second may be sufficient during normal operation, while a higher observation frequency may be needed once an anomalous event is detected. Moreover, even the number of count-steps, and hence also the accuracy, can be adapted on a sample per sample basis. These types of adaptation are rarely needed in signal processing applications, but can certainly be useful in sensor readout applications.
3. Capacitor nonlinearity 3.1. Basic phenomenon The target process in its basic form does not provide highly linear capacitors. An analog option with a poly2 layer is available and would provide highly linear capacitors. However, in this work we have investigated how to achieve the targeted performance without the additional cost of the analog option. This means that we have to use nonlinear capacitors and, hence, the charge QðV Þ that is sampled on a capacitor is not a linear function of the voltage V across it: QðV Þ ¼ Cf ðV ÞaCV .
(8)
To investigate what changes if the capacitors in the circuit are nonlinear, we should reconsider the circuit-level configuration of the converter during the counting conversion (Fig. 1). Again we will first assume that the input voltage V in is constant. It was shown in [7] that the charge-transfer operation of switched-capacitor circuits itself is not affected by the nonlinearity of the capacitors. Hence, it is useful to think of the A/D converter in terms of charges instead of voltages. This is illustrated in Fig. 2. Here, the charge Qin on the input capacitor is considered as the input signal and the charge Qi on the feedback capacitor represents the internal state of the conversion algorithm. Since the charge transfer operation is unaffected, nonlinearity of the capacitors does not influence the signal processing operation of the circuit, when thinking in terms of charges. Therefore, a similar equation as (6) can be developed for the charges DðQin Þ ¼
Qin OðÞ þ , N count Qref |fflffl{zfflffl}
(9)
ADC error
Qi-1
Qin
C1 C2
C2 Vin
Qi
Di-1Qref
C1
comp.
OA
Di-1Vref
OA
Vi-1
Vi
Di-1
First Phase
Second Phase
Fig. 2. Circuit configuration during the counting conversion with charge signals.
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Vin
f( )
53
Digital
Qin
ADC
D
f -1( )
Dcorr
Nonlinearity correction
Fig. 3. Switched-capacitor A/D converter with nonlinear capacitors.
where Qref corresponds to the reference charge C 2 f ðV ref Þ: This implies that the output of a switched-capacitor analog (charge) to digital conversion is not affected by capacitor nonlinearity. From these elements we can conclude that the effect of nonlinear capacitors only appears where charges are translated into voltages, i.e. at the input of the converter. From a signal processing perspective this is described by the diagram of Fig. 3. 3.2. Simple digital correction technique If we neglect the errors of the A/D converter itself, the output of the analog (charge) to digital conversion equals D¼
Qin f ðV in Þ ¼ . Qref f ðV ref Þ
(10)
Then this capacitor nonlinearity can be inverted at the output of the converter to cancel its effect. This is represented in Fig. 3. Evidently, this requires that the voltage to charge function f ðÞ is known exactly. In the target process, a poly0-poly1 capacitor is available. Normally it is used to implement EEPROM. This capacitor is used in the circuits described here. It exhibits a pronounced 1st- and 2nd-order voltage coefficient. For our case, where the circuit is implemented fully differential, the effect of the 1st-order voltage coefficient will be rejected. Hence, without the compensation technique of Fig. 3, the linearity would be limited by the 2nd-order voltage coefficient. Still this would not affect the monotonicity of the circuit. For our case, the function f ðV in Þ becomes Qin ¼ Cf ðV in Þ ¼ CV in ð1 þ aV 2in Þ.
(11)
To obtain the corrected digital output Dcorr ; this function should be inverted. Since the error is small, the correction may be very well approximated by the following simplified relationship: Dcorr ¼ D bD3 ,
(12) 2
1
where b equals af ðV ref Þ : This approximation of the inverse function f will be accurate to 5th order. Note that the correction of Eq. (12) can easily be done by the microprocessor, which performs the processing on the ADC output data. Hence, application of the correction scheme may be a viable alternative over the use of the poly2 option. An important limitation of this correction technique is that it requires knowledge of the a coefficient. The simplest solution here is to use the nominal value of this coefficient. Alternatively,
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Vin(t)
f( )
Qin(t)
fSAMPLE Qin(i Tclk)
Reconstruction filter
D(i TSAMPLE)
ADC
Fig. 4. Switched-capacitor A/D converter with nonlinear capacitors.
this value may be determined during wafer testing and written in EEPROM, which is available. Finally, more complex schemes with adaptive estimation [8,9] of the a coefficient are thinkable but out of the scope of this work. For the rest we will assume that the a coefficient is known.
4. The effectiveness of the correction technique for rapidly changing input signals It is important to note that the correction scheme outlined above (Fig. 3) is only correct for signals that are constant during the entire conversion cycle. If the input signal cannot be considered constant during a conversion cycle, Eq. (9) and Fig. 3 are not valid because they neglect the filtering and downsampling effect of the reconstruction logic, which was already discussed in Section 2.3. In Fig. 4 the signal processing diagram for the AD converter with nonlinear input capacitors is shown where these effects are included. The most important deviation from the diagram of Fig. 3 is due to the filtering inherent to the reconstruction. Let us e.g. assume that we have an input tone with a certain amplitude. This tone will be filtered according to Eq. (7) and hence exhibit a different amplitude at the output of the converter. Moreover, for our case of a third-order nonlinearity, there will also be a distortion tone. This distortion tone is at higher frequency and hence the attenuation will be stronger for this distortion tone than for the original tone. Hence, for a single tone input signal with frequency f, the correction scheme of Fig. 3 will not completely cancel the third harmonic (HD3 ) but instead suppress it according to HD3 / Hð3f Þ Hðf Þ3 ,
(13)
where Hðf Þ is the transfer function of the reconstruction filter. This relationship is plotted in Fig. 12, together with the actually measured third harmonic. Similar expressions can be obtained for two-tone inputs and in principle for multi-tone inputs as well.
5. CMOS implementation The circuit was implemented in a standard double-metal 0:6 mm CMOS process. The main building blocks (shown in Fig. 1) are the operational amplifier and the comparator. The operational amplifier (Fig. 5) is a conventional folded cascode design with gain boost amplifiers [10]. The gain boosters are needed to achieve an adequate DC-gain, which was 110 dB according to simulation. An NMOS input stage was used, although the 1=f noise performance of the NMOS-transistors is considerably worse than their PMOS counterparts. This is acceptable
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Vbias,2
55
Vbias,2
Vout–
Vin+
Vin–
Vout+
Vbias,1 CMFB
CMFB
Fig. 5. Opamp. C
Vin–
C –
+
+
–
C Vin+
(a)
C
Vout+ C C
φ1 φ2
Vout– C
(b)
Fig. 6. (a) Schematic of the chopper and (b) its associate timing.
because the offset requirement on the A/D conversion imposes the use of a chopping technique [11], which nearly eliminates the effect of the opamp’s 1=f noise. The details of the chopping circuit and the associated timing are shown in Fig. 6. The comparator is implemented as a pre-amplifier followed by a latch. The pre-amplifier is a simple NMOS differential pair loaded with ordinary and cross-coupled PMOS mirrors, very similar to what was used in [3,4]. Fig. 7 shows a microscope photograph of the ADC core, which was incorporated in a test chip. The silicon area of the core itself (including all logic) is slightly less than 1:3 mm2 : This includes storage registers and testability features such as a boundary scanpad. It does not include the nonlinearity correction of Eq. (12).
Fig. 7. Microphotograph of the core rectangle.
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6. Experimental results We received 5 samples of the test chips, all of which were functional with very similar performance. An operational amplifier circuit with phase error compensation similar to [12] was used to drive the differential input of the circuit. Commercially available audio operational amplifiers were used for this purpose. The measurements described here were performed with the nominal 1.42 MHz clock and 3.3 V supply voltage (see Table 1). However, it was verified that the design has nearly identical performance for supply voltages ranging from 2.7 to 5 V. 6.1. Static measurements Fig. 8 shows the INL (estimated from a code-density test according to [13]) for the fastest conversion time of 50 ms; where N count ¼ 64: Here, the ADC-output was truncated to 16-bit. The plot corresponds to the case without correction of the 2nd-order voltage coefficient and clearly shows the third-order nonlinearity which is caused by capacitor nonlinearity as explained above. From this measurement the 2nd-order voltage coefficient a of the capacitors can be determined by fitting the data to Eq. (11). This procedure was repeated for the 5 available test chips. All these measurements gave nearly identical estimations of the 2nd-order voltage coefficient which turned Table 1 Nominal ADC conditions Clock frequency Supply voltage Common mode voltage Nominal reference voltages Nominal input voltage range
1.42 MHz 3.3 V 1.65 V (halfway supply) 1:5 V differential 1:5 V differential
6
INL (LSB@16bit)
4
2 0 –2
–4 –6
–4
–3
–2
–1
0
1
Output code
2
3
4 x 104
Fig. 8. INL with the output truncated to 16-bit reconstructed from a code-density test for 64 counting steps without correction of the 2nd-order voltage coefficient.
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6
6
4
4
INL (LSB@16bit)
INL (LSB@16bit)
out to be 0:18%=V 2 for this batch of test chips. The nominal 2nd-order voltage coefficient for the process was 0:13%=V 2 : The case where the voltage-coefficient correction of Eq. (12) was applied is shown in Fig. 9. Here, two cases are distinguished. In the first case, shown in Fig. 9(a), the nominal value of a is used. The resulting INL is within 2 LSB: In the second case, shown in Fig. 9(b), the actual (fitted) value of a is used. The resulting INL is within 1:5 LSB: This case corresponds to what can be expected when the optional (linear) poly2-poly1 capacitors are used. From the same test also the DNL (not shown) was estimated and it was found that the DNL is within 0:8 and þ0:4 LSB in this accuracy mode. The DNL was nearly identical for the cases with or without correction of the capacitor nonlinearity. In the highest accuracy mode with 512 counting steps and a corresponding conversion time of 365 ms; the INL at the 18-bit level was measured as well. It is shown in Fig. 10(a) for the case with the nonlinearity correction of Eq. (12) where the actual value of a was used. Here the INL is within 1:7 LSB: The plot without nonlinearity correction is not shown, but of course in this case the INL is dominated by a 3rd-order nonlinearity leading to an INL within 16 LSB: In the case where the correction is performed with the nominal value of a; the INL is within 4:6 LSB: The DNL is plotted on Fig. 10(b) and is within 0:55 and +0.25 LSB. The DNL plot for the case without correction for the capacitor nonlinearity looks identical.
2 0 –2 –4 –6 –4
–3
–2
–1
(a)
0
1
2
3
Output code
x 10
0 –2 –4 –6 –4
4 4
2
–3
(b)
–2
–1
0
1
4
3
2
Output code
x 104
2
0.3
1.5
0.2
DNL (LSB@18bit)
INL (LSB@18bit)
Fig. 9. INL with the output truncated to 16-bit reconstructed from a code-density test for 64 counting steps with correction of the 2nd-order voltage coefficient (a) with the nominal value of a and (b) with the actual value of a:
1 0.5 0 –0.5 –1 –1.5 –2 –1.5
(a)
0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5
–1
–0.5
0
0.5
Output code
1
–0.6 –1.5
1.5 5
x 10
(b)
–1
–0.5
0
0.5
Output code
1
1.5 5
x 10
Fig. 10. (a) INL and (b) DNL with the output truncated to 18-bit reconstructed from a code-density test for 512 counting steps with correction of the 2nd-order voltage coefficient.
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Analog and digital power consumption of the ADC core were measured separately: 4.4 mW analog and 0.4 mW by the controller, the reconstruction logic and the clock and switch drivers. This makes a total of slightly less than 5 mW in total, independent of the accuracy mode. 6.2. Low-frequency measurements The converter is not intended for applications with rapidly changing input signals. Moreover, as outlined in Section 4, the correction scheme for the capacitor nonlinearity is not very effective for input signals with a variation that is fast compared to the sampling frequency. However, dynamic measurements with relatively slowly varying signals can easily be done. For this purpose a sinusoidal signal was applied at the input of the converter. Fig. 11 shows a typical spectrum (32 K FFT) for the lowest accuracy mode (N count ¼ 64 counting steps) where the converter operates at 20 KS/s. Fig. 11(a) corresponds to the case without correction of the capacitor nonlinearity. The 0:6 dB input signal has a frequency of about 1 KHz. The plot is normalized to full scale. In this figure no 1=f -noise can be observed, which confirms the well-behaved performance of the chopper. As expected, the capacitor nonlinearity causes a pronounced third harmonic ð82:5 dBcÞ: This measurement provides an alternative way to determine the 2nd-order voltage coefficient a of the capacitors. This can be done by fitting a sine wave, that is distorded according to Eq. (11), to the measured data. This procedure was repeated for the 5 available testchips at various supply and reference voltages and in all the implemented accuracy modes. Also here all the measurements gave nearly identical estimations of the 2nd-order voltage coefficient, which was consistent with the static measurement. Fig. 11(b) shows the FFT result for the case where the error correction scheme of Fig. 3 uses the actual (estimated) voltage coefficient. Now the third harmonic is reduced to 107 dBc and does not affect the signal-to-noise (SNR) and distortion ratio which is 91 dB in this case. For the case where the correction is done with the nominal 2nd-order voltage coefficient, the third harmonic becomes 94 dBc and the signal-to-noise and distortion ratio SNDR ¼ 89 dB: Unfortunately, no data on the stability and process variation of the 2nd-order voltagecoefficient are available. Based on our measurements we can already conclude that a deviation of 30% from the nominal value is not impossible. In the lowest accuracy mode of this converter, this would affect the performance of the correction scheme only to a limited extent. Hence, its 0
0 SNR = 91 dB SNDR = 83 dB THD = 83 dB
–40
HD2 (–107 dBc)
–80 –100 –120
–40 –60 –100 –120 –140
–160
–160 0
2
4
6
Frequency (kHz)
8
–180
10
(b)
HD2 HD3 (–107 dBc) (–107 dBc)
–80
–140 –180
(a)
HD3 (-83 dBc)
–60
SNR = 91 dB SNDR = 91 dB THD = 103 dB
–20
Spectrum (dB)
Spectrum (dB)
–20
0
2
4
6
8
10
Frequency (kHz)
Fig. 11. FFT-result in the lowest-accuracy mode (64 counting steps) at 20 kSample=s (a) without and (b) with correction of the 2nd-order voltage coefficient.
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Table 2 ADC dynamic performance in various accuracy modes Number of counting steps N
64
128
256
512
Sampling frequency Peak SNR Peak SNDR Peak SNDR (with correction) DR DR (from short-circuit)
20 kHz 91 dB 86 dB 91 dB 93 dB 95 dB
10.5 kHz 96 dB 89 dB 95 dB 97 dB 100 dB
5.4 kHz 100 dB 92 dB 99 dB 101 dB 106 dB
2.7 kHz 104 dB 96 dB 102 dB 105 dB 110 dB
Table 3 ADC sensitivities to power and common mode voltages Common-mode input voltage range
1.3–2.0 V
CMRR (at 1 kHz)
74 dB
PSRR (at 1 kHz)
95 dB
application even with the nominal coefficient may be a viable alternative over the use of the poly2 option. To determine the dynamic range (DR), the peak SNR and the peak SNDR, a complete set of dynamic measurements was performed for each accuracy mode (number of counting steps) both with and without the nonlinearity correction scheme. All these results are tabulated in Table 2. The dynamic range can also be determined by a measurement with short-circuited inputs. This figure is also mentioned in Table 2. It turns out that it is always larger than the dynamic range from the signal measurement. This difference is attributed in part to noise from the driving amplifiers and in part to kickback from the switched input capacitor to the output of the driving operational amplifier, both of which do not occur in the case of the short-circuit measurement. The short-circuit measurements on the 5 test chips revealed a small systematic offset of +1.6 LSB at 16 bit with a standard deviation of 0.5 LSB at 16 bit, nearly independent of the number of counting steps. The ADCs sensitivities to power and common mode voltages were measured as well and are tabulated in Table 3. 6.3. Rapidly changing input signals For completeness the third harmonic was also measured as a function of the input frequency. This was done by applying a sine wave with an amplitude of 0:3 dB of the full scale at the input of the converter. The amplitude of the residual third harmonic after applying the nonlinearity correction is shown in Fig. 12. The theoretical curve according to Eq. (13) is shown as well. The
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Third harmonic (dB)
–90 Calculated according eq. (13)
–95
–100
–105
–110
1/16
1/8
1/4
1/2
Frequency (1/Fsample)
Fig. 12. Third harmonic vs. fundamental frequency.
plot corresponds to the nominal accuracy mode with 64 counting steps. It is obvious from the figure that the effectiveness of the correction technique decreases for higher input frequencies. For low frequencies the measurement is limited by the accuracy of the distortion of the used (lowdistortion) generator.
7. Conclusion In this paper we have presented a versatile ADC core for sensor readout applications. To achieve a high resolution combined with a Nyquist-rate conversion it employs the extended counting technique [1]. It is shown that this technique is capable of realizing up to 18 bits of resolution. To the authors’ knowledge, this is the highest accuracy that has been reported for an extended counting ADC until now. To achieve this performance without linear capacitors, a nonlinearity correction is required. It is shown that this can be performed by inverting the voltage to charge relationship of the capacitors. This was approximated by a simple third-order correction, which is easily implemented in software on the microcontroller that processes the data. A drawback of this approach is that it requires knowledge of the capacitor’s voltage coefficient. Next to this, the technique is only effective for slowly varying signals, but this is not a limitation for the target applications. If the nonlinearity correction is omitted, the monotonicity (DNL) and noise performance (SNR and DR) of the convertor remain unchanged but its linearity performance (SNDR and INL) is affected.
Acknowledgements The authors wish to thank Ronny Grosfeld, Kenneth Verstraete, Jerome Casters and Rudi De Winter of Melexis for technical discussions and for initiating this design project.
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