Digital-to-Analog and Analog-to-Digital Conversion with Metal Oxide ...
Digital-to-Analog and Analog-to-Digital Conversion with Metal Oxide Memristors for Ultra-Low Power Computing Ligang Gao, Farnood Merrikh-Bayat, Fabien Alibart, Xinjie Guo, Brian D. Hoskins, Kwang-Ting Cheng, and Dmitri B. Strukov Department of Electrical and Computer Engineering University of California Santa Barbara Santa Barbara, CA 93106, USA
I.
INTRODUCTION
Analog computing presents an attractive alternative for data processing that demands extraordinary energy efficiency. However, as pure analog circuits cannot address the noise accumulation problem, a practical solution would require inclusion of analog-to-digital and digital-to-analog stages for signal restoration [1]. Highly energy-efficient data converters are therefore expected to play an important role in future computing platforms and thus new ways of implementing compact and ultra-low-energy data converters are therefore of significant relevance. One promising technology particularly suited for analog computing is the hybrid circuits which integrate CMOS and memristor devices [2-5]. Memristors are essentially twoterminal thin-film devices whose resistances can be tuned in a nonvolatile and analog way [6-15]. In the context of analog circuit applications, recent advances in memristive devices and their integration with CMOS enable efficient implementations of nanoscale analog-grade resistive elements which can be fine-tuned after fabrication [16]. In this paper, we demonstrate binary-weighted DAC and Hopfield-network ADC circuits which utilize the feature of post-fabrication resistance tuning for achieving energy-efficient conversion. II.
MEMRISTIVE DEVICES
Fig. 1 shows typical I-V characteristics of TiO2-x memristive devices, which are obtained by a quasi-DC
(b) -3
10
RESET
SET
-4
10
-5
10
S
Pt V V
TiO2
-6
10
A
Pt
-7
10
-0.5
0.0
0.5
1.0
1.5
Voltage (V) Figure 1. (a) Typical I-V showing analog resistive switching characteristics of Pt/TiO2-x/Pt memristive device. The inset shows schematically device structure. (b) Wire-bonded TiO2-x memristive device in a 40-pin package.
(a)
(b)
100
top electrode
20 nm
bottom electrode 200 nm
50 nm
Working devices (%)
Keywords— ReRAM; memristor; Digital-to-analog conversion; Analog-to-digital conversion; Hopfield neural network; hybrid circuits
(a) Current (A)
Abstract— The paper presents experimental demonstration of 6-bit digital-to-analog (DAC) and 4-bit analog-to-digital conversion (ADC) operations implemented with a hybrid circuit consisting of Pt/TiO2-x/Pt resistive switching devices (also known as ReRAMs or memristors) and a Si operational amplifier (opamp). In particular, a binary-weighted implementation is demonstrated for DAC, while ADC is implemented with a Hopfield neural network circuit.
80 60 40 20 0
no protrusion 35 nm
Figure 2. (a) TEM images of 50-nm-thick titanium dioxide devices with e-beam defined protrusion and (b) a yield comparison between no protrusion and 35nm-long protrusion devices.
1.8
2-4/R
1.5
2-3/R
V3
2-2/R
V2
2-1/R
V1
Rf +
Vout
Op-amp
0
2 /R
V0
1.2 0.9
BINARY-WEIGHTED DAC
Fig. 3 shows a schematic diagram of a 6-bit DAC following a binary-weighted style. The circuit consists of 6 memristors and an op-amp with a negative feedback resistor Rf. For a set of digital input voltages Vi (where i is from 0 to 5) the analog output voltage Vout can be expressed as -Rf/R×∑i2i Vi, when the ith memristor is tuned to a state with a conductance of 2-i/R. The circuit is implemented with a discrete integrated circuit (IC) op-amp (ST TL074) and a packaged memristor chip wired manually on a breadboard. During the programming stage, memristors are set to the desired states with high precision (~1% error) with the help of automated feedback-based algorithm [16] using relatively large programming voltages |V| > 0.5V whereas input voltage is always limited to 0.2V during operation which has been shown to cause negligible drift to the state in the considered memristors [16]. The experimental results for a 6-bit DAC are shown in Fig. 4, and its differential nonlinearity (< 0.11 LSB) and integral nonlinearity (< 0.17 LSB) characteristics are shown in Figs. 5a and b, respectively. Because of the quasiDC testing condition, the main contributing factor to the nonlinearity is proven to be random telegraph noise [6, 17-20] in the high resistance states (Fig. 6).
0.00 0
1
2
3
4
Input code
5
6
experimental result
0
10
20
30
40
50
60
Input code Figure 4. Measured transfer characteristics of a 6-bit DAC as a function of input code. The voltage step (= 26mV) can be seen clearly in the inset of the figure.
(a) DNL [LSB]
0.1
0.0
-0.1 0
(b)
10
20
10
20
30
40
50
60
30
40
50
60
0.1
INL [LSB]
III.
0.09
0.6
0.0
triangular voltage sweep from 0 to 1.5V followed by a quasiDC triangular current sweep from 0 to -1mA. The device structure and fabrication methods are similar to the ones described in Ref. [16]. Additionally, nanoscale metallic protrusion has been implemented in each device in order to localize the switching region (Fig. 2a). This technique, while not required for truly nanoscale devices, helps improve the yield (from about 60% for the blanket film devices to 95%+ for devices with protrusion, as shown in Fig. 2b) and significantly lower the variations in their switching behaviors.
0.18
0.3
Digital Input Figure 3. A schematics of 6-bit binary-weighted digital-toanalog converter implemented with hybrid circuits. Memristors are programmed to have conductances (at 0.2V) 40µS, 80µS, 160µS, 320µS, 640µS, and 1280µS. The circuit utilizes op-amp (with the feedback resistor Rf = 3.3k) to form the weighted sum of all input pulses applied to memristors.
Amplitude (V)
V4
2-5/R
Amplitude (V)
V5
0.0 -0.1 -0.2 0
Input code Figure 5. (a) The differential nonlinearity (DNL) and (b) integral nonlinearity (INL) measured in least significant bits (LSB) as a function of input code for a 6-bit DAC. IV.
HOPFIELD NETWORK ADC
A 4-bit ADC implemented with a Hopfield neural network is shown schematically in Fig. 7a [21]. It consists of four inverting amplifiers (neurons), each of which is made with three IC op-amps (Fig. 7b), and a 46 memristor crossbar which defines the connectivity among neurons (and bias). The weights of recurrent part of the network, represented by the conductances of memristors which are listed in Fig. 8, are symmetrical with zero entries in the principal diagonal and Tij=2(i+j) otherwise, whereas the weights which are serving bias the voltage VR are TjR =2(2j-1). The analog input VS is supplied
Variation (%) Variation (%)
0.4
(a)
256 A @ 0.2V
0.3 0.2 0.1 0.0
0
200
400
4
600
800
1000
T1R
T2S
T2R
T3S
8 A @ 0.2V
2
T1S
T4S VS (Input)
0
T21 T12
T3R
T13
T4R
T31
T41
T32
T42
V1
2
V2
3
V3
4
V4
T43
T23
T14
1
T24
T34
VR (Ref.)
-2
(b)
-4 0
200
400
600
800
1000
R1
:
Time (s)
+
NMOS R1
+
R2
R3 +
(c)
Figure 6. Variations in resistance measurements due to random telegraph noise for a particular resistance states. via fixed IC resistors of weight 2j [21]. In other words, each neuron gets its input as a weighted sum of three different set of signals: reference bias VR, the analog input voltage VS, and four ADC circuit outputs, i.e. V1 through V4. Fig. 9a shows the measured output voltage for a quasi-DC sweep of input VS from 0 to 3.7V, while Fig. 9b shows the corresponding binary output code. In order to achieve a properly functional circuit, all neurons are reset periodically to ‘zero’, which helps avoid getting stuck in local minima. Additionally, non-ideal behaviors of neurons (most importantly the offset voltage in op-amps) are compensated by fine-tuning bias weights. V.
SUMMARY
We have experimentally demonstrated hybrid circuit implementation of DAC and ADC. The demonstrated work is a proof of concept for using memristors as high-precision weights in conversion circuits. At least for relatively lowprecision (< 8 bit) data processing the considered approach could be very compact and energy efficient due to high density of analog weights implemented with memristive devices.
Figure 7. (a) Schematics of Hopfield neural network-based ADC. (b) An op-amp based neuron circuit. (c) A photo of a breadboard experimental setup. [4]
AKCNOWLEDGEMNT This work is supported by AFOSR under MURI grant FA9550-12-1-0038 and NSF grant CCF-1028336.
[5]
[6]
REFERENCES [1]
[2] [3]
R. Sarpeshkar, "Analog versus digital: Extrapolating from electronics to neurobiology," Neural Computation, vol. 10, pp. 1601-1638, Oct 1 1998. J. J. Yang, D. B. Strukov, and D. R. Stewart, "Memristive devices for computing," Nature Nanotechnology, vol. 8, pp. 13-24, Jan 2013. R. Waser, Nanoelectronics & Information Technology, 3 rd Ed, Wiley, 2012.
[7]
[8]
D. B. Strukov and R. S. Williams, "Four-dimensional address topology for circuits with stacked multilayer crossbar arrays," Proceedings of the National Academy of Sciences of the United States of America, vol. 106, pp. 20155-20158, Dec 1 2009. K. K. Likharev, "Hybrid CMOS/Nanoelectronic Circuits: Opportunities and Challenges," Journal of Nanoelectronics and Optoelectronics, vol. 3, pp. 203-230, Dec 2008. L. Gao, F. Alibart, and D. B. Strukov, "Analog-input analog-weight dotproduct operation with Ag/a-Si/Pt memristive devices," VLSI and System-on-Chip (VLSI-SoC), 2012 IEEE/IFIP 20th International Conference on, p. 6, Oct. 2012 2012. L. Gao, F. Alibart, and D. B. Strukov, "Programmable CMOS/Memristor Threshold Logic," IEEE Transactions on Nanotechnology, vol. 12, pp. 115-119, 2013. S. Shin, K. Kim, and S. M. Kang, "Memristor Applications for Programmable Analog ICs," IEEE Transactions on Nanotechnology, vol. 10, pp. 266-274, Mar 2011.
[9]
[10]
[11]
[12]
[13]
[14] [15]
[16]
[17]
[18]
Y. V. Pershin and M. Di Ventra, "Practical Approach to Programmable Analog Circuits With Memristors," IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 57, pp. 1857-1864, Aug 2010. S. M. Yu, Y. Wu, R. Jeyasingh, D. G. Kuzum, and H. S. P. Wong, "An Electronic Synapse Device Based on Metal Oxide Resistive Switching Memory for Neuromorphic Computation," IEEE Transactions on Electron Devices, vol. 58, pp. 2729-2737, Aug 2011. K. Seo, I. Kim, S. Jung, M. Jo, S. Park, J. Park, J. Shin, K. P. Biju, J. Kong, K. Lee, B. Lee, and H. Hwang, "Analog memory and spiketiming-dependent plasticity characteristics of a nanoscale titanium oxide bilayer resistive switching device," Nanotechnology, vol. 22, Jun 24 2011. S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu, "Nanoscale Memristor Device as Synapse in Neuromorphic Systems," Nano Letters, vol. 10, pp. 1297-1301, Apr 2010. T. Chang, S. H. Jo, K. H. Kim, P. Sheridan, S. Gaba, and W. Lu, "Synaptic behaviors and modeling of a metal oxide memristive device," Applied Physics A-Materials Science & Processing, vol. 102, pp. 857863, Mar 2011. G. S. Snider, "Self-organized computation with unreliable, memristive nanodevices," Nanotechnology, vol. 18, Sep 12 2007. T. A. Wey and W. D. Jemison, "Variable gain amplifier circuit using titanium dioxide memristors," IET Circuits Devices & Systems, vol. 5, pp. 59-65, Jan 2011. F. Alibart, L. Gao, B. D. Hoskins, and D. B. Strukov, "High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm," Nanotechnology, vol. 23, Feb 24 2012. D. Lee, J. Lee, M. Jo, J. Park, M. Siddik, and H. Hwang, "NoiseAnalysis-Based Model of Filamentary Switching ReRAM With ZrOx/HfOx Stacks," IEEE Electron Device Letters, vol. 32, pp. 964-966, Jul 2011. Y.-H. Tseng, S. Wen Chao, H. Chia-En, L. Chrong-Jung, and K. YaChin, "Electron trapping effect on the switching behavior of contact RRAM devices through random telegraph noise analysis," in Electron
V1
0.0 -0.1
-0.1
-0.1
-0.1
-0.2 0.0 -0.2 0.0 -0.2 0.0 -0.2 0.0
0.2
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Time (s)
0.8
1.0
(b) 3.5 3.0 2.5
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
Digital output Analog input
2.0 1.5 1.0 0.5 0.0 0.0
0.2
0.4
0.6
Time (s)
0.8
Digital Code
Figure 8 The conductance values of the memristors used in the ADC circuit. Resistors R1, R2, and R3 are used in the neuron circuit to ensure either a 0 or -0.2V output.
(a)
V2
Conductance ([email protected]) 4.75e-6 2.19e-5 9.33e-5 41.85e-5 Conductance (S) 8.33e-6 1.67e-5 3.33e-5 6.67e-5 Resistance (k) 1 100 2
V3
Reference T1R T2R T3R T4R Input T1S T2S T3S T4S Neuron R1 R2 R3
V4
Conductance ([email protected]) 2e-5 4e-5 7.9e-5 2e-5 7.9e-5 15e-5 4e-5 7.9e-5 30.9e-5 7.9e-5 15e-5 30.9e-5
Voltage (V)
Feedback T21 T31 T41 T12 T32 T42 T13 T23 T43 T14 T24 T34
1.0
Figure 9 (a) Measured output voltage of the ADC circuit and (b) the corresponding digital code as a result of an application of analog input voltage ramp (shown with red in panel b) which is varied from 0 to its maximum value. The outputs of the neurons are periodically reset with a frequency of 80Hz. Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 28.5.128.5.4. [19] D. Ielmini, F. Nardi, and C. Cagli, "Resistance-dependent amplitude of random telegraph-signal noise in resistive switching memories," Applied Physics Letters, vol. 96, Feb 1 2010. [20] M. Terai, Y. Sakotsubo, Y. Saito, S. Kotsuji, and H. Hada, "Effect of bottom electrode of ReRAM with Ta2O5/TiO2 stack on RTN and retention," in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 1-4. [21] D. W. Tank and J. J. Hopfield, "Simple Neural Optimization Networks an A/D Converter, Signal Decision Circuit, and a Linear-Programming Circuit," IEEE Transactions on Circuits and Systems, vol. 33, pp. 533541, May 1986.
I.
INTRODUCTION
Analog computing presents an attractive alternative for data processing that demands extraordinary energy efficiency. However, as pure analog circuits cannot address the noise accumulation problem, a practical solution would require inclusion of analog-to-digital and digital-to-analog stages for signal restoration [1]. Highly energy-efficient data converters are therefore expected to play an important role in future computing platforms and thus new ways of implementing compact and ultra-low-energy data converters are therefore of significant relevance. One promising technology particularly suited for analog computing is the hybrid circuits which integrate CMOS and memristor devices [2-5]. Memristors are essentially twoterminal thin-film devices whose resistances can be tuned in a nonvolatile and analog way [6-15]. In the context of analog circuit applications, recent advances in memristive devices and their integration with CMOS enable efficient implementations of nanoscale analog-grade resistive elements which can be fine-tuned after fabrication [16]. In this paper, we demonstrate binary-weighted DAC and Hopfield-network ADC circuits which utilize the feature of post-fabrication resistance tuning for achieving energy-efficient conversion. II.
MEMRISTIVE DEVICES
Fig. 1 shows typical I-V characteristics of TiO2-x memristive devices, which are obtained by a quasi-DC
(b) -3
10
RESET
SET
-4
10
-5
10
S
Pt V V
TiO2
-6
10
A
Pt
-7
10
-0.5
0.0
0.5
1.0
1.5
Voltage (V) Figure 1. (a) Typical I-V showing analog resistive switching characteristics of Pt/TiO2-x/Pt memristive device. The inset shows schematically device structure. (b) Wire-bonded TiO2-x memristive device in a 40-pin package.
(a)
(b)
100
top electrode
20 nm
bottom electrode 200 nm
50 nm
Working devices (%)
Keywords— ReRAM; memristor; Digital-to-analog conversion; Analog-to-digital conversion; Hopfield neural network; hybrid circuits
(a) Current (A)
Abstract— The paper presents experimental demonstration of 6-bit digital-to-analog (DAC) and 4-bit analog-to-digital conversion (ADC) operations implemented with a hybrid circuit consisting of Pt/TiO2-x/Pt resistive switching devices (also known as ReRAMs or memristors) and a Si operational amplifier (opamp). In particular, a binary-weighted implementation is demonstrated for DAC, while ADC is implemented with a Hopfield neural network circuit.
80 60 40 20 0
no protrusion 35 nm
Figure 2. (a) TEM images of 50-nm-thick titanium dioxide devices with e-beam defined protrusion and (b) a yield comparison between no protrusion and 35nm-long protrusion devices.
1.8
2-4/R
1.5
2-3/R
V3
2-2/R
V2
2-1/R
V1
Rf +
Vout
Op-amp
0
2 /R
V0
1.2 0.9
BINARY-WEIGHTED DAC
Fig. 3 shows a schematic diagram of a 6-bit DAC following a binary-weighted style. The circuit consists of 6 memristors and an op-amp with a negative feedback resistor Rf. For a set of digital input voltages Vi (where i is from 0 to 5) the analog output voltage Vout can be expressed as -Rf/R×∑i2i Vi, when the ith memristor is tuned to a state with a conductance of 2-i/R. The circuit is implemented with a discrete integrated circuit (IC) op-amp (ST TL074) and a packaged memristor chip wired manually on a breadboard. During the programming stage, memristors are set to the desired states with high precision (~1% error) with the help of automated feedback-based algorithm [16] using relatively large programming voltages |V| > 0.5V whereas input voltage is always limited to 0.2V during operation which has been shown to cause negligible drift to the state in the considered memristors [16]. The experimental results for a 6-bit DAC are shown in Fig. 4, and its differential nonlinearity (< 0.11 LSB) and integral nonlinearity (< 0.17 LSB) characteristics are shown in Figs. 5a and b, respectively. Because of the quasiDC testing condition, the main contributing factor to the nonlinearity is proven to be random telegraph noise [6, 17-20] in the high resistance states (Fig. 6).
0.00 0
1
2
3
4
Input code
5
6
experimental result
0
10
20
30
40
50
60
Input code Figure 4. Measured transfer characteristics of a 6-bit DAC as a function of input code. The voltage step (= 26mV) can be seen clearly in the inset of the figure.
(a) DNL [LSB]
0.1
0.0
-0.1 0
(b)
10
20
10
20
30
40
50
60
30
40
50
60
0.1
INL [LSB]
III.
0.09
0.6
0.0
triangular voltage sweep from 0 to 1.5V followed by a quasiDC triangular current sweep from 0 to -1mA. The device structure and fabrication methods are similar to the ones described in Ref. [16]. Additionally, nanoscale metallic protrusion has been implemented in each device in order to localize the switching region (Fig. 2a). This technique, while not required for truly nanoscale devices, helps improve the yield (from about 60% for the blanket film devices to 95%+ for devices with protrusion, as shown in Fig. 2b) and significantly lower the variations in their switching behaviors.
0.18
0.3
Digital Input Figure 3. A schematics of 6-bit binary-weighted digital-toanalog converter implemented with hybrid circuits. Memristors are programmed to have conductances (at 0.2V) 40µS, 80µS, 160µS, 320µS, 640µS, and 1280µS. The circuit utilizes op-amp (with the feedback resistor Rf = 3.3k) to form the weighted sum of all input pulses applied to memristors.
Amplitude (V)
V4
2-5/R
Amplitude (V)
V5
0.0 -0.1 -0.2 0
Input code Figure 5. (a) The differential nonlinearity (DNL) and (b) integral nonlinearity (INL) measured in least significant bits (LSB) as a function of input code for a 6-bit DAC. IV.
HOPFIELD NETWORK ADC
A 4-bit ADC implemented with a Hopfield neural network is shown schematically in Fig. 7a [21]. It consists of four inverting amplifiers (neurons), each of which is made with three IC op-amps (Fig. 7b), and a 46 memristor crossbar which defines the connectivity among neurons (and bias). The weights of recurrent part of the network, represented by the conductances of memristors which are listed in Fig. 8, are symmetrical with zero entries in the principal diagonal and Tij=2(i+j) otherwise, whereas the weights which are serving bias the voltage VR are TjR =2(2j-1). The analog input VS is supplied
Variation (%) Variation (%)
0.4
(a)
256 A @ 0.2V
0.3 0.2 0.1 0.0
0
200
400
4
600
800
1000
T1R
T2S
T2R
T3S
8 A @ 0.2V
2
T1S
T4S VS (Input)
0
T21 T12
T3R
T13
T4R
T31
T41
T32
T42
V1
2
V2
3
V3
4
V4
T43
T23
T14
1
T24
T34
VR (Ref.)
-2
(b)
-4 0
200
400
600
800
1000
R1
:
Time (s)
+
NMOS R1
+
R2
R3 +
(c)
Figure 6. Variations in resistance measurements due to random telegraph noise for a particular resistance states. via fixed IC resistors of weight 2j [21]. In other words, each neuron gets its input as a weighted sum of three different set of signals: reference bias VR, the analog input voltage VS, and four ADC circuit outputs, i.e. V1 through V4. Fig. 9a shows the measured output voltage for a quasi-DC sweep of input VS from 0 to 3.7V, while Fig. 9b shows the corresponding binary output code. In order to achieve a properly functional circuit, all neurons are reset periodically to ‘zero’, which helps avoid getting stuck in local minima. Additionally, non-ideal behaviors of neurons (most importantly the offset voltage in op-amps) are compensated by fine-tuning bias weights. V.
SUMMARY
We have experimentally demonstrated hybrid circuit implementation of DAC and ADC. The demonstrated work is a proof of concept for using memristors as high-precision weights in conversion circuits. At least for relatively lowprecision (< 8 bit) data processing the considered approach could be very compact and energy efficient due to high density of analog weights implemented with memristive devices.
Figure 7. (a) Schematics of Hopfield neural network-based ADC. (b) An op-amp based neuron circuit. (c) A photo of a breadboard experimental setup. [4]
AKCNOWLEDGEMNT This work is supported by AFOSR under MURI grant FA9550-12-1-0038 and NSF grant CCF-1028336.
[5]
[6]
REFERENCES [1]
[2] [3]
R. Sarpeshkar, "Analog versus digital: Extrapolating from electronics to neurobiology," Neural Computation, vol. 10, pp. 1601-1638, Oct 1 1998. J. J. Yang, D. B. Strukov, and D. R. Stewart, "Memristive devices for computing," Nature Nanotechnology, vol. 8, pp. 13-24, Jan 2013. R. Waser, Nanoelectronics & Information Technology, 3 rd Ed, Wiley, 2012.
[7]
[8]
D. B. Strukov and R. S. Williams, "Four-dimensional address topology for circuits with stacked multilayer crossbar arrays," Proceedings of the National Academy of Sciences of the United States of America, vol. 106, pp. 20155-20158, Dec 1 2009. K. K. Likharev, "Hybrid CMOS/Nanoelectronic Circuits: Opportunities and Challenges," Journal of Nanoelectronics and Optoelectronics, vol. 3, pp. 203-230, Dec 2008. L. Gao, F. Alibart, and D. B. Strukov, "Analog-input analog-weight dotproduct operation with Ag/a-Si/Pt memristive devices," VLSI and System-on-Chip (VLSI-SoC), 2012 IEEE/IFIP 20th International Conference on, p. 6, Oct. 2012 2012. L. Gao, F. Alibart, and D. B. Strukov, "Programmable CMOS/Memristor Threshold Logic," IEEE Transactions on Nanotechnology, vol. 12, pp. 115-119, 2013. S. Shin, K. Kim, and S. M. Kang, "Memristor Applications for Programmable Analog ICs," IEEE Transactions on Nanotechnology, vol. 10, pp. 266-274, Mar 2011.
[9]
[10]
[11]
[12]
[13]
[14] [15]
[16]
[17]
[18]
Y. V. Pershin and M. Di Ventra, "Practical Approach to Programmable Analog Circuits With Memristors," IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 57, pp. 1857-1864, Aug 2010. S. M. Yu, Y. Wu, R. Jeyasingh, D. G. Kuzum, and H. S. P. Wong, "An Electronic Synapse Device Based on Metal Oxide Resistive Switching Memory for Neuromorphic Computation," IEEE Transactions on Electron Devices, vol. 58, pp. 2729-2737, Aug 2011. K. Seo, I. Kim, S. Jung, M. Jo, S. Park, J. Park, J. Shin, K. P. Biju, J. Kong, K. Lee, B. Lee, and H. Hwang, "Analog memory and spiketiming-dependent plasticity characteristics of a nanoscale titanium oxide bilayer resistive switching device," Nanotechnology, vol. 22, Jun 24 2011. S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu, "Nanoscale Memristor Device as Synapse in Neuromorphic Systems," Nano Letters, vol. 10, pp. 1297-1301, Apr 2010. T. Chang, S. H. Jo, K. H. Kim, P. Sheridan, S. Gaba, and W. Lu, "Synaptic behaviors and modeling of a metal oxide memristive device," Applied Physics A-Materials Science & Processing, vol. 102, pp. 857863, Mar 2011. G. S. Snider, "Self-organized computation with unreliable, memristive nanodevices," Nanotechnology, vol. 18, Sep 12 2007. T. A. Wey and W. D. Jemison, "Variable gain amplifier circuit using titanium dioxide memristors," IET Circuits Devices & Systems, vol. 5, pp. 59-65, Jan 2011. F. Alibart, L. Gao, B. D. Hoskins, and D. B. Strukov, "High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm," Nanotechnology, vol. 23, Feb 24 2012. D. Lee, J. Lee, M. Jo, J. Park, M. Siddik, and H. Hwang, "NoiseAnalysis-Based Model of Filamentary Switching ReRAM With ZrOx/HfOx Stacks," IEEE Electron Device Letters, vol. 32, pp. 964-966, Jul 2011. Y.-H. Tseng, S. Wen Chao, H. Chia-En, L. Chrong-Jung, and K. YaChin, "Electron trapping effect on the switching behavior of contact RRAM devices through random telegraph noise analysis," in Electron
V1
0.0 -0.1
-0.1
-0.1
-0.1
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Time (s)
0.8
1.0
(b) 3.5 3.0 2.5
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
Digital output Analog input
2.0 1.5 1.0 0.5 0.0 0.0
0.2
0.4
0.6
Time (s)
0.8
Digital Code
Figure 8 The conductance values of the memristors used in the ADC circuit. Resistors R1, R2, and R3 are used in the neuron circuit to ensure either a 0 or -0.2V output.
(a)
V2
Conductance ([email protected]) 4.75e-6 2.19e-5 9.33e-5 41.85e-5 Conductance (S) 8.33e-6 1.67e-5 3.33e-5 6.67e-5 Resistance (k) 1 100 2
V3
Reference T1R T2R T3R T4R Input T1S T2S T3S T4S Neuron R1 R2 R3
V4
Conductance ([email protected]) 2e-5 4e-5 7.9e-5 2e-5 7.9e-5 15e-5 4e-5 7.9e-5 30.9e-5 7.9e-5 15e-5 30.9e-5
Voltage (V)
Feedback T21 T31 T41 T12 T32 T42 T13 T23 T43 T14 T24 T34
1.0
Figure 9 (a) Measured output voltage of the ADC circuit and (b) the corresponding digital code as a result of an application of analog input voltage ramp (shown with red in panel b) which is varied from 0 to its maximum value. The outputs of the neurons are periodically reset with a frequency of 80Hz. Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 28.5.128.5.4. [19] D. Ielmini, F. Nardi, and C. Cagli, "Resistance-dependent amplitude of random telegraph-signal noise in resistive switching memories," Applied Physics Letters, vol. 96, Feb 1 2010. [20] M. Terai, Y. Sakotsubo, Y. Saito, S. Kotsuji, and H. Hada, "Effect of bottom electrode of ReRAM with Ta2O5/TiO2 stack on RTN and retention," in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 1-4. [21] D. W. Tank and J. J. Hopfield, "Simple Neural Optimization Networks an A/D Converter, Signal Decision Circuit, and a Linear-Programming Circuit," IEEE Transactions on Circuits and Systems, vol. 33, pp. 533541, May 1986.
