5% @180
USO05282147A
United States Patent [191
[11] Patent Number:
Goetz et a].
[45]
[54] 7 METHOD AND APPARATUS FOR OPTIMIZING A LOGIC NETWORK
5,197,015 3/1993 Hartoog et al. ................... .. 364/490 5,200,907 4/1993 Tran .................................. .. 364/490
[75] Inventors: John W. Goetz; David J. Hathaway,
Attorney, Agent, or Fzrm-J. Dennis Moore
[73] Assignee: International Business Machines
I57]
Corporation, Armonk, N-Y_
pressing the logic network as an original graph having
vertices, edges which connect the vertices and which represent connections in the logic network, and inver
-
"""""""""""""
U Go“
sion markings for representing inverters in the logic
2489,
""
network; determining a fundamental cycle(s) in the
489’ 490 491
""""""" "
[56]
ABSTRACT
A system for optimizing a logic network including ex
[21] Appl‘ No" 739’923 [22] Filed: Aug. 2, 1991
[58] Fi'elh of:
Jan. 25, 1994
Prima')’ Examiner-‘Vincent N- Tfans
both of Underhil], Vt‘
5
Date of Patent:
5,282,147
’
’
original graph; sorting the determined fundamental
’
cycle(s) according to its parity; forming a ?nal graph by
References Cited
processing the fundamental cycle(s) so as to optimize
Us’ PATENT DOCUMENTS
inverter placement therein while maintaining the parity
_ . 4,566,064 _ 1/1986 Whitaker ........................... .. 364/28?
thereof; companng the ll'lVel'SlOIl markmgs of the origi Hal and ?nal graphs to determme a set of transformation
41:38’??? I l‘éav‘ada e‘ 31' 322,28 1,703,435 10/1987 inglrrriiilgl'e'i'ei'iii'. ............. .1: 364/489
locations in the logic network; and re-con?guring the logic “ctwmk I" accm'dance with the determined trans‘
4:916,627 4/1990 Hathaway .............. .. 364/490 5,003,487 3/1991 Drumm et al 364/489 5,029,102 7/1991 Drumm et a]. ................... .. 364/489
fmmam" mamm 16 Claims, 19 Drawing Sheets
INPUT TOPOLOGY OF NETWORK,LIST OF TIMING
CRITICAL CONNECTIONS, AND CIRCUIT LIBRARY
rvqo
I GENERATE GRAPH WITH VERTICES, EDGES, AND INVERSION MARKINGS
I DETERMINE FUNDAMENTAL CYCLES OF GRAPH
110
I soar FUNDAMENTAL CYCLES INTO THOSE wrru EVEN AND ODD NUMBERS or INVERSION MARKINGSNIzO
I REMOVE INVERSION MARKINGS AND LABEL LIST OF EVEN CYCLES AS CORRECT AND N130 LIST OF ODD CYCLES AS INCORRECT
I40
IS INCORRECT us'r
EMPTY '2
glSO CHOOSE AN INCORRECT CYCLE AND ADD
COMPARE INITIAL AND
INVERSION MARKINGS
MARKINGS TO DETERMINE LOCATIONS AT WHICH TO PERFORM
TO THE GRAPH T0 CORRECT IT
FINAL INVERSION
TRAN SFORMATIONS MOVE ALL CYCLES MADE
CORRECT BY THE ADDED
INVERSION MARKINGS TO THE CORRECT LIST, AND ALL CYCLES MADE INCORRECT TO THE INCORRECT LIST
8760
I APPLY TRANSFORMATIONS
AT DETERMINED LOCATIONS IN THE NETWORK AND ADD AND DELETE INVERTERS TO MATCH FINAL INVERSION MARKINGS
5% @180
US. Patent
w>PmDFDn
United States Patent [191
[11] Patent Number:
Goetz et a].
[45]
[54] 7 METHOD AND APPARATUS FOR OPTIMIZING A LOGIC NETWORK
5,197,015 3/1993 Hartoog et al. ................... .. 364/490 5,200,907 4/1993 Tran .................................. .. 364/490
[75] Inventors: John W. Goetz; David J. Hathaway,
Attorney, Agent, or Fzrm-J. Dennis Moore
[73] Assignee: International Business Machines
I57]
Corporation, Armonk, N-Y_
pressing the logic network as an original graph having
vertices, edges which connect the vertices and which represent connections in the logic network, and inver
-
"""""""""""""
U Go“
sion markings for representing inverters in the logic
2489,
""
network; determining a fundamental cycle(s) in the
489’ 490 491
""""""" "
[56]
ABSTRACT
A system for optimizing a logic network including ex
[21] Appl‘ No" 739’923 [22] Filed: Aug. 2, 1991
[58] Fi'elh of:
Jan. 25, 1994
Prima')’ Examiner-‘Vincent N- Tfans
both of Underhil], Vt‘
5
Date of Patent:
5,282,147
’
’
original graph; sorting the determined fundamental
’
cycle(s) according to its parity; forming a ?nal graph by
References Cited
processing the fundamental cycle(s) so as to optimize
Us’ PATENT DOCUMENTS
inverter placement therein while maintaining the parity
_ . 4,566,064 _ 1/1986 Whitaker ........................... .. 364/28?
thereof; companng the ll'lVel'SlOIl markmgs of the origi Hal and ?nal graphs to determme a set of transformation
41:38’??? I l‘éav‘ada e‘ 31' 322,28 1,703,435 10/1987 inglrrriiilgl'e'i'ei'iii'. ............. .1: 364/489
locations in the logic network; and re-con?guring the logic “ctwmk I" accm'dance with the determined trans‘
4:916,627 4/1990 Hathaway .............. .. 364/490 5,003,487 3/1991 Drumm et al 364/489 5,029,102 7/1991 Drumm et a]. ................... .. 364/489
fmmam" mamm 16 Claims, 19 Drawing Sheets
INPUT TOPOLOGY OF NETWORK,LIST OF TIMING
CRITICAL CONNECTIONS, AND CIRCUIT LIBRARY
rvqo
I GENERATE GRAPH WITH VERTICES, EDGES, AND INVERSION MARKINGS
I DETERMINE FUNDAMENTAL CYCLES OF GRAPH
110
I soar FUNDAMENTAL CYCLES INTO THOSE wrru EVEN AND ODD NUMBERS or INVERSION MARKINGSNIzO
I REMOVE INVERSION MARKINGS AND LABEL LIST OF EVEN CYCLES AS CORRECT AND N130 LIST OF ODD CYCLES AS INCORRECT
I40
IS INCORRECT us'r
EMPTY '2
glSO CHOOSE AN INCORRECT CYCLE AND ADD
COMPARE INITIAL AND
INVERSION MARKINGS
MARKINGS TO DETERMINE LOCATIONS AT WHICH TO PERFORM
TO THE GRAPH T0 CORRECT IT
FINAL INVERSION
TRAN SFORMATIONS MOVE ALL CYCLES MADE
CORRECT BY THE ADDED
INVERSION MARKINGS TO THE CORRECT LIST, AND ALL CYCLES MADE INCORRECT TO THE INCORRECT LIST
8760
I APPLY TRANSFORMATIONS
AT DETERMINED LOCATIONS IN THE NETWORK AND ADD AND DELETE INVERTERS TO MATCH FINAL INVERSION MARKINGS
5% @180
US. Patent
w>PmDFDn
