A 20-MS/S SIGMA DELTA MODULATOR FOR ... - Semantic Scholar
A 20-MS/S SIGMA DELTA MODULATOR FOR 802.11a APPLICATIONS Jen-Shiun Chiang, Yi-Tsung Li, and Hsin-Liang Chen Department of Electrical Engineering Tamkang University Tamsui, Taipei, Taiwan E-mail: [email protected] Abstarct － In this paper, a 20-Msample/sec and 12-bit resolution sigma delta modulator for 802.11a applications is presented. The distributed feedback with a forward input and resonator feedback schemes are utilized to implement this modulator. The fifth-order 3-bit quantizer single-loop sigma delta modulator achieves 20-MS/s conversion ratio with 74dB of dynamic range and 70dB of peak signal-to-noise-distortion ratio. The circuit is implemented in a standard 0.18-µm 1P6M CMOS technology. The core area is 0.77mm2 (1.1mm x 0.7mm) and the power consumption is only 38-mW at 1.8-V supply.
1. INTRODUCTION Wireless local area network (WLAN) provides wideband wireless connectivity between PCs and other consumer electronic devices as well as access to the core network and other equipment in corporate, public, and home environments. The potential application of WLAN is highspeed extension to cellular radio access networks. Ratified in 1999, the IEEE 802.11a [1] operates in the 5-GHz unlicensed national information infrastructure (U-NII) band and is based on orthogonal frequency division multiplexing (OFDM). It supports data rates from 6 to 54 Mb/s. According to the presented papers [2][3], the analog to digital converter needs to have high speed (wide-bandwidth) and high dynamic range. The resolution of 802.11a locates about 10 ~ 12 bits and the needed bandwidth is 10MHz. By using oversampling and noise-shaping techniques, the sigma delta modulator (SDM) typically achieves high dynamic ranges (DR) at the expense of reduced signal bandwidth [4]. Such techniques have been widely used in the audio band applications. Furthermore, the high resolution characteristics attract people to design SDM for wide bandwidth applications [5]. Usually, the oversampling ratio (OSR) must be reduced to increase the signal bandwidth without increasing sampling rate for wide bandwidth applications. However, the resolution of the modulator is proportional to the OSR. Therefore, it is necessary to reduce the in-band quantization noise level and increase the order of the modulator to maintain performance at a reduced OSR [4]. Combining the high order SDM with multi-bit quantization is an effective solution to achieve high dynamic range for wide bandwidth applications. This paper devotes to the design of a wide bandwidth and low power SDM for WLAN communication applications.
The rest of this paper is organized as follows: in Section 2, the system design and simulation are described and the specifications of the system are presented. The implemented circuits are discussed in Section 3. Section 4 illustrates the post process simulation result and layout. Finally, the brief conclusion is shown in Section 5. 2. SYSTEM DESIGN Figure 1 shows the proposed fifth-order 3-bit quantizer single-loop sigma delta modulator. Here, we use the distributed feedback with a forward input and resonator feedback topologies [4]. The addition of input feed-forward paths allows a certain degree of independence in specifying the noise transfer function (NTF) and signal transfer function (STF). In the NTF, the inclusion of the local feedback introduces two pairs of poles in the forward path of the overall loop. It only slightly modifies other integrator gain factors to achieve the same closed-loop transfer function. For the closed-loop transfer function between the quantizer error and the output of this modulator, the poles of the local feedback loops form the transmission zeros that suppress the quantization noise in the pass-band and the edge of the cut-off frequency. To ensure the notches at two poles is as deep as possible; the local loop is implemented with the non-delay integrator [5]. By this arrangement, a pair of zeros exactly locate on the unit circle of the closedloop transfer function. In our design, we use the optimization routine based on the closed-loop analysis of noise-shaper (CLANS) method [6] to achieve the best compromise between stable input and total integrated inband noise.
Figure 1: The schematic of the fifth order single loop sigma delta modulator
0-7803-9390-2/06/$20.00 ©2006 IEEE
1888
ISCAS 2006
For considerations of the non-ideal circuits, we consider the non-ideal sources such as jitter, thermal noise, and nonlinearly finite gain, by Matlab simulation, mathematically. Table 1 lists the ideal case and the individual influence of each non-ideal source altogether. According to the referenced paper [7], the non-ideal sources are modelled and simulated. The circuit specifications can be defined by the simulation results shown in Figures 2, 3, and 4(a). Figure 4(b) shows the mathematical model of the nonlinear finite gain. It is a second order polynomial to approach the real linear characteristic. Due to the high sampling rate of this system, the influence of the jitter is significant. The jitter influence reduces the signal-to-noisedistortion ratio (SNDR) 5dB. Therefore, the design of the clock generator is very important. Table 1 Influences of the non-idealities Modulator Paramet
SNDRpeak
Ideal modulator
80.6
Sampling jitter (50ps)
75.26
Thermal noise (0.8pF)
77.04
Finite DC gain (800)
79.97
Total
73.62
Figure 4: (a) SNDR vs. nonlinearly finite gain. (b) Mathematical model of the nonlinear opamp.
3. CIRCUIT IMPLEMENTATION The modulator is implemented by the SC technique. Figure 5 shows the input stage (the 1st integrator) and the feedback D/A converter (DAC). The DAC feedback voltages (rfp1 to rfp4 and rfn1 to rfn4) and the four unit capacitors on each input of the integrator are used to generate a nine-level DAC.
Figure 5: Schematic of the input stage
Figure 2: SNDR vs. jitter
The feed-forward summing node path at the input of the quantizer is realized by differential SC comparators of a 3bit quantizer. The 3-bit quantizer combines the SC summation without op-amp in order to reduce the power consumption, as shown in Figure 6 [8]. However, the SC summation makes the input signal of quantizer loss a gain of 4. Accordingly, comparators with higher resolution are necessary.
Figure 6: The 3-bit quantizer combines with SC summation Figure 3: SNDR vs. KT/C
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Here, a fully differential telescopic amplifier [9] is used for the fifth-order SDM. Although the telescopic amplifier suffers from lower output swing, it potentially has less noise (because it has fewer transistors) and lower power than other architectures. The gain of a telescopic amplifier is approximately: (1)
gmn ⋅ ( gmn ⋅ ron ⋅ ron ) ( gmp ⋅ rop ⋅ rop ).
The telescopic amplifier requires a minimum of 5 overdrive voltages (Vov) for the devices to stay in saturation. A high dynamic range requires a large output swing and a low output noise. Therefore, we need large Vov transistors in the current source and small Vov transistors in the input. We can increase the channel length of the device to get a larger output resistance for higher DC gain. Although the circuit needs minimum channel length for the input transistors to keep the CGS of the input transistors small to have a large feedback factor (to lower the output noise), the channel lengths of the input transistors are selected to be 0.3µm due to gain requirement. The tail current transistor is sized to have small Vov to maximize the output swing. Minimum channel length is used in the tail current source to maximize the feedback factor. Another main consideration is noise. To minimize the noise, we need to minimize the noise factor. Noises from the cascode devices are not significant. PMOS current sources contribute significantly to the total noise, and the noise is proportional to (1 + gmp/gm1). Therefore, Vov of the PMOS current source is designed to be 200mV, which is more than triple that of the input transistors to lower the noise factor. The circuit of the fully differential telescopic amplifier is shown in Figure 7. The key performance parameters of the op-amp are summarized in Table 2.
The switched-capacitor circuits and quantizers require various clock signals, and these signals are generated on chip from the main external clock signal. The switchedcapacitor circuit requires two non-overlapping clocks for the sampling and integration phases. Some switches must be controlled by signals with a delayed falling edge to avoid signal dependent charge injection. Therefore, a delayed falling edge signal is also required. Finally, one more clock signal ck1a is needed in the comparator to ensure the correct timing of the feedback signals [10]. 4. SIMULATION RESULTS The fifth order sigma delta modulator was designed in a one-poly six-metal 0.18-µm CMOS MIM process. The chip area with bounding pads is 1.4 X 1.05 mm2. The floor plan is arranged by the mixed-mode layout rule. The analog and digital circuits are separated by a capacitor array, and independent power lines are used to avoid cross couple noise. Each analog component is protected by guard ring in order to prevent the noise injection from the substrate. The layout of the modulator is shown in Figure 9. The SDM is operated with sampling rate 160-MHz to achieve a 10-MHz signal bandwidth. The peak SNDR is 70dB, and the dynamic range is 74dB. Figure 10 shows the output spectrum. Simulation results for SNDR vs. input amplitude are shown in Figure 11. The power dissipation of the whole sigma delta modulator is about 38-mW. Table 3 summarizes the overall performance. Table 4 shows the Figure-of-Merit (FOM) parameter of the SDM [5, 11, 12]. The FOM equation is given as follows: FOM =
Power (W ) ×1012 ( pJ ), 2 ⋅ (2 f BW ) ENOB
where Power(W) denotes the power consumption of the modulator in Watt; fBW is the modulator bandwidth in Hz, and the equivalent number of bits (ENOB) is related to the SNRmax according to the formula SNRmax ≅ 6.02 × ENOB + 1.76 (dB).
Figure 7: The schematic of the telescopic OTA Table 2: Performance summary of the telescopic OTA Specification
OTA
Corner
SS ( 75ºC)
TT (25ºC)
FF (0ºC)
DC Gain
58.3 dB
58.02 dB
55 dB
GBW (CL=1.5p)
0.83 GHz
1.06 GHz
1.31 GHz
SR (CL=1.5p)
306 V/us
357 V/us
418 V/us
Phase Margin
71.6∘
72∘
72∘
Maximum Current
1.94-mA
2.16-mA
2.46-mA
Power
4-mW
4.47-mW
5.08-mW
(2)
Figure 9: VLSI layout of the modulator
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hand sets and mobile equipments. This work proposes a low power SDM for 802.11a applications. The power consumption is only 38mW and the wide DR is 74dB. The test chip is designed and fabricated by the standard 0.18-µm 1P6M CMOS technology with 0.77mm2 (1.1mm x 0.7mm) of the core area at 1.8-V supply. It is very suitable to be utilized in the receiver of the 802.11a applications. ACKNOWLEDGEMENTS This work is supported by National Science Council of Taiwan, ROC, under grant number NSC 93-2215-E-032001-. The authors would like to thank the Chip Implementation Center (CIC) of Taiwan for the design and implementation support of analog-digital integrated circuits.
Figure 10: Output spectrum of the modulator (post layout simulation)
REFERENCES [1] “Information Technology - Telecommunications and Information Exchange Between Systems - Local and Metropolitan Area Networks Specific Requirements. Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications,” ISO/IEC 8802-11, ANSI/IEEE Std 802.11, 20 Aug. 1999. [2] J. Thomson, B. Baas, E. M. Cooper, J. M. Gilbert, G. Hsieh, P. Husted, A. Lokanathan, J. S. Kuskin, D. McCracken, B. McFarland, T. H. Meng, D. Nakahira, S. Ng, M. Rattehalli, J. L. Smith, R. Subramanian, L. Thon, Y. H. Wang, R. Yu, and Z. Xiaoru. “An Integrated 802.11a Baseband and MAC Processor,” IEEE International Solid-State Circuits Conference, ISSCC, vol. 4, Feb. 2002. [3] S. Ray, P. Tadeparthy, S. S. Rath, D. B. Lavanmoorthy, C. P. S. Sujit, and S. Mathur, “A Low Power 10 Bit 80 MSPS Pipelined ADC in Digital CMOS Process,” IEEE MWSCAS Circuits and Systems, vol. 1, pp. 579582, Aug. 2002.
Figure 11: The dynamic range of the modulator Table 3: Performance summary Specifications
Value
Sampling rate
160 MHz
OSR
8
Signal bandwidth
10 MHz
Peak SNDR
70 dB
Dynamic Range
74 dB
[4] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation, New York: IEEE Press, 1996. [5] P. Balmelli and Q. Huang, “A 25MS/s 14b 200mW Sigma Delta Modulator in 0.18um CMOS,” IEEE International Solid-State Circuits Conference, ISSCC, vol. 4, 2004. [6] J. G. Kenney and L. R. Carley, “Design of Multibit Noise-Shaping Data Converters,” Analog Integrated Circuits Signal Processing Journal, vol. 3, pp. 259-272, 1993. [7] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato, and A. Baschirotto, “Behavioral Modeling of Switched-Capacitor Sigma Delta Modulators,” IEEE Trans. Circuits Syst. I, vol. 50, pp. 352–364, Mar. 2003.
Power consumption
38 mW
Active Area
1.4×1.05 mm2, 1.8-V
Process
TSMC 1P6M 0.18um CMOS
[8] R. Gaggl, M. Inversi and A. Wiesbauer, “A Power Optimized 14-Bit SC Delta Digma Modulator for ADSL CO Applications,” IEEE International Solid-State Circuits Conference, ISSCC, vol. 4, 2004. [9] K. Gulati and H. S. Lee, “A High-Swing COMS Telescopic Operational Amplifier,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2010-2019, Dec. 1998.
Table 3: Sigma delta modulator performance comparisons ENOB
fBW
Process
(Bit) (MHz)
Power FOM
Park 03
14.5
2.5
0.35µm-5V
495
4.2
Geerts 00
12.5
6.25
0.65µm-5V
380
5.2
Balmelli 04
14
12.5 0.18µm-1.8V 200
0.49
This work
12
10
[10] A. Marques, V. Peluso, M. Steyaert, and W. Sansen, “A 15-b Resolution 2MHz Nyquist Rate Delta Sigma ADC in a 1-um COMS Technology,” IEEE Journal of Solid-state Circuits, vol. 33, no. 7, pp. 10651075, July 1998.
(mW) (pJ)
0.18µm-1.8V
38
[11] Y.-In Park; S. Karthikeyan, M. K. Wern, J. Zhongnong, and T.-C. Tan, “A 16-bit, 5-MHz Multi-Bit Sigma-Delta ADC Using Adaptively Randmoized DWA,” in Proc. IEEE Custom Integrated Circ. Conf., pp. 7-21–7-2-4, Sept. 2003.
0.46
5. CONCLUSION In the wide bandwidth applications, the power consumption is a critical point of the circuit design for the
[12] Y. Geerts, M. J. Steyaert, and W. Sansen, “A High-Performance Multibit Delta Sigma CMOS ADC,” IEEE J. Solid-State Circuits, vol. 35, pp. 1829–1840, Dec. 2000.
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1. INTRODUCTION Wireless local area network (WLAN) provides wideband wireless connectivity between PCs and other consumer electronic devices as well as access to the core network and other equipment in corporate, public, and home environments. The potential application of WLAN is highspeed extension to cellular radio access networks. Ratified in 1999, the IEEE 802.11a [1] operates in the 5-GHz unlicensed national information infrastructure (U-NII) band and is based on orthogonal frequency division multiplexing (OFDM). It supports data rates from 6 to 54 Mb/s. According to the presented papers [2][3], the analog to digital converter needs to have high speed (wide-bandwidth) and high dynamic range. The resolution of 802.11a locates about 10 ~ 12 bits and the needed bandwidth is 10MHz. By using oversampling and noise-shaping techniques, the sigma delta modulator (SDM) typically achieves high dynamic ranges (DR) at the expense of reduced signal bandwidth [4]. Such techniques have been widely used in the audio band applications. Furthermore, the high resolution characteristics attract people to design SDM for wide bandwidth applications [5]. Usually, the oversampling ratio (OSR) must be reduced to increase the signal bandwidth without increasing sampling rate for wide bandwidth applications. However, the resolution of the modulator is proportional to the OSR. Therefore, it is necessary to reduce the in-band quantization noise level and increase the order of the modulator to maintain performance at a reduced OSR [4]. Combining the high order SDM with multi-bit quantization is an effective solution to achieve high dynamic range for wide bandwidth applications. This paper devotes to the design of a wide bandwidth and low power SDM for WLAN communication applications.
The rest of this paper is organized as follows: in Section 2, the system design and simulation are described and the specifications of the system are presented. The implemented circuits are discussed in Section 3. Section 4 illustrates the post process simulation result and layout. Finally, the brief conclusion is shown in Section 5. 2. SYSTEM DESIGN Figure 1 shows the proposed fifth-order 3-bit quantizer single-loop sigma delta modulator. Here, we use the distributed feedback with a forward input and resonator feedback topologies [4]. The addition of input feed-forward paths allows a certain degree of independence in specifying the noise transfer function (NTF) and signal transfer function (STF). In the NTF, the inclusion of the local feedback introduces two pairs of poles in the forward path of the overall loop. It only slightly modifies other integrator gain factors to achieve the same closed-loop transfer function. For the closed-loop transfer function between the quantizer error and the output of this modulator, the poles of the local feedback loops form the transmission zeros that suppress the quantization noise in the pass-band and the edge of the cut-off frequency. To ensure the notches at two poles is as deep as possible; the local loop is implemented with the non-delay integrator [5]. By this arrangement, a pair of zeros exactly locate on the unit circle of the closedloop transfer function. In our design, we use the optimization routine based on the closed-loop analysis of noise-shaper (CLANS) method [6] to achieve the best compromise between stable input and total integrated inband noise.
Figure 1: The schematic of the fifth order single loop sigma delta modulator
0-7803-9390-2/06/$20.00 ©2006 IEEE
1888
ISCAS 2006
For considerations of the non-ideal circuits, we consider the non-ideal sources such as jitter, thermal noise, and nonlinearly finite gain, by Matlab simulation, mathematically. Table 1 lists the ideal case and the individual influence of each non-ideal source altogether. According to the referenced paper [7], the non-ideal sources are modelled and simulated. The circuit specifications can be defined by the simulation results shown in Figures 2, 3, and 4(a). Figure 4(b) shows the mathematical model of the nonlinear finite gain. It is a second order polynomial to approach the real linear characteristic. Due to the high sampling rate of this system, the influence of the jitter is significant. The jitter influence reduces the signal-to-noisedistortion ratio (SNDR) 5dB. Therefore, the design of the clock generator is very important. Table 1 Influences of the non-idealities Modulator Paramet
SNDRpeak
Ideal modulator
80.6
Sampling jitter (50ps)
75.26
Thermal noise (0.8pF)
77.04
Finite DC gain (800)
79.97
Total
73.62
Figure 4: (a) SNDR vs. nonlinearly finite gain. (b) Mathematical model of the nonlinear opamp.
3. CIRCUIT IMPLEMENTATION The modulator is implemented by the SC technique. Figure 5 shows the input stage (the 1st integrator) and the feedback D/A converter (DAC). The DAC feedback voltages (rfp1 to rfp4 and rfn1 to rfn4) and the four unit capacitors on each input of the integrator are used to generate a nine-level DAC.
Figure 5: Schematic of the input stage
Figure 2: SNDR vs. jitter
The feed-forward summing node path at the input of the quantizer is realized by differential SC comparators of a 3bit quantizer. The 3-bit quantizer combines the SC summation without op-amp in order to reduce the power consumption, as shown in Figure 6 [8]. However, the SC summation makes the input signal of quantizer loss a gain of 4. Accordingly, comparators with higher resolution are necessary.
Figure 6: The 3-bit quantizer combines with SC summation Figure 3: SNDR vs. KT/C
1889
Here, a fully differential telescopic amplifier [9] is used for the fifth-order SDM. Although the telescopic amplifier suffers from lower output swing, it potentially has less noise (because it has fewer transistors) and lower power than other architectures. The gain of a telescopic amplifier is approximately: (1)
gmn ⋅ ( gmn ⋅ ron ⋅ ron ) ( gmp ⋅ rop ⋅ rop ).
The telescopic amplifier requires a minimum of 5 overdrive voltages (Vov) for the devices to stay in saturation. A high dynamic range requires a large output swing and a low output noise. Therefore, we need large Vov transistors in the current source and small Vov transistors in the input. We can increase the channel length of the device to get a larger output resistance for higher DC gain. Although the circuit needs minimum channel length for the input transistors to keep the CGS of the input transistors small to have a large feedback factor (to lower the output noise), the channel lengths of the input transistors are selected to be 0.3µm due to gain requirement. The tail current transistor is sized to have small Vov to maximize the output swing. Minimum channel length is used in the tail current source to maximize the feedback factor. Another main consideration is noise. To minimize the noise, we need to minimize the noise factor. Noises from the cascode devices are not significant. PMOS current sources contribute significantly to the total noise, and the noise is proportional to (1 + gmp/gm1). Therefore, Vov of the PMOS current source is designed to be 200mV, which is more than triple that of the input transistors to lower the noise factor. The circuit of the fully differential telescopic amplifier is shown in Figure 7. The key performance parameters of the op-amp are summarized in Table 2.
The switched-capacitor circuits and quantizers require various clock signals, and these signals are generated on chip from the main external clock signal. The switchedcapacitor circuit requires two non-overlapping clocks for the sampling and integration phases. Some switches must be controlled by signals with a delayed falling edge to avoid signal dependent charge injection. Therefore, a delayed falling edge signal is also required. Finally, one more clock signal ck1a is needed in the comparator to ensure the correct timing of the feedback signals [10]. 4. SIMULATION RESULTS The fifth order sigma delta modulator was designed in a one-poly six-metal 0.18-µm CMOS MIM process. The chip area with bounding pads is 1.4 X 1.05 mm2. The floor plan is arranged by the mixed-mode layout rule. The analog and digital circuits are separated by a capacitor array, and independent power lines are used to avoid cross couple noise. Each analog component is protected by guard ring in order to prevent the noise injection from the substrate. The layout of the modulator is shown in Figure 9. The SDM is operated with sampling rate 160-MHz to achieve a 10-MHz signal bandwidth. The peak SNDR is 70dB, and the dynamic range is 74dB. Figure 10 shows the output spectrum. Simulation results for SNDR vs. input amplitude are shown in Figure 11. The power dissipation of the whole sigma delta modulator is about 38-mW. Table 3 summarizes the overall performance. Table 4 shows the Figure-of-Merit (FOM) parameter of the SDM [5, 11, 12]. The FOM equation is given as follows: FOM =
Power (W ) ×1012 ( pJ ), 2 ⋅ (2 f BW ) ENOB
where Power(W) denotes the power consumption of the modulator in Watt; fBW is the modulator bandwidth in Hz, and the equivalent number of bits (ENOB) is related to the SNRmax according to the formula SNRmax ≅ 6.02 × ENOB + 1.76 (dB).
Figure 7: The schematic of the telescopic OTA Table 2: Performance summary of the telescopic OTA Specification
OTA
Corner
SS ( 75ºC)
TT (25ºC)
FF (0ºC)
DC Gain
58.3 dB
58.02 dB
55 dB
GBW (CL=1.5p)
0.83 GHz
1.06 GHz
1.31 GHz
SR (CL=1.5p)
306 V/us
357 V/us
418 V/us
Phase Margin
71.6∘
72∘
72∘
Maximum Current
1.94-mA
2.16-mA
2.46-mA
Power
4-mW
4.47-mW
5.08-mW
(2)
Figure 9: VLSI layout of the modulator
1890
hand sets and mobile equipments. This work proposes a low power SDM for 802.11a applications. The power consumption is only 38mW and the wide DR is 74dB. The test chip is designed and fabricated by the standard 0.18-µm 1P6M CMOS technology with 0.77mm2 (1.1mm x 0.7mm) of the core area at 1.8-V supply. It is very suitable to be utilized in the receiver of the 802.11a applications. ACKNOWLEDGEMENTS This work is supported by National Science Council of Taiwan, ROC, under grant number NSC 93-2215-E-032001-. The authors would like to thank the Chip Implementation Center (CIC) of Taiwan for the design and implementation support of analog-digital integrated circuits.
Figure 10: Output spectrum of the modulator (post layout simulation)
REFERENCES [1] “Information Technology - Telecommunications and Information Exchange Between Systems - Local and Metropolitan Area Networks Specific Requirements. Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications,” ISO/IEC 8802-11, ANSI/IEEE Std 802.11, 20 Aug. 1999. [2] J. Thomson, B. Baas, E. M. Cooper, J. M. Gilbert, G. Hsieh, P. Husted, A. Lokanathan, J. S. Kuskin, D. McCracken, B. McFarland, T. H. Meng, D. Nakahira, S. Ng, M. Rattehalli, J. L. Smith, R. Subramanian, L. Thon, Y. H. Wang, R. Yu, and Z. Xiaoru. “An Integrated 802.11a Baseband and MAC Processor,” IEEE International Solid-State Circuits Conference, ISSCC, vol. 4, Feb. 2002. [3] S. Ray, P. Tadeparthy, S. S. Rath, D. B. Lavanmoorthy, C. P. S. Sujit, and S. Mathur, “A Low Power 10 Bit 80 MSPS Pipelined ADC in Digital CMOS Process,” IEEE MWSCAS Circuits and Systems, vol. 1, pp. 579582, Aug. 2002.
Figure 11: The dynamic range of the modulator Table 3: Performance summary Specifications
Value
Sampling rate
160 MHz
OSR
8
Signal bandwidth
10 MHz
Peak SNDR
70 dB
Dynamic Range
74 dB
[4] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters: Theory, Design, and Simulation, New York: IEEE Press, 1996. [5] P. Balmelli and Q. Huang, “A 25MS/s 14b 200mW Sigma Delta Modulator in 0.18um CMOS,” IEEE International Solid-State Circuits Conference, ISSCC, vol. 4, 2004. [6] J. G. Kenney and L. R. Carley, “Design of Multibit Noise-Shaping Data Converters,” Analog Integrated Circuits Signal Processing Journal, vol. 3, pp. 259-272, 1993. [7] P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato, and A. Baschirotto, “Behavioral Modeling of Switched-Capacitor Sigma Delta Modulators,” IEEE Trans. Circuits Syst. I, vol. 50, pp. 352–364, Mar. 2003.
Power consumption
38 mW
Active Area
1.4×1.05 mm2, 1.8-V
Process
TSMC 1P6M 0.18um CMOS
[8] R. Gaggl, M. Inversi and A. Wiesbauer, “A Power Optimized 14-Bit SC Delta Digma Modulator for ADSL CO Applications,” IEEE International Solid-State Circuits Conference, ISSCC, vol. 4, 2004. [9] K. Gulati and H. S. Lee, “A High-Swing COMS Telescopic Operational Amplifier,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2010-2019, Dec. 1998.
Table 3: Sigma delta modulator performance comparisons ENOB
fBW
Process
(Bit) (MHz)
Power FOM
Park 03
14.5
2.5
0.35µm-5V
495
4.2
Geerts 00
12.5
6.25
0.65µm-5V
380
5.2
Balmelli 04
14
12.5 0.18µm-1.8V 200
0.49
This work
12
10
[10] A. Marques, V. Peluso, M. Steyaert, and W. Sansen, “A 15-b Resolution 2MHz Nyquist Rate Delta Sigma ADC in a 1-um COMS Technology,” IEEE Journal of Solid-state Circuits, vol. 33, no. 7, pp. 10651075, July 1998.
(mW) (pJ)
0.18µm-1.8V
38
[11] Y.-In Park; S. Karthikeyan, M. K. Wern, J. Zhongnong, and T.-C. Tan, “A 16-bit, 5-MHz Multi-Bit Sigma-Delta ADC Using Adaptively Randmoized DWA,” in Proc. IEEE Custom Integrated Circ. Conf., pp. 7-21–7-2-4, Sept. 2003.
0.46
5. CONCLUSION In the wide bandwidth applications, the power consumption is a critical point of the circuit design for the
[12] Y. Geerts, M. J. Steyaert, and W. Sansen, “A High-Performance Multibit Delta Sigma CMOS ADC,” IEEE J. Solid-State Circuits, vol. 35, pp. 1829–1840, Dec. 2000.
1891
