A 500 MHz to 6 GHz Frequency Synthesizer ... - LabUnix - UQAM
A 500 MHz to 6 GHz Frequency Synthesizer Architecture for Cognitive Radio Applications Zakaria El alaoui Ismaili, Frederic Nabki, Wessam Ajib and Mounir Boukadoum CoFaMic Research Center, Department of Computer Science Universit´e du Qu´ebec a` Montr´eal, Canada [email protected], {nabki.frederic, ajib.wessam, boukadoum.mounir}@uqam.ca Abstract— This paper presents a frequency synthesizer architecture for cognitive radio applications designed to generate carrier frequencies spread into twelve bands distributed from 500 MHz to 6 GHz with a spacing of 500 MHz. At 4 GHz, the simulated phase noise is −110.8 dBc/Hz at a 1-MHz offset. The loop bandwidth of the PLL is of 575 kHz, and the switching time between bands is simulated to be of 5.75 ns.
I. I NTRODUCTION Cognitive radio is an emerging wireless communication paradigm that brings about many advantages, one of which being spectrum sensing, where the degree of occupancy of the spectrum can be detected on the fly in order to be utilized without affecting the transmissions of licensed users. To enable this function, wide band detection and transmission of signals is required. As such, for maximum versatility, the local oscillators (LO) in transceivers for cognitive radio needs to cover a very wide range of output frequencies while taking into consideration the noise performance requirements. Such systems have previously used complicated discrete modules and functions to achieve multi-GHz output frequency ranges [1,2]. These implementations usually consume large area and have elevated power consumption. Today’s CMOS technologies allows for very high degrees of integration and functionality, and for low-power consumption. As such, by using CMOS technology, these multi-GHz frequency synthesis modules are well-suited to integration within a single chip. Such integrated systems have been demonstrated in different integrated technologies. For instance, different synthesizers using a single voltage controlled oscillator (VCO) were shown in [1-4]. In [1], seven carrier frequencies between 3.4 GHz and 7.9 GHz can be generated using two single sideband (SSB) mixers. In [2], thirteen bands between 3 and 10 GHz can be generated using three SSB mixers and four polyphase filters. In [3], eight frequency bands can be generated in the range of 54862 MHz without any SSB mixer, while in [4], the continuous frequency tuning range was demonstrated from 5 to 10 GHz. Other works have increased the complexity of systems by using multiple VCOs. In [5], seven bands were generated between 3 to 8 GHz using a single SSB mixer and two phaselocked loops (PLL), each with independent VCOs. Two VCOs were also used in [6] to produce thirteen bands from 1 to 10 GHz, but these VCOs do not operate simultaneously. A similar approach was used in [7] to generate 22 bands from 0.6 to 4.6 GHz, 5 to 7 GHz, 10 to 14 GHz, and 20 to 28 GHz.
978-1-4673-1260-8/12/$31.00 ©2012 IEEE
All these works can be classified by the number of VCOs and SSB mixers used. Works in [5] and [7] use dual VCOs, whereas works in [1] and [4] use a single VCO producing a smaller output range and requiring more SSB mixers. The usage of several mixers in these architectures results in multiple spurs and higher complexity. Overall, multi-VCO systems allow for a wide output range and a reduced number of SSB mixers. Those approaches, as they require multiple PLLs, exhibit some disadvantages such as large power consumption, high complexity and large die area. Accordingly, the challenge is to design a synthesizer able to cover multi-GHz frequency bands with a single PLL while minimizing the number of SSB mixers used in order to maintain low power consumption and reduce system area. This paper presents a frequency synthesizer architecture that can be used to implement such a system in order to achieve good spur performance, low phase noise and fast band-switching performances. To do this, the architecture contains only one SSB mixer and dual-frequency VCO controlled by a single PLL. The synthesizer can generate twelve carriers with a spacing of 500 MHz to cover a frequency range from 500 MHz to 6 GHz. The paper is organized as follows. An architecture overview is given in section II, followed in section III by a brief description of the design elements and a discussion of each block envisioned for the implementation of this architecture. The PLL phase noise is discussed in section IV. System-level simulation results are then presented in section V and are followed by our conclusions. II. A RCHITECTURE OVERVIEW The block diagram of the proposed frequency synthesizer is shown in Fig.1. It includes a dual-frequency VCO, a SSB mixer, a phase-frequency detector (PFD), two polyphase filters, three band selectors and frequency dividers. The VCO generates two frequencies: 3.5 GHz and 6 GHz. The 6 GHz is divided to provide the 2 GHz, 1.5 GHz, 1 GHz, and 500 MHz output frequencies. By using band selector 1, either of the VCO output frequencies can be mixed with a frequency of 2 GHz, 1.5 GHz, 1 GHz or 500 MHz coming from band selector 2. This provides frequencies from 1.5 to 5.5 GHz in increments of 500 MHz, except for 3.5 GHz. This particular frequency can be routed directly from the output of the VCO using band selectors 1 and 3. This can also be done for the 6 GHz VCO output, and, by using band
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Fig. 1.
Fig. 2.
Block diagram of the frequency synthesizer architecture.
The frequency allocations. Fig. 3.
selectors 2 and 3, for its divided frequencies of 500 MHz and 1 GHz. Overall, frequencies ranging from 500 MHz to 6 GHz can be generated in 500 MHz increments as shown in Fig.2. Frequencies between these 500 MHz increments can be reached by modulating the VCO’s output through an integer-N operation of the PLL loop by using a programmable divide by N divider. Alternatively, fractional−N operation can be used if continuous frequency tuning over a given range is required, but this may be limited by the continuous tuning range of the VCO. The SSB mixer used in this architecture consists of two 90-degree phase shifters and two double-side-band mixers [3]. III. A RCHITECTURAL D ESIGN A. Phase-locked Loop The PLL used in this architecture consists of a PFD with gain Kd , a charge pump (CP) with current Ip directly related to Kd by Kd =Ip /2π, a passive phase lag-lead low pass filter with R, C1 and C2 as filter components [8], a VCO with gain K0 and a programmable divider. The PLL loop insures that the output frequency, fout , is locked to the input frequency, fin , such that fout = N.fin . The resulting LPF transfer function F (s) is given by: F (s) =
1 + RC1 s . 1 C2 s(C1 + C2 ) 1 + RC C1 +C2 s
(1)
The closed loop transfer function Y (s) is described as [8]: s 2 K0 ω 1 + n K F (s) ω z d s , (2) Y (s) = = 2 s + 2ξωn s + ωn2 1 + Ks0 Kd F (s)N where N is the division loop factor. The loop bandwidth and stability involve careful selection of the natural frequency ωn , the stabilizing zero ωz , and the damping factor ξ. The PLL design was undertaken using the aforementioned equations, and validated through the Advanced Design System (ADS) software package simulation tools. The VCO gain
Pulse swallow programmable divider.
K0 and charge pump current Ip must be chosen carefully to ensure suitable compromise between the bandwidth and the stability. Whereas a large value of K0 Ip increases the bandwidth, a high Ip value should be avoided in order to not require a big capacitance inside the loop filter, and a low VCO gain generally translates to better phase noise and spur performance. With these considerations, the value for R should be between 0.5 kΩ and 20 kΩ to guarantee sufficient phase margin of at least 45 degrees. The capacitance C1 is related to both the natural frequency and the damping factor, and can be between 50 pF and 400 pF to attain stable operation. Moreover, capacitance C2 should be less than 10% of C1 in order to preserve the phase margin, and more than 2% of C1 to allow for better spur and jitter performance [8]. B. Dividers The architecture uses a divide by 2 and a divide by 3 that are implemented using D-type flip-flops [2]. The divide by 4 is achieved by two cascaded divide by 2s. The PLL utilizes a programmable divide-by-N in the feedback path. As shown in Fig. 3, the implementation of this divider is based on the pulse swallow architecture, consisting of a 2/3 dual modulus prescaler based on the combined logical functions of both the divide by 2 and the divide by 3, a 7-bit program P counter and an 7-bit swallow S counter. When targeting any of the twelve bands, the divider ratio is fixed at 240. However, in order to allow output frequencies between bands, the programmable divider can be programmed with a ratio from 199 to 293. This allows a configuration that supports integer-N or fractionalN implementations. A fractional-N configuration provides a continuous frequency range from 1.25 GHz to 6.25 GHz. The continuous tuning range is limited at the low-side to 1.5 GHz because of the excessive VCO tuning range that would be required to lock the PLL between a 0.5 and 1.25 GHz output frequency. This limitation was set by assuming a VCO continuous tuning range of 29%, and could be mitigated if
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Magnitude (dB)
a wider tuning range VCO is used. However, a wider tuning range VCO may cause significant degradation of the spur and phase noise performance.
Phase (degree)
C. Band Selectors The architecture utilizes three 2-input or 4-input band selectors that are controlled digitally and implemented using analog multiplexers. The band selectors are implemented in 0.18 µm CMOS technology with transmission gates. Sufficient isolation must be achieved to avoid signal leakage, especially of the 6 GHz VCO output [5,6].
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IV. PLL P HASE N OISE This section will present an analytical description of the noise behavior in the PLL, in order to distinguish the contribution of each component and predict the phase noise vs. frequency offset performance. The thermal noise, 1/f noise and shot noise produced in different PLL components cause the phase noise. The important sources of noise are: i) the noise introduced by the frequency reference, ii) the noise generated by the VCOs and iii) the noise of the loop filter. The reference represents an inevitable noise source in PLL systems. Its noise performance has already analyzed in [9], taking into account Lesson’s model modifications. The noise contribution from the reference is: G(s) 2 , (3) Srefout (f ) = Sref (f ) 1 + G(s)N
where G(s) is the PLL forward transfer function (K0 Kd F (s))/s, while Sref (f ) is the phase noise of the free-running reference. As can be seen from (3), the reference noise is low-pass filtered, such that its phase noise contribution at the output is dominant at lower frequencies within the loop bandwidth. The phase noise introduced by the VCO is expressed as: 2 1 , (4) Svcoout (f ) = Svco (f ) 1 + G(s)N where Svco (f ) is the phase noise of the free-running VCO. Equation (4) indicates that the VCO noise contribution is high-pass filtered, suppressing the phase noise within the loop bandwidth. This relates to the typical optimization of the loop bandwidth in order to minimize the phase noise maxima of the VCO within the loop. The loop filter also contributes to the phase noise mainly because of resistor with a power density Sloop (f ) given in [10]. The loop filter contribution to the PLL output phase noise is expressed as: 2 2 1 2 K0 . (5) Sloopout (f ) = Sloop (f ) |F (s)| s 1 + G(s)N
The loop filter phase noise contribution at the PLL output is thus similar to the VCO’s contribution, with the addition of a pole from the VCO at DC, thus increasing its negative slope. The PFD and the divider are assumed to have a negligible
impact on phase noise because of the relatively larger noise contributed by the VCO, loop filter and reference [11]. This is expected because of the large divider ratio used and the operating frequencies of the VCO and frequency reference. In addition, frequency detectors are not a dominant source of noise in synthesizers because of their low operation frequency. V. S IMULATION R ESULTS The architecture was simulated at the system level using ADS. Phase noise performance of the free-running reference and free-running VCO where inserted within the simulator, in order to give realistic estimates of the performances of these elements considering their respective operating frequency and Q-factor. These were based on results reported in [12]. Phase noise performance was simulated along with the frequency response to extract phase margin and the transient response to characterize the dynamic behavior. As was discussed in Section III, values for the loop filter components, VCO gain and charge pump current have to be carefully selected. The values were selected through postanalysis simulation-driven optimizations. The values of R, C1 and C2 were set to 1.93 kΩ, 389 pF and 29 pF, respectively, whereas the VCO gain and charge pump current were selected to be 400 MHz/V and 2 mA, respectively. The reference of the PLL has a frequency of 25 MHz, allowing for a relatively large natural frequency. Fig. 4 shows the open-loop frequency response of the PLL at a 4 GHz output frequency. The loop exhibits a bandwidth of 575 kHz and a phase margin of 57 degrees, which allow for fast settling time and stable operation. The overall simulated phase noise at an operating frequency of 4 GHz is −110.8 dBc/Hz at a 1 MHz offset frequency, as illustrated in Fig. 5. The phase noise of the system is dominated close-in by the reference noise, as expected by the lack of noise filtering within the loop bandwidth, and by the relatively large divider ratio used. The loop filter noise dominates in the mid frequency offsets, whereas the VCO noise dominates at far-out offsets, beyond the loop bandwidth. This is expected, as the VCO gain was selected to be fairly large, in order to allow for a wide enough tuning range, given the limited CMOS control voltage input range (i.e., below 1.8 V). It would be possible to reduce the impact of the loop filter noise by reducing the VCO gain, but this would require
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−80 −110.8dBc/Hz
−100 −120 −140
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Fig. 5. Output phase noise plot for the different noise contributors with the total resulting phase noise.
Band switching time. TABLE I
P ERFORMANCE S UMMARY
VCO frequency (MHz)
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Frequency (GHz) No. of Bands VCO (GHz) SSB Mixers Phase Noise (dBc/Hz at 1-MHz) Switching Time (ns)
3.4−7.9 7 16 2 −110 3
3−10 13 10.032 3 −106 3.75
0.5−6 12 6/3.5 1 −110.8 5.75
Transient response of the PLL.
the use of a voltage charge pump to increase the VCO control voltage [13]. The 6.25 GHz frequency setting represents the worst settling time as it requires the highest divider ratio. Figure 6 shows the transient behavior of the system during a transition from 6 GHz to 6.25 GHz. After the system start-up, a setting time of 1.7 µs is exhibited, showing the loop-related locking dynamics for relatively small frequency excursions. Figure 7 shows the frequency synthesizer switching time between the 0.5 GHz and the 2 GHz by using the band selectors. The band switching time is 5.75 ns. This is expected as this switching time is dominated by the band selectors, and could be increased depending on whether the SSB mixer dynamics are exerted. Table I summarizes the performance of the proposed architecture and compares it with some other frequency synthesizers previously presented in the literature. The proposed architecture compares favorably in terms of the covered frequency range and of the reduced number of SSB mixers used, indicating that it has the potential of increasing system versatility and reducing overall system complexity. Its projected phase noise is also comparable to others. VI. CONCLUSION In this paper, a 500 MHz to 6 GHz frequency synthesizer architecture was presented. With a 25 MHz frequency reference, the system can generate twelve carriers between 500 MHz and 6 GHz with only one SSB mixer, and is suitable for cognitive radio applications. At a 4 GHz frequency, the synthesizer achieves a phase margin of 57 degrees with bandwidth of 575 KHz. The simulated phase noise is about −110.8 dBc/Hz at a 1 MHz offset frequency and the band switching time
is 5.75 ns. This architecture is currently being implemented in 0.18µm CMOS technology. Implementation-specific details will be discussed in future work. R EFERENCES [1] A. Ismail and A. Abidi, “A 3.1 to 8.2 GHz zero-IF receiver and direct frequency synthesizer in 0.18 µm SiGe BiCMOS for mode-2 MBOFDM UWB communication,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2573 – 2582, Dec. 2005. [2] Z.-D. Huang, F.-W. Kuo, W.-C. Wang, and C.-Y. Wu, “A 1.5 V 3 to 10 GHz 0.18 µm CMOS frequency synthesizer for MB-OFDM UWB applications,” in IEEE MTT-S Int. Microwave Symp. Digest, June 2008, pp. 229 –232. [3] J. Kim, S. J. Lee, S. Kim, J. O. Ha, Y. S. Eo, and H. Shin, “A 54862 MHz CMOS transceiver for TV-band white-dpace device applications,” IEEE Trans. on Microwave Theory and Techniques, vol. 59, no. 4, pp. 966 –977, April 2011. [4] J. Lu, N.-Y. Wang, and M. Chang, “A single-LC-tank 5-10 GHz quadrature local oscillator for cognitive radio applications,” in IEEE RFIC, June 2011. [5] J. Lee, “A 3 to 8 GHz fast-hopping frequency synthesizer in 0.18 µm CMOS technology,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 566 – 573, Mar. 2006. [6] B. Razavi, “Multi-decade carrier generation for cognitive radios,” in Symp. VLSI Circuits, June 2009, pp. 120 –121. [7] S. Osmany, F. Herzel, and J. Scheytt, “An Integrated 0.6-4.6 GHz, 57 GHz, 10-14 GHz, and 20-28 GHz frequency synthesizer for softwaredefined radio applications,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1657 –1668, Sept. 2010. [8] V. F. Kroupa, Phase lock loops and frequency synthesis. John Wiley and Sons,Ltd, June 2003. [9] D. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, no. 2, pp. 329 – 330, Feb. 1966. [10] D. Banerjee, PLL Performance, Simulation, and Design. Dog Ear Publishing, LLC; 4th edition, 2006. [11] B. Razavi, Phase-Locking in High-Performance Systems: From Devices to Architectures. Wiley-IEEE Press, New York, 2003. [12] Y. W. Kim and J. D. Yu, “Phase Noise Model of Single Loop Frequency Synthesizer,” IEEE Trans. on Broadcasting, vol. 54, no. 1, pp. 112 – 119, march 2008. [13] H.-S. Kim and M. El-Gamal, “A 1 V fully integrated CMOS frequency synthesizer for 5-GHz WLAN,” in IEEE ISCAS, may 2005.
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I. I NTRODUCTION Cognitive radio is an emerging wireless communication paradigm that brings about many advantages, one of which being spectrum sensing, where the degree of occupancy of the spectrum can be detected on the fly in order to be utilized without affecting the transmissions of licensed users. To enable this function, wide band detection and transmission of signals is required. As such, for maximum versatility, the local oscillators (LO) in transceivers for cognitive radio needs to cover a very wide range of output frequencies while taking into consideration the noise performance requirements. Such systems have previously used complicated discrete modules and functions to achieve multi-GHz output frequency ranges [1,2]. These implementations usually consume large area and have elevated power consumption. Today’s CMOS technologies allows for very high degrees of integration and functionality, and for low-power consumption. As such, by using CMOS technology, these multi-GHz frequency synthesis modules are well-suited to integration within a single chip. Such integrated systems have been demonstrated in different integrated technologies. For instance, different synthesizers using a single voltage controlled oscillator (VCO) were shown in [1-4]. In [1], seven carrier frequencies between 3.4 GHz and 7.9 GHz can be generated using two single sideband (SSB) mixers. In [2], thirteen bands between 3 and 10 GHz can be generated using three SSB mixers and four polyphase filters. In [3], eight frequency bands can be generated in the range of 54862 MHz without any SSB mixer, while in [4], the continuous frequency tuning range was demonstrated from 5 to 10 GHz. Other works have increased the complexity of systems by using multiple VCOs. In [5], seven bands were generated between 3 to 8 GHz using a single SSB mixer and two phaselocked loops (PLL), each with independent VCOs. Two VCOs were also used in [6] to produce thirteen bands from 1 to 10 GHz, but these VCOs do not operate simultaneously. A similar approach was used in [7] to generate 22 bands from 0.6 to 4.6 GHz, 5 to 7 GHz, 10 to 14 GHz, and 20 to 28 GHz.
978-1-4673-1260-8/12/$31.00 ©2012 IEEE
All these works can be classified by the number of VCOs and SSB mixers used. Works in [5] and [7] use dual VCOs, whereas works in [1] and [4] use a single VCO producing a smaller output range and requiring more SSB mixers. The usage of several mixers in these architectures results in multiple spurs and higher complexity. Overall, multi-VCO systems allow for a wide output range and a reduced number of SSB mixers. Those approaches, as they require multiple PLLs, exhibit some disadvantages such as large power consumption, high complexity and large die area. Accordingly, the challenge is to design a synthesizer able to cover multi-GHz frequency bands with a single PLL while minimizing the number of SSB mixers used in order to maintain low power consumption and reduce system area. This paper presents a frequency synthesizer architecture that can be used to implement such a system in order to achieve good spur performance, low phase noise and fast band-switching performances. To do this, the architecture contains only one SSB mixer and dual-frequency VCO controlled by a single PLL. The synthesizer can generate twelve carriers with a spacing of 500 MHz to cover a frequency range from 500 MHz to 6 GHz. The paper is organized as follows. An architecture overview is given in section II, followed in section III by a brief description of the design elements and a discussion of each block envisioned for the implementation of this architecture. The PLL phase noise is discussed in section IV. System-level simulation results are then presented in section V and are followed by our conclusions. II. A RCHITECTURE OVERVIEW The block diagram of the proposed frequency synthesizer is shown in Fig.1. It includes a dual-frequency VCO, a SSB mixer, a phase-frequency detector (PFD), two polyphase filters, three band selectors and frequency dividers. The VCO generates two frequencies: 3.5 GHz and 6 GHz. The 6 GHz is divided to provide the 2 GHz, 1.5 GHz, 1 GHz, and 500 MHz output frequencies. By using band selector 1, either of the VCO output frequencies can be mixed with a frequency of 2 GHz, 1.5 GHz, 1 GHz or 500 MHz coming from band selector 2. This provides frequencies from 1.5 to 5.5 GHz in increments of 500 MHz, except for 3.5 GHz. This particular frequency can be routed directly from the output of the VCO using band selectors 1 and 3. This can also be done for the 6 GHz VCO output, and, by using band
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Fig. 1.
Fig. 2.
Block diagram of the frequency synthesizer architecture.
The frequency allocations. Fig. 3.
selectors 2 and 3, for its divided frequencies of 500 MHz and 1 GHz. Overall, frequencies ranging from 500 MHz to 6 GHz can be generated in 500 MHz increments as shown in Fig.2. Frequencies between these 500 MHz increments can be reached by modulating the VCO’s output through an integer-N operation of the PLL loop by using a programmable divide by N divider. Alternatively, fractional−N operation can be used if continuous frequency tuning over a given range is required, but this may be limited by the continuous tuning range of the VCO. The SSB mixer used in this architecture consists of two 90-degree phase shifters and two double-side-band mixers [3]. III. A RCHITECTURAL D ESIGN A. Phase-locked Loop The PLL used in this architecture consists of a PFD with gain Kd , a charge pump (CP) with current Ip directly related to Kd by Kd =Ip /2π, a passive phase lag-lead low pass filter with R, C1 and C2 as filter components [8], a VCO with gain K0 and a programmable divider. The PLL loop insures that the output frequency, fout , is locked to the input frequency, fin , such that fout = N.fin . The resulting LPF transfer function F (s) is given by: F (s) =
1 + RC1 s . 1 C2 s(C1 + C2 ) 1 + RC C1 +C2 s
(1)
The closed loop transfer function Y (s) is described as [8]: s 2 K0 ω 1 + n K F (s) ω z d s , (2) Y (s) = = 2 s + 2ξωn s + ωn2 1 + Ks0 Kd F (s)N where N is the division loop factor. The loop bandwidth and stability involve careful selection of the natural frequency ωn , the stabilizing zero ωz , and the damping factor ξ. The PLL design was undertaken using the aforementioned equations, and validated through the Advanced Design System (ADS) software package simulation tools. The VCO gain
Pulse swallow programmable divider.
K0 and charge pump current Ip must be chosen carefully to ensure suitable compromise between the bandwidth and the stability. Whereas a large value of K0 Ip increases the bandwidth, a high Ip value should be avoided in order to not require a big capacitance inside the loop filter, and a low VCO gain generally translates to better phase noise and spur performance. With these considerations, the value for R should be between 0.5 kΩ and 20 kΩ to guarantee sufficient phase margin of at least 45 degrees. The capacitance C1 is related to both the natural frequency and the damping factor, and can be between 50 pF and 400 pF to attain stable operation. Moreover, capacitance C2 should be less than 10% of C1 in order to preserve the phase margin, and more than 2% of C1 to allow for better spur and jitter performance [8]. B. Dividers The architecture uses a divide by 2 and a divide by 3 that are implemented using D-type flip-flops [2]. The divide by 4 is achieved by two cascaded divide by 2s. The PLL utilizes a programmable divide-by-N in the feedback path. As shown in Fig. 3, the implementation of this divider is based on the pulse swallow architecture, consisting of a 2/3 dual modulus prescaler based on the combined logical functions of both the divide by 2 and the divide by 3, a 7-bit program P counter and an 7-bit swallow S counter. When targeting any of the twelve bands, the divider ratio is fixed at 240. However, in order to allow output frequencies between bands, the programmable divider can be programmed with a ratio from 199 to 293. This allows a configuration that supports integer-N or fractionalN implementations. A fractional-N configuration provides a continuous frequency range from 1.25 GHz to 6.25 GHz. The continuous tuning range is limited at the low-side to 1.5 GHz because of the excessive VCO tuning range that would be required to lock the PLL between a 0.5 and 1.25 GHz output frequency. This limitation was set by assuming a VCO continuous tuning range of 29%, and could be mitigated if
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Magnitude (dB)
a wider tuning range VCO is used. However, a wider tuning range VCO may cause significant degradation of the spur and phase noise performance.
Phase (degree)
C. Band Selectors The architecture utilizes three 2-input or 4-input band selectors that are controlled digitally and implemented using analog multiplexers. The band selectors are implemented in 0.18 µm CMOS technology with transmission gates. Sufficient isolation must be achieved to avoid signal leakage, especially of the 6 GHz VCO output [5,6].
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IV. PLL P HASE N OISE This section will present an analytical description of the noise behavior in the PLL, in order to distinguish the contribution of each component and predict the phase noise vs. frequency offset performance. The thermal noise, 1/f noise and shot noise produced in different PLL components cause the phase noise. The important sources of noise are: i) the noise introduced by the frequency reference, ii) the noise generated by the VCOs and iii) the noise of the loop filter. The reference represents an inevitable noise source in PLL systems. Its noise performance has already analyzed in [9], taking into account Lesson’s model modifications. The noise contribution from the reference is: G(s) 2 , (3) Srefout (f ) = Sref (f ) 1 + G(s)N
where G(s) is the PLL forward transfer function (K0 Kd F (s))/s, while Sref (f ) is the phase noise of the free-running reference. As can be seen from (3), the reference noise is low-pass filtered, such that its phase noise contribution at the output is dominant at lower frequencies within the loop bandwidth. The phase noise introduced by the VCO is expressed as: 2 1 , (4) Svcoout (f ) = Svco (f ) 1 + G(s)N where Svco (f ) is the phase noise of the free-running VCO. Equation (4) indicates that the VCO noise contribution is high-pass filtered, suppressing the phase noise within the loop bandwidth. This relates to the typical optimization of the loop bandwidth in order to minimize the phase noise maxima of the VCO within the loop. The loop filter also contributes to the phase noise mainly because of resistor with a power density Sloop (f ) given in [10]. The loop filter contribution to the PLL output phase noise is expressed as: 2 2 1 2 K0 . (5) Sloopout (f ) = Sloop (f ) |F (s)| s 1 + G(s)N
The loop filter phase noise contribution at the PLL output is thus similar to the VCO’s contribution, with the addition of a pole from the VCO at DC, thus increasing its negative slope. The PFD and the divider are assumed to have a negligible
impact on phase noise because of the relatively larger noise contributed by the VCO, loop filter and reference [11]. This is expected because of the large divider ratio used and the operating frequencies of the VCO and frequency reference. In addition, frequency detectors are not a dominant source of noise in synthesizers because of their low operation frequency. V. S IMULATION R ESULTS The architecture was simulated at the system level using ADS. Phase noise performance of the free-running reference and free-running VCO where inserted within the simulator, in order to give realistic estimates of the performances of these elements considering their respective operating frequency and Q-factor. These were based on results reported in [12]. Phase noise performance was simulated along with the frequency response to extract phase margin and the transient response to characterize the dynamic behavior. As was discussed in Section III, values for the loop filter components, VCO gain and charge pump current have to be carefully selected. The values were selected through postanalysis simulation-driven optimizations. The values of R, C1 and C2 were set to 1.93 kΩ, 389 pF and 29 pF, respectively, whereas the VCO gain and charge pump current were selected to be 400 MHz/V and 2 mA, respectively. The reference of the PLL has a frequency of 25 MHz, allowing for a relatively large natural frequency. Fig. 4 shows the open-loop frequency response of the PLL at a 4 GHz output frequency. The loop exhibits a bandwidth of 575 kHz and a phase margin of 57 degrees, which allow for fast settling time and stable operation. The overall simulated phase noise at an operating frequency of 4 GHz is −110.8 dBc/Hz at a 1 MHz offset frequency, as illustrated in Fig. 5. The phase noise of the system is dominated close-in by the reference noise, as expected by the lack of noise filtering within the loop bandwidth, and by the relatively large divider ratio used. The loop filter noise dominates in the mid frequency offsets, whereas the VCO noise dominates at far-out offsets, beyond the loop bandwidth. This is expected, as the VCO gain was selected to be fairly large, in order to allow for a wide enough tuning range, given the limited CMOS control voltage input range (i.e., below 1.8 V). It would be possible to reduce the impact of the loop filter noise by reducing the VCO gain, but this would require
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Fig. 5. Output phase noise plot for the different noise contributors with the total resulting phase noise.
Band switching time. TABLE I
P ERFORMANCE S UMMARY
VCO frequency (MHz)
7000 6500 1.7us
6000 5500 5000 4500 4000 2
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[2]
This work
Frequency (GHz) No. of Bands VCO (GHz) SSB Mixers Phase Noise (dBc/Hz at 1-MHz) Switching Time (ns)
3.4−7.9 7 16 2 −110 3
3−10 13 10.032 3 −106 3.75
0.5−6 12 6/3.5 1 −110.8 5.75
Transient response of the PLL.
the use of a voltage charge pump to increase the VCO control voltage [13]. The 6.25 GHz frequency setting represents the worst settling time as it requires the highest divider ratio. Figure 6 shows the transient behavior of the system during a transition from 6 GHz to 6.25 GHz. After the system start-up, a setting time of 1.7 µs is exhibited, showing the loop-related locking dynamics for relatively small frequency excursions. Figure 7 shows the frequency synthesizer switching time between the 0.5 GHz and the 2 GHz by using the band selectors. The band switching time is 5.75 ns. This is expected as this switching time is dominated by the band selectors, and could be increased depending on whether the SSB mixer dynamics are exerted. Table I summarizes the performance of the proposed architecture and compares it with some other frequency synthesizers previously presented in the literature. The proposed architecture compares favorably in terms of the covered frequency range and of the reduced number of SSB mixers used, indicating that it has the potential of increasing system versatility and reducing overall system complexity. Its projected phase noise is also comparable to others. VI. CONCLUSION In this paper, a 500 MHz to 6 GHz frequency synthesizer architecture was presented. With a 25 MHz frequency reference, the system can generate twelve carriers between 500 MHz and 6 GHz with only one SSB mixer, and is suitable for cognitive radio applications. At a 4 GHz frequency, the synthesizer achieves a phase margin of 57 degrees with bandwidth of 575 KHz. The simulated phase noise is about −110.8 dBc/Hz at a 1 MHz offset frequency and the band switching time
is 5.75 ns. This architecture is currently being implemented in 0.18µm CMOS technology. Implementation-specific details will be discussed in future work. R EFERENCES [1] A. Ismail and A. Abidi, “A 3.1 to 8.2 GHz zero-IF receiver and direct frequency synthesizer in 0.18 µm SiGe BiCMOS for mode-2 MBOFDM UWB communication,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2573 – 2582, Dec. 2005. [2] Z.-D. Huang, F.-W. Kuo, W.-C. Wang, and C.-Y. Wu, “A 1.5 V 3 to 10 GHz 0.18 µm CMOS frequency synthesizer for MB-OFDM UWB applications,” in IEEE MTT-S Int. Microwave Symp. Digest, June 2008, pp. 229 –232. [3] J. Kim, S. J. Lee, S. Kim, J. O. Ha, Y. S. Eo, and H. Shin, “A 54862 MHz CMOS transceiver for TV-band white-dpace device applications,” IEEE Trans. on Microwave Theory and Techniques, vol. 59, no. 4, pp. 966 –977, April 2011. [4] J. Lu, N.-Y. Wang, and M. Chang, “A single-LC-tank 5-10 GHz quadrature local oscillator for cognitive radio applications,” in IEEE RFIC, June 2011. [5] J. Lee, “A 3 to 8 GHz fast-hopping frequency synthesizer in 0.18 µm CMOS technology,” IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 566 – 573, Mar. 2006. [6] B. Razavi, “Multi-decade carrier generation for cognitive radios,” in Symp. VLSI Circuits, June 2009, pp. 120 –121. [7] S. Osmany, F. Herzel, and J. Scheytt, “An Integrated 0.6-4.6 GHz, 57 GHz, 10-14 GHz, and 20-28 GHz frequency synthesizer for softwaredefined radio applications,” IEEE J. Solid-State Circuits, vol. 45, no. 9, pp. 1657 –1668, Sept. 2010. [8] V. F. Kroupa, Phase lock loops and frequency synthesis. John Wiley and Sons,Ltd, June 2003. [9] D. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, no. 2, pp. 329 – 330, Feb. 1966. [10] D. Banerjee, PLL Performance, Simulation, and Design. Dog Ear Publishing, LLC; 4th edition, 2006. [11] B. Razavi, Phase-Locking in High-Performance Systems: From Devices to Architectures. Wiley-IEEE Press, New York, 2003. [12] Y. W. Kim and J. D. Yu, “Phase Noise Model of Single Loop Frequency Synthesizer,” IEEE Trans. on Broadcasting, vol. 54, no. 1, pp. 112 – 119, march 2008. [13] H.-S. Kim and M. El-Gamal, “A 1 V fully integrated CMOS frequency synthesizer for 5-GHz WLAN,” in IEEE ISCAS, may 2005.
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