A BICS for CMOS opamps by monitoring the ... - Semantic Scholar
A BICS for CMOS Opamps by Monitoring the Supply Current Peak J. Font, J. Ginard, E. Isern, M. Roca, J.Segura, E. García Departament de Física- Universitat Illes Balears Cra. Valldemossa, km 7.5- 07071 Palma de Mallorca
We present a Built-In-Current-Sensor (BICS) based on monitoring the supply current peak of CMOS opamps using the oscillation-test-strategy. The BICS takes a weighed sample of the current through each opamp current branch and monitors the peak value under oscillation. An envelope detector and additional digital circuitry is used to provide a pass/fail flag. Simulation results demonstrate a high defect coverage with a very small impact on the opamp nominal operation.
voltage drop at the terminals of a resistor, MOS or diode. But it has the shortcoming of impacting the effective supply voltage range seen by the CUT. In this paper we propose for current measurement a collector of current mirrors, hardly impacting the normal operation of the opamp, that we have called current signature compressor. The rest of the paper is organised as follows. Section 2 presents the different blocks, the operation and the design specifications of the BICS. Section 3 presents the simulation results and the impact on OTA characteristics. Finally, main conclusions are highlighted in last section.
1. Introduction
2. BICS operation
The increase of mixed signal applications with ICs containing analog and digital parts, along with technology scaling motivates the development of several approaches for testing analog sections embedded in digital systems. One appoach to test mixed signal ICs that received significant attention is the oscillation-test-strategy (OTS). The basic idea under the oscillation-test strategy is to convert the circuit under test (CUT) into an oscillator during the test mode [1]. A feedback block is added to the CUT and activated in test mode to produce self-sustained oscillations. The presence of defects in the circuit impacts the oscillation frequency or even prevents it and can be used to distinguish between good and bad ICs. It has been also reported that the supply current can be an effective test observable with OTS to test CMOS opamps ([2], [3]). In [2] we measured the supply current of an opamp using the oscillation-test strategy considering bridges and opens with different resistance values. In [3] results showed that the most sensitive parameter was the supply current peak even when injecting GOS and floating gate defects. In [3], out of a number of 40 faults, 39 faults were detected using the negative supply current peak whose tolerance band was wide enough to expect a good robustness of the methodology. Based on the high defect coverage of this technique we propose a BICS that monitors the current peak. Here a BICS based on current peak monitoring is analysed to test compensated two-stage opamps. On the other hand, it has been studied in literature [4] which is the main drawback of Built-In-Current-Sensors. The observability of the supply current, either dynamic or quiescent, can be easily achieved by measuring the
We develop a BICS oriented to test compensated twostage CMOS opamps (Fig. 1) using the oscillation-test strategy [1, 5, 6, 7]. The test configuration and the feedback network were reported in [2]. The test observable is the peak of the negative supply current, shown in Fig. 2. The proposed BICS consists of three functional blocks: a current signature compressor, an envelope detector and a go/no go circuitry (Fig. 3).
Abstract
VDD
M1
M4
Vn
M7
M2
M5
Rc
Vp
VO
Cc
M8 M9 I9
M3
M6
I3
I6 VSS
I8
ISS
Figure 1. Compensated two-stage opamp.
2.1 The Current Signature Compressor (CSC) Many of the BICS proposed in the literature use a current-to-voltage tranducer inserted in series at the supply/ground node. This approach has the drawback of impacting the effective supply voltage range seen by the CUT.
Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW’02) 0-7695-1641-6/02 $17.00 © 2002 IEEE
desirable that at least M8bis wouldn’t fall into the ohmic (non saturation) region to obtain the best possible match Icopy and ISS. By simulation, it has been studied that M8bis is always in saturation if RS is below 2.7K. Anyway, M9bis still fades during a short interval into the ohmic zone. For RS=2.7K the error between ISS and Icopy is smaller than 1µA (0.11%). VDD +
Icopy=Iss
Vi
Rs
-
M9bis
Figure 2. Supply current in a single-opamp oscillator.
G9
The solution proposed in this work uses transistors of the opamp as referencial transistors to mirror the current of the different branches composing the amplifier. The current signature compressor is composed of N branches with N being the number of current paths being sensed from the opamp. The amplifier of Fig. 1 has four current branches that will be monitored and compressed into a single signature.
M3bis
M6bis
G3
I9
G6
G8
I6
I3
M8bis
I8
Iss VSS
Figure 4. Current signature compressor (CSC).
2.2 The envelope detector OPAMP UNDER TEST
EXTERNAL NETWORK
CURRENT SIGNATURE COMPRESSOR
ENVELOPE DETECTOR
PASS / FAIL CIRCUIT
BICS
Figure 3. Block diagram of the BICS. The CSC is shown in Fig. 4. It is composed of n NMOS transistors (n number of branches) that mirror the current from the branches of interest. Transistor M9bis copies the current I9 since the gate is connected to M9. Currents I3 and I6 should be equal and are copied through M3bis and M6bis, that are connected together. Finally device M8bis copies the current I8. Current mirrors have an important drawback: the two transistors must work within the active region (vDS>vGS Vth). Depending on the CSC pull-up RS value, some of the MOS transistors may work within non-saturation zone and wouldn’t behave as current mirrors. That occurs when the copied current is too large. If only one of the CSC transistors is not in saturation, the replica current Icopy is not equal to ISS. Indeed, each current mirror contributes to the current signature in a different manner. Clearly, I8 is the most important, followed by I3 and I6, and finally I9 (in this order). In the fault-free circuit, if the ISS peak is approximately 900µA, then I8≈800µA, I6=I3≈30µA and I9≈15µA. It would be
Different methods have been proposed to measure the amplitude of a waveform like the one shown in Fig. 2. One of the simplest methods is the envelope detector. Fig. 5 shows this detector, that is essentially just a halfwave rectifier which charges a capacitor CL to a voltage being approximately the peak voltage of the incoming input waveform. When vi’s amplitude increases, the capacitor voltage is increased via the rectifying diode. When the input’s amplitude decreases, the capacitor is discharged by a ‘bleed’ resistor RL. The main advantage of this form of this circuit is its simplicity. However, it does suffer from some practical problems, such as the diode’s nonlinearity and the ripple. + vd
-
vx
+ Icopy
vi -
RS
RL
CL
+ vo -
vy Figure 5. Envelope detector. The envelope detector relies upon the behaviour of the diode, allowing current through when the input is positive with respect to the capacitor voltage, hence ‘topping up’ the capacitor voltage to the peak level, but blocking any current from flowing back out through the diode when Vi is below the capacitor voltage vo. Unfortunately, all real diodes are non-linear. The I-V conversion is performed by
Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW’02) 0-7695-1641-6/02 $17.00 © 2002 IEEE
a single resistor RS, as illustrated in Fig. 5, and is carried out by the current signature compressor. The current through the diode varies with the applied voltage, as the diode’s I-V characteristic. To evaluate the distortion due to the diode’s non-linearity, the dynamic diode resistance model has been used: vd=Vknee+ rd(K) id(mA) The diodes provided by the technology used have and dynamic diode conductance Vknee≈0.853V gd≈41mA/V (these parameters are taken from a 0.35µm technology diode model). The relative error has been determined analytically: ∆Vo = Vo
The Pass/Fail circuit is activated by the test mode signal TM=1. The Vo voltage at the output of the envelope detector must be compared to each of the limits of the tolerance window (see Table 1), VHIGH and VLOW. Instead of measuring the differential voltage Vo and compare it to VLOW and VHIGH, new tolerance limits VHIGHTDM and VLOWTDM are calculated with respect to VY, which can be referred to VDD. So, for a fault-free circuit: VLOW
We present a Built-In-Current-Sensor (BICS) based on monitoring the supply current peak of CMOS opamps using the oscillation-test-strategy. The BICS takes a weighed sample of the current through each opamp current branch and monitors the peak value under oscillation. An envelope detector and additional digital circuitry is used to provide a pass/fail flag. Simulation results demonstrate a high defect coverage with a very small impact on the opamp nominal operation.
voltage drop at the terminals of a resistor, MOS or diode. But it has the shortcoming of impacting the effective supply voltage range seen by the CUT. In this paper we propose for current measurement a collector of current mirrors, hardly impacting the normal operation of the opamp, that we have called current signature compressor. The rest of the paper is organised as follows. Section 2 presents the different blocks, the operation and the design specifications of the BICS. Section 3 presents the simulation results and the impact on OTA characteristics. Finally, main conclusions are highlighted in last section.
1. Introduction
2. BICS operation
The increase of mixed signal applications with ICs containing analog and digital parts, along with technology scaling motivates the development of several approaches for testing analog sections embedded in digital systems. One appoach to test mixed signal ICs that received significant attention is the oscillation-test-strategy (OTS). The basic idea under the oscillation-test strategy is to convert the circuit under test (CUT) into an oscillator during the test mode [1]. A feedback block is added to the CUT and activated in test mode to produce self-sustained oscillations. The presence of defects in the circuit impacts the oscillation frequency or even prevents it and can be used to distinguish between good and bad ICs. It has been also reported that the supply current can be an effective test observable with OTS to test CMOS opamps ([2], [3]). In [2] we measured the supply current of an opamp using the oscillation-test strategy considering bridges and opens with different resistance values. In [3] results showed that the most sensitive parameter was the supply current peak even when injecting GOS and floating gate defects. In [3], out of a number of 40 faults, 39 faults were detected using the negative supply current peak whose tolerance band was wide enough to expect a good robustness of the methodology. Based on the high defect coverage of this technique we propose a BICS that monitors the current peak. Here a BICS based on current peak monitoring is analysed to test compensated two-stage opamps. On the other hand, it has been studied in literature [4] which is the main drawback of Built-In-Current-Sensors. The observability of the supply current, either dynamic or quiescent, can be easily achieved by measuring the
We develop a BICS oriented to test compensated twostage CMOS opamps (Fig. 1) using the oscillation-test strategy [1, 5, 6, 7]. The test configuration and the feedback network were reported in [2]. The test observable is the peak of the negative supply current, shown in Fig. 2. The proposed BICS consists of three functional blocks: a current signature compressor, an envelope detector and a go/no go circuitry (Fig. 3).
Abstract
VDD
M1
M4
Vn
M7
M2
M5
Rc
Vp
VO
Cc
M8 M9 I9
M3
M6
I3
I6 VSS
I8
ISS
Figure 1. Compensated two-stage opamp.
2.1 The Current Signature Compressor (CSC) Many of the BICS proposed in the literature use a current-to-voltage tranducer inserted in series at the supply/ground node. This approach has the drawback of impacting the effective supply voltage range seen by the CUT.
Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW’02) 0-7695-1641-6/02 $17.00 © 2002 IEEE
desirable that at least M8bis wouldn’t fall into the ohmic (non saturation) region to obtain the best possible match Icopy and ISS. By simulation, it has been studied that M8bis is always in saturation if RS is below 2.7K. Anyway, M9bis still fades during a short interval into the ohmic zone. For RS=2.7K the error between ISS and Icopy is smaller than 1µA (0.11%). VDD +
Icopy=Iss
Vi
Rs
-
M9bis
Figure 2. Supply current in a single-opamp oscillator.
G9
The solution proposed in this work uses transistors of the opamp as referencial transistors to mirror the current of the different branches composing the amplifier. The current signature compressor is composed of N branches with N being the number of current paths being sensed from the opamp. The amplifier of Fig. 1 has four current branches that will be monitored and compressed into a single signature.
M3bis
M6bis
G3
I9
G6
G8
I6
I3
M8bis
I8
Iss VSS
Figure 4. Current signature compressor (CSC).
2.2 The envelope detector OPAMP UNDER TEST
EXTERNAL NETWORK
CURRENT SIGNATURE COMPRESSOR
ENVELOPE DETECTOR
PASS / FAIL CIRCUIT
BICS
Figure 3. Block diagram of the BICS. The CSC is shown in Fig. 4. It is composed of n NMOS transistors (n number of branches) that mirror the current from the branches of interest. Transistor M9bis copies the current I9 since the gate is connected to M9. Currents I3 and I6 should be equal and are copied through M3bis and M6bis, that are connected together. Finally device M8bis copies the current I8. Current mirrors have an important drawback: the two transistors must work within the active region (vDS>vGS Vth). Depending on the CSC pull-up RS value, some of the MOS transistors may work within non-saturation zone and wouldn’t behave as current mirrors. That occurs when the copied current is too large. If only one of the CSC transistors is not in saturation, the replica current Icopy is not equal to ISS. Indeed, each current mirror contributes to the current signature in a different manner. Clearly, I8 is the most important, followed by I3 and I6, and finally I9 (in this order). In the fault-free circuit, if the ISS peak is approximately 900µA, then I8≈800µA, I6=I3≈30µA and I9≈15µA. It would be
Different methods have been proposed to measure the amplitude of a waveform like the one shown in Fig. 2. One of the simplest methods is the envelope detector. Fig. 5 shows this detector, that is essentially just a halfwave rectifier which charges a capacitor CL to a voltage being approximately the peak voltage of the incoming input waveform. When vi’s amplitude increases, the capacitor voltage is increased via the rectifying diode. When the input’s amplitude decreases, the capacitor is discharged by a ‘bleed’ resistor RL. The main advantage of this form of this circuit is its simplicity. However, it does suffer from some practical problems, such as the diode’s nonlinearity and the ripple. + vd
-
vx
+ Icopy
vi -
RS
RL
CL
+ vo -
vy Figure 5. Envelope detector. The envelope detector relies upon the behaviour of the diode, allowing current through when the input is positive with respect to the capacitor voltage, hence ‘topping up’ the capacitor voltage to the peak level, but blocking any current from flowing back out through the diode when Vi is below the capacitor voltage vo. Unfortunately, all real diodes are non-linear. The I-V conversion is performed by
Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW’02) 0-7695-1641-6/02 $17.00 © 2002 IEEE
a single resistor RS, as illustrated in Fig. 5, and is carried out by the current signature compressor. The current through the diode varies with the applied voltage, as the diode’s I-V characteristic. To evaluate the distortion due to the diode’s non-linearity, the dynamic diode resistance model has been used: vd=Vknee+ rd(K) id(mA) The diodes provided by the technology used have and dynamic diode conductance Vknee≈0.853V gd≈41mA/V (these parameters are taken from a 0.35µm technology diode model). The relative error has been determined analytically: ∆Vo = Vo
The Pass/Fail circuit is activated by the test mode signal TM=1. The Vo voltage at the output of the envelope detector must be compared to each of the limits of the tolerance window (see Table 1), VHIGH and VLOW. Instead of measuring the differential voltage Vo and compare it to VLOW and VHIGH, new tolerance limits VHIGHTDM and VLOWTDM are calculated with respect to VY, which can be referred to VDD. So, for a fault-free circuit: VLOW
