A Digital Dual-state-variable Predictive Controller for High Switching ...
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A Digital Dual-state-variable Predictive Controller for High Switching Frequency Buck Converter with Improved Σ-∆ DPWM Bo Li, Xuefang Lin-Shi, Member, IEEE, Bruno Allard, Senior Member, IEEE, Jean-Marie R´etif
Abstract—This paper presents a novel digital controller for the high switching frequency buck converter based on the principle of predictive control. Compared to traditional current-mode predictive controller, the prediction of the inductor current and the output voltage are performed at the same time by adding a control variable to the DPWM signal that can dynamically adjust the time of voltage jump. It accelerates the convergence rate during transient states, while inherently preserving the rejection of power and reference perturbations. The analysis of controller’s operation illustrates the dual-state-variable predictive attributes that lead to the digital implementation. To further enhance the power efficiency of the controller, an 1-1 MASH Σ-∆ DPWM with a feasible dither generation module is proposed to restrain the idle-tone effects without deteriorating the closed-loop stability as well as to preserve reasonable cost in silicon area. Experimental results verify closed-loop operations at switching frequency up to 4 MHz only limited by the discrete buck converter. The converter is well regulated over a large output range with excellent dynamic performances. Index Terms—DC-DC converter, switched-mode power supply, predictive control, digital control, digital pulse-width-modulator.
I. I NTRODUCTION
D
IGITAL control for low-power switched-mode power supplies (SMPS) opens up the possibility of the integration of high switching frequency power converter systems [1]–[5]. Compared to analog counterparts, the digital approach allows the development of controllers which cannot be realized in the analog domain. For example, specific nonlinear controllers can boost the dynamic response to the perturbations from the power stage [6], [7]; the active efficiency monitoring and the digital autotuning can improve the control performances [8]–[10]. Moreover digital control exhibits inherent advantages with respect to integration, for instance, its insensitivity to the process-voltage-temperature (PVT) variations, design reuse and reprogrammability that accelerates time-tomarket (TTM). Digital controller is therefore regarded as an attractive candidate with better performances than the analog counterparts. Manuscript received October 24, 2011. Accepted for publication March 22, 2012. c 2009 IEEE. Personal use of this material is permitted. Copyright However, permission to use this material for any other purposes must be obtained from the IEEE by sending a request to [email protected] Bo Li, Xuefang Lin-Shi, Bruno Allard and Jean-Marie R´etif are with the Universit´e de Lyon, Amp`ere, INSA Lyon, CNRS UMR 5005, Villeurbanne, France, F-69621 (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).
Thanks to the approach based on the look-up table (LUT), the implementation of the linear controller, notably the voltage-mode PID controller, benefits most in terms of the cost of the hardware resource [2], [11], [12]. However, their performances generally depend on the operating point, so that the presence of parasitic elements, time-varying loads and variable supply voltages can deteriorate the control behavior. With the knowledge of inductor current, a double closed-loop control method is often adopted with an outer voltage loop and an inner current loop. This method has proven to be effective with inherent advantages including overcurrent protection and excellent audiosusceptibility [13], [14]. Dead-beat control [14] and current programmed control [13], [15] are widely used for the inner current loop. These control algorithms calculate the duty cycle according to a converter discrete model at every sampling period to make sure the inductor current tracks the reference in the next period. The current reference is generated by a classical voltage control loop. So the prediction is only made for the current loop but not for the voltage loop that restricts the dynamic performances. Moreover, a large part of these solutions have been still devoted to performed on Digital Signal Processor (DSP) or other processors in medium to high power application [16], [17]. Generally these digital control systems present sufficient resources to accommodate the modest switching frequency of the converter in the range of kHz. In these medium to high power application systems, the size is not the primary focus, neither the power consumption. For low-power SMPS application, in order to reduce the size of passive components, the switching frequency can reach MHz and over. To the authors’ knowledge, predictive control has never been employed in the design of a digital control for such highswitching frequency SMPS. However, the target applications of the proposed controller cover the typical operations of battery-powered embedded systems in power range from 100 mW to several watts. In this paper, a current and voltage predictive controller is proposed for a high-switching frequency SMPS. Unlike the double closed-loop control method, the prediction of both the inductor current and the output voltage is performed at the same time by adding an extra control parameter τ1 which corresponds to an interval between the beginning of each switching period and the time of high voltage (see Fig. 1). The proposed controller preserves the merits of the predictive current control and allows to further enhance the dynamic performances while maintaining an excellent rejection of
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adjust control parameters, this paper also discusses an online parameter tuning module giving the possibility that allows an extended compatibility to higher switching frequency. This paper is organized as follows. Section II gives the details of the proposed current and voltage predicitve control. In Section III, a DMASH 1-1 DPWM is described. Simulation and experimental results are discussed in Section IV and V. A conclusion is drawn in Section VI. II. C URRENT AND VOLTAGE P REDICTIVE C ONTROL A. Discrete Model of the Buck Converter
Fig. 1. (a) Block diagram of the buck converter (b) A sample of corresponding current and voltage predictive control waveform
the power supply perturbations, and a robust and automatic switching error correction. Unlike the controller in analog domain, the implementation of a digital controller requires an analog-to-digital converter (ADC) and a digital pulse-width-modulator (DPWM) [18] for which a particular attention must be payed to avoid limit cycle oscillations (LCO) [19], [20]. The critical issue of ADC is to achieve sufficient resolution while to maintain low power consumption. Delay-line derived architectures [21], [22] are feasible solutions. All the proposed ADCs only measure the vicinity of the reference voltage employing the so-called windows concept. The design of ADCs does not fall within the scope of this paper. A high-resolution DPWM is another necessary condition to avoid LCO. From the viewpoint of time domain, many delay-line based architectures are proposed to generate shorter interval than the period of the basic system clock without the need of unachievable clock by counter-comparator architecture [21]. However, these approaches usually depend on a series of tight logic cells that exponentially increase with the increase of DPWM resolution. Frequency domain is another appropriate access to achieve DPWM with sufficient resolution using noise-shaping concept. The effective resolution is achieved by the Σ-∆ modulator through several switching periods without sacrificing larger hardware resource than that of the delay-line method [2]. However the slow convergence due to a low frequency periodic behavior in the lower-order Σ-∆ DPWM, known as idle-tone, produces low-frequency noise in the power stage [2]. The MASH type Σ-∆ DPWM appears to be an effective trade-off between the idle-tone attenuation and the cost of hardware, but proves no amelioration in noise-shaping effect [23]. In this paper, a dithered 1-1 MASH Σ-∆ structure (DMASH 11) is proposed to be a feasible candidate in terms of hardware cost and effective resolution. In addition, as an interface to
As shown in Fig. 1(a), the supply voltage is noted as E. The switched voltage is filtered by an LC tank to provide a constant output Vo to the load RL . Choosing the inductor current IL and the capacitor voltage as the state variable x (t) = , VC the state equations of the buck converter can be written as 1 1 0 0 −L (1) x˙ (t) = 1 x (t) + L 1 u (t) 0 − 0 C C 1 0 y (t) = x (t) (2) 0 1 0 where the input variable u (t) = when the PMOSFET Io E is ON, u (t) = when the NMOSFET is ON. Io Assuming only a small variation of the output current Io during a switching period Te , the input variable can be considered to be constant during Te . So the discrete-time model of the buck converter limited to the first-order can be expressed as Te Te Te2 1 −L 2LC x (k + 1) = T u (k) (3) x (k) + TL2 Te e e 1 − C 2LC C The description of the system state-space allows to analyse the behavior of the buck converter. The aim of the proposed controller is to make the inductor current and the capacitor voltage at the sampling point (k + 1) Te equal to the reference current and voltage at the end of corresponding switching period, respectively. B. Calculation of the Current Variation The PWM waveform pattern of the proposed dual-statevariable predictive control is shown in Fig. 1(b). The switching period is divided into three parts. Providing that all the current variations are defined as ∆Ii (k) = Ii (k + 1) − Ii (k), the change in IL in two adjacent cycles, ∆IL (k), is derived as (4). So the total change in IL in the current cycle is ∆IL (k) =
3 X i=1
∆ILi (k) =
1 (E · T1 (k) − VC (k) · Te ) (5) L
From (5), we can derived that ∆IL (k) is related to T1 and the capacitor voltage VC (k). That is to say, T1 in the next
LI et al.: A DIGITAL DUAL-STATE-VARIABLE PREDICTIVE CONTROLLER FOR HIGH SWITCHING FREQUENCY BUCK CONVERTER WITH IMPROVED Σ-∆ DPWM3
0;
τ1 ; τ1 + T1
τ1 + T1 ; Te
τ1
1 1 R τ1 (−VC (k)) dt = − VC (k) τ1 0 L L 1 1 R T1 (E − V (k)) dt = − (−ET1 + VC (k) T1 ) ∆IL2 (k) = C 0 L L 1 1 R Te (VC (k) Te − VC (k) τ1 − VC (k) T1 ) (−V (k)) dt = − ∆IL3 (k) = C τ +T 1 1 L L ∆IL1 (k) =
switching period can be, therefore, predicted from ∆IL (k) which obliges that the inductor current in the next cycle is compensated with the amount of ∆IL (k). So T1 (k + 1) is represented as T1 (k + 1) =
L Te ∆IL (k) + VC (k) E E
(6)
C. Calculation of the Voltage Variation From the perspective of a current variation, the three parts in one switching cycle can be expressed as (7) where I˙C0 (k) and I˙C1 (k) are the change rates of the capacitor current during the interval of τ1 and T1 respectively. IC (k) denotes the capacitor current at the starting point of each period. Here we define the capacitor voltage variation as ∆VC (k + 1) = VC (k + 1) − VC (k). The corresponding variation of the capacitor voltage in each switching period is, therefore, described as
of the predictive current and voltage. In order to simplify the analysis, (6) and (12) are represented respectively as T1 (k + 1) = f (∆IL (k) , VC (k)) (13) τ1 (k + 1) = g T1 (k + 1) , IC (k) , I˙C0 (k) , ∆VC (k + 1) (14) In order to obtain T1 by (13), VC (k) and ∆IL (k) are necessary values. If we ignore the capacitor ESR, the output voltage can be considered as the required VC (k) so that it can be obtained at every switching period. ∆IL (k) is another necessary variable. The output voltage is a slowly varying signal and can be considered invariant during the current switching period, that is to say, ∆Io (k) ≈ 0. Referring to the definition of ∆VC (k + 1), ∆IL (k) can be expanded as ∆IL (k) = C
1 Rτ1 IC1 (t) dt C 0 1 TR1 τ1 ; τ1 + T1 IC2 (t) dt ∆VC2 (k + 1) = C 0 1 RTe τ1 + T1 ; Te IC3 (t) dt ∆VC3 (k + 1) = C τ1 +T1
0; τ1
∆VC1 (k + 1) =
3 X
∆VCi (k + 1)
i=1
∆IL (k) =
(9)
= b1 (k + 1) × τ1 (k + 1) + b0 (k + 1) where b1 (k + 1) = −
E · T1 (k + 1) LC
d∆VC (k) ∆VC (k + 1) − ∆VC (k) =C (15) dt Te
Substituting the reference capacitor voltage VC,ref (k) for the capacitor voltage in the next cycle VC (k + 1), equation (15) can be rewritten as
(8) Accumulating over the three intervals as described in (8), as well as applying the predictive concept to both control variables τ1 and T1 , the overall voltage variation across the filter capacitor can be derived as ∆VC (k + 1) =
(4)
(10)
E ETe 2 T1 (k + 1) + T1 (k + 1) 2LC LC (11) IC (k) I˙C0 (k) 2 + Te + Te C 2C From (9), (10) and (11), the increase in the capacitor voltage is associated to both τ1 and T1 . τ1 can be then expressed as (12). b0 (k + 1) = −
D. Operation of the Proposed Controller Although (6) and (12) offer calculation method for the modulated signals, as a matter of fact, they cannot give indication about the operation procedure including the generation
C (VC,ref (k) − 2VC (k) + VC (k − 1)) Te
(16)
As above, T1 can be obtained using the capacitor voltage prediction approach without any physical current sensor. In (14), the calculation of τ1 does not only depend on T1 , but also on ∆VC (k + 1), I˙C0 (k) and IC (k). The same voltage prediction approach is adopted so as to interpret ∆VC (k + 1) as ∆VC (k + 1) = VC,ref (k) − VC (k) (17) I˙C0 (k) stands for the reduction rate of the capacitor current during τ1 (k). An additional assumption is that Io (k) varies slowly between the adjacent periods. Also we take into consideration that VL (k) = −VC (k) during the interval τ1 (k) because the ground ends of the inductor and capacitor keep at the same potential (see Fig. 1). The following equation applies in this case ∆IC (k) ∆IL (k) VL (k) VC (k) I˙C0 (k) = = = =− (18) ∆t ∆t L L The following analysis provides a method to estimate IC (k). Provided that the inductor current verifies IL (k + 1) = Io (k + 1) + IC (k + 1), it can be expanded as ∆IL (k) = Io (k) − IL (k) + ∆Io (k) + IC (k + 1)
(19)
The aforementioned assumptions are found to be suitable for achieving target. Firstly, ∆Io (k) approximates to zero if there is no significant load variation. Secondly, the predicated
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0; τ1 τ1 ; τ1 + T1 τ1 + T1 ; Te
τ1 (k + 1) =
IC1 (t) = IC (k) + I˙C0 (k) × t IC2 (t) = IC (k) + I˙C0 (k) × τ1 + I˙C1 (k) × t IC3 (t) = IC (k) + I˙C0 (k) × τ1 + I˙C1 (k) × T1 + I˙C0 (k) × t
(7)
T1 (k + 1) L ∆VC (k + 1) − b0 (k + 1) = Te − + × 2IC (k) Te + I˙C0 (k) Te2 − 2C · ∆VC (k + 1) b1 (k + 1) 2 2E · T1 (k + 1) (12)
capacitor current satisfies IC (k + 1) = IC,ref (k) = 0. Therefore, equation (19) can be simplified as
τ1 and T1 . The dynamic ranges and the corresponding effects on τ1 and T1 can be therefore summarized as • The dynamic range of T1 is limited from 0 to Te and permits the adjustment of IL within the margin given in (22); • The dynamic range of τ1 is limited from 0 to Te − T1 and permits the adjustment of VC with the limits given in (23); • The adjustment of VC does not only depend on τ1 but also on T1 , that is to say, in relationship with ∆IL (k). Based on the above analysis, the maximum voltage change occurs if and only if τ1 = 0, and the minimum one achieves at τ1 = Te − T1 . The basic control scheme is given by the results of T1 (6) and τ1 (12). Since it is updated at every switching period, the scheme achieves the reference voltage in its best effort as mentioned above.
∆IL (k) = Io (k) − IL (k)
III. D ITHERED 1-1 MASH Σ-∆ DPWM
Fig. 2.
The operation of the proposed controller
(20)
According to (20), IC (k) can be solved as IC (k) = IL (k) − Io (k) = −∆IL (k)
(21)
where ∆IL (k) has already been obtained in (16). So the above analysis offers a feasible current predictive approach without sensor so as to obtain τ1 . Fig. 2 sums up the operation of the aforementioned current and voltage predictive controller. Besides the fixed converter parameters, basic principles of predictive control are used only with the measured output voltage and the corresponding reference voltage. τ1 and T1 can be generated from the predicted ∆VC (k + 1) and ∆IL (k). E. Dynamic Range of τ1 and T1 According to (6), a range of T1 (k + 1) from 0 to Te leads to the range of the predictive inductor current variation to make it possible to follow VC,ref (k) after each switching period, following Te Te VC (k) < ∆IL (k) < (E − VC (k)) (22) L L The overall influence on VC , here to be regarded as the output voltage Vo , requires an appropriate voltage margin that permits better dynamic performances, particularly, the immunity to the variation of the supply voltage and the tracking of the reference voltage. From (9), (10) and (11), the two extremes are given by (23). As shown in Fig. 2, the values of ∆IL (k) and ∆VC (k) are necessary factors that influence the two control variables −
As discussed in Section II, the proposed controller will generate the required modulated pattern that varies according to the dual-state-variable prediction. The DPWM module operates meanwhile to convert each generated combination pattern of {T1 , τ1 } into a modulated signal so as to control the switching action of the power MOSFETs. In this section, an improved Σ-∆ DPWM will be introduced to maintain noised-shaping effect as the second-order Σ-∆ DPWM [2] as well as to further reduce the idle-tone influence. Σ-∆ modulator for DPWM is regarded as consuming less power than that of delay-line based ones, as well as being more foreseeable and controllable than that of the dithering method [19]. Note that the DC excitation of the Σ-∆ modulator is the steady state requirements associated directly with the converter output. Whereas the inherent periodic sequence in Σ∆ modulator, known as idle-tone, is particularly serious under DC excitation. This situation is more serious when applied to a power stage with high corner frequency which is also the origin of a potential oscillation at the output of the DC-DC converter. According to the power spectrum of existing Σ-∆ modulator devoted to DPWM, higher order modulator features a better idle-tone attenuation, but brings out more complex hardware architecture. Another approach, MASH 1-1 Σ-∆ DPWM proposed by [23] is still suspicious to archive better performance especially in normal quasi-DC input situation. Provided that an artificially binary noise can be cancelled at the output of the MASH DPWM, the input of the quantizer behaves like a noise and therefore the quantization noise of MASH is likely white. In order to further decrease the effect
LI et al.: A DIGITAL DUAL-STATE-VARIABLE PREDICTIVE CONTROLLER FOR HIGH SWITCHING FREQUENCY BUCK CONVERTER WITH IMPROVED Σ-∆ DPWM5
E · Te IC (k) I˙C0 (k) 2 E 2 T1 (k + 1) + T1 (k + 1) + Te + Te 2LC LC C 2C 2 ˙ E · T1 (k + 1) IC (k) IC0 (k) 2 = b1 × (Te − T1 (k + 1)) + b0 = + Te + Te 2LC C 2C
τ1 =Te − T1
∆VC,min
of the idle-tone, a dither generation module, a pseudo-noise (PN) sequence generator, is added to the latter stage of MASH 1-1 DPWM. This dither module consists of a series of shift registers and several XOR gates connecting certain outputs of the shift register. If we denote c [n] the output of the PN dither generator, we have c [n] = ±1 so that c [n] × c [n] = 1. Inspired by [24], an 11-bit PN dither generator is adopted of which the generator polynomial is 10 7 0 . Fig. 3 shows the block diagram of the proposed DMASH 1-1 DPWM. The overall output signal is given by 2 2 1 1 − z −1 D (z) V (z) = U (z) + 1 − z −1 E2 (z) + n−1 (24) where D (z) is the dither signal, E2 (z) is the truncation error of the second stage. For this design, n = 11, and we set m1 = 4 and m2 = 2. The output spectrum of the DC input whose 1 equivalent duty-cycle equals 0.5 + N indicates the idle-tone 2 attenuation effect as shown in Fig. 4. The simulation result is analyzed by the Welch’s method with a Hanning window size of 8192. In Fig. 4, the noise power peaks begin to occur after the corner frequency of the buck converter, here 10.7 kHz. Another power peak at the frequency of the basic idle-tone Fs appears at N −m1 −m2 (see Fig. 4(b)). All the second-order 2 DPWMs have lower idle-tone noise than that of the first-order DPWM. However, compared to the traditional second-order DPWM, no noise attenuation appears in MASH 1-1 DPWM [23]. The proposed DMASH 1-1 DPWM exhibits further idletone attenuation than all the aforementioned architectures. IV. S IMULATION R ESULTS AND S YSTEM A NALYSIS The fixed-point simulations are carried out in Matlab using a non-ideal buck model written in S-function. The buck converter transforms an input voltage of 3 V to an output voltage of 1.5 V. All the circuit parameters have the same values as in the test board. The default switching frequency fs =1 MHz, filter inductor L=4.7 µH, filter capacitor C=22 µF , and the nominal load RL =5 Ω. The equivalent series resistances of the inductor and the capacitor are RI =0.2 Ω and RC =3 mΩ, respectively. As aforementioned in Section II, the proposed controller can generate an asymmetric modulation pattern that is capable of further boosting the dynamic performance than that of traditional current-mode controllers. In order to take a better comparison of the current regulation effect, here we take the predictive dead-beat controller as a reference [14]. Fig. 5 gives the dynamic behavior in the transient states when the load current changes from 0.3 A to 0.5 A. The adopted predictive dead-beat controller is designed to achieve fast response in not only the current loop but also the voltage loop in which appropriate PI parameters assure a relative fast dynamic response. An obvious observation from Fig. 5(a) (d) and (b)
(23)
−50 Power spectrums of regulated output voltage Vo(dB)
∆VC,max = b0 = −
MOD1 MOD2 MASH 1−1 DMASH 1−1 Reference
−100
−150
−200
−250
3
10
4
5
10
6
10
10
Frequency(Hz)
(a)
−130 Power spectrums of regulated output voltage Vo(dB)
τ1 = 0
MOD1 MOD2 MASH 1−1 DMASH 1−1 Reference
−140 −150 −160 −170 −180 −190 −200 −210 4 10
5
10 Frequency(Hz)
(b) Fig. 4. (a) Power spectrums of output voltage Vo using DMASH 1-1 and existing DPWMs (b) Power spectrums in the vicinity of the corner frequency
(e) is that the regulation rate of dual-state-variable predictive control is significantly faster than that of the dead-beat control. Inherent novel regulation variables in the proposed controller can be used to explain this fast convergence phenomenon which is mapped to the modulated switching signals as shown in Fig. 5(c). In steady state, the voltage and current predictive controller generates the optimized switching signal of which the pattern is like the average current-mode controller. While in transient state, it adjusts both the time of voltage jump and duty cycle of the switching signal. In contrast, such performance is not available in dead-beat control. The converter gives a regulated output that ranges from 0.4 to 2.5 V as shown in Fig. 6(a). When the power supply has a disturbance from 3 to 1.6 V, the regulated output voltage is shown in Fig. 6(b). The slope mode test from 0.8 to 1.36 ms shows that the supply voltage must be larger than 1.96 V. A
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Fig. 3.
Proposed DMASH 1-1 DPWM Proposed control (b)
(a)
(c) 3.5
Vo
IL
0.6
2.5
1.5
0.5
voltage (V)
current (A)
voltage (V)
Modulated pulse
3
Vref
0.4
2 1.5 1 0.5
0.3
0 1.495 0.998
1
1.002 time (ms)
0.2 0.998
1.004
1
−3
x 10
1.002 time (ms)
−0.5 0.998
1.004
Dead−beat control (e)
(d)
IL
Vref
1.49
2.5 voltage (V)
current (A)
1.495
−3
x 10
Modulated pulse
3
0.6
1.5
1.004
3.5
Vo
1.505
1.002 time (ms) (f)
0.7
voltage (V)
1
−3
x 10
0.5 0.4
2 1.5 1 0.5
0.3
0 1.485 0.998
1
1.002 time (ms)
0.2 0.998
1.004
1
−3
x 10
1.002 time (ms)
−0.5 0.998
1.004 −3
x 10
1
1.002 time (ms)
1.004 −3
x 10
Fig. 5. Dynamic performance of the proposed control and dead-beat control respectively: Voltage response (a) and (d), inductor current regulation (b) and (e), modulated driving pulse (c) and (f)
very short convergence time shown in the transition mode test of Fig. 6(b) guarantees an excellent performance to reject the power disturbance.
(a) Dynamic responses for the reference voltage variation 2.5
1.5 1 Reference voltage Output voltage
0.5 0
0
0.5 1 1.5 time (ms) (b) Dynamic responses for the supply voltage variation
2
Vo−−Output voltage
1.505 Vo Vin
1.5025 1.5 1.4975 1.495
0.8
1
1.2
1.4 time (ms)
1.6
1.8
2
3.1 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5
Vin−−supply voltage
voltage (V)
2
Fig. 6. (a) Dynamic responses for the reference voltage variation as well as the slope trajectory tracking, (b) Dynamic responses for the supply voltage variation in slope mode and transition mode
V. E XPERIMENTAL R ESULTS A. FPGA Platform As an effective verification and validation tool for ASIC, FPGA allows the development of digital controllers with the aid of rich peripherals [25]. To verify the function and timing issues of the proposed voltage and current predictive controller and proposed DPWM, a high switching frequency low power buck converter is connected to a VIRTEX-II Pro XC2VP30 FPGA with 3.0 V input and 1.5 V output voltage as shown in Fig. 7. The output power of the buck converter prototype ranges from 450 mW to 682 mW over the switching frequency range. Some important system parameters are summarized in Table. I. An open-loop environment is designed to test the proposed DPWM. In terms of design specification, dynamic and steady performance can be obtained through a closed-loop test. B. Test of DPWM
LI et al.: A DIGITAL DUAL-STATE-VARIABLE PREDICTIVE CONTROLLER FOR HIGH SWITCHING FREQUENCY BUCK CONVERTER WITH IMPROVED Σ-∆ DPWM7
Fig. 7. Schematic of the experimental controller prototype for a synchronous buck converter TABLE I PARAMETERS OF THE DIGITALLY CONTROLLED SMPS Buck R L C Vin Vo fs ADC DPWM NDP W M NΣ−∆ fclk
Switching mode power converter Nominal load Inductor Capacitor Input voltage Output voltage Switching frequency Analog to digital Converter DMASH 1-1 DPWM Core DPWM resolution Proposed DPWM resolution DPWM counter frequency
Fig. 8. Regulated output Vo of the experimental converter for a digital ramp from 2047 to 0
Step down 5Ω 4.7 µH 22 µF 3.0 V 1.5 V 4 MHz (up to 10 MHz) 10-bit 11-bit 6-bit 5-bit 64 MHz
1) Steady-state Test: A 6-bit counter-comparator based DPWM, also known as the core DPWM within the proposed DPWM, is adopted as a reference. Fig. 8 shows the LC filtered output of the duty cycle for a manually generated ramp signal from 2047 to 0 that is also the duty cycle sweep change for the 11-bit DPWM. An obvious observation from the results of open-loop DPWM test is that the slope of the proposed DPWM is smoother than that of the core DPWM. As the nature of Σ-∆, it conforms to the noise shaping principal that also leads to the increase in the effective resolution. The integral nonlinearity (INL) and the differential nonlinearity (DNL) are measured with a 61.44 Hz full-scale ramp input. At 61.44 KS/s, 60011 sample points are collected. The measured DNL is within ±0.62 LSB and the INL curve never exceeds +0.55/-0.83 LSB over the 3 V dynamic range. 2) Transient-state Test: Fig. 9 shows an example of the dynamic behavioral characteristic in which there is a transition of equivalent input bins from 2047 to 0. The convergence time for our proposed DMASH 1-1 DPWM is 204 µs that is significantly smaller than that of the first order Σ-∆ DPWM. C. Test of the Proposed Controller As introduced in Section V-A, a buck power stage from 3 V to 1.5 V is constructed and regulated by the proposed FPGA-based digital controller. An external 10-bit ADC converts the output voltage of the buck converter to the digital format so as to verify the closed-loop operation. The ADC specifications, such as resolution and conversion delay, play an important role in the controller performances with respect
Fig. 9. Comparison of the regulated output Vo in transient state using the first order Σ-∆ DPWM and proposed DMASH 1-1 DPWM
to the settling time, the output ripple value and LCO. The used ADC (ADC9203) can guarantee satisfactory steady-state and transient-state performances. Due to frequency limits of the discrete buck architecture, tests are currently performed up to 4 MHz, but can be possibly extended to 10 MHz with an integrated controller IC according to the VHDL-AMS simulation results performed on INCISIV, Cadence. Test of the proposed controller is carried out on the FPGA-platform. The involved dead-beat controller cannot perform at so high switching frequency due to the absence of current sensor. So the dynamic behavior of the proposed controller is compared with that of a PID controller. Considering the tradeoff between the dynamic performance and robustness (modulus and delay margins) of a PID controller, the pulsation ωcr is set to 15 times the open-loop pulsation ω0 corresponding to 1475100 rad/s with the closed-loop damping ratio ζcr = 0.7. The discrete-time PID controller, which is tuned to be optimal can then be written as d[n] =0.784 × d[n − 1] + 0.216 × d[n − 2] + 8.366 × e[n] − 16.244 × e[n − 1] + 7.940 × e[n − 2] (25) where d[n] is the discrete value of the PWM output, e[n] is the discrete value of the error signal between the reference
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(a)
Fig. 11. Transient output voltage at 4 MHz switching frequency during load change from 0.45 A to 0.3 A (R: from 3.3 Ω to 5 Ω) using proposed controller
proposed controller operating at different switching frequencies are reported in Table. III. TABLE III DYNAMIC P ERFORMANCE OF THE P ROPOSED C ONTROLLER UNDER A L OAD P ERTURBATION BETWEEN 0.3 A AND 0.45 A Switching frequency
(b) Fig. 10. Transient output voltage at 1 MHz switching frequency during load change from 0.3 A to 0.45 A (R: from 5 Ω to 3.3 Ω) using (a) proposed controller (b) PID controller
voltage Vref and the regulated output Vo , d[n − i] and e[n − i] are respectively the PWM output and the error values at the ith-cycles prior to the current cycle. Experimental results are presented in Fig. 10. Unlike the predictive dead-beat controller, the two controllers can operate without the aid of a current sensor. The PID controller can support up to 1 MHz switching frequency with the same testbench of the proposed controller. Fig. 10(a) and (b) show the transient output voltage response operating at 1 MHz switching frequency when the load suddenly varies from 0.3 A to 0.45 A (5 Ω to 3.3 Ω). Comparisons of design parameters and operation performances of the two controllers are summarized in Table. II. The proposed controller shows better dynamic performances than the PID controller. It exhibits more than 5 times shorter dynamic response and about half the overshoot voltage. All these improvements only cost less than 35% extra hardware resources. So for a high switching frequency buck converter, the dual-state-variable predictive controller is a better tradeoff taking into account hardware implementation and dynamic performance. Fig. 11 shows the dynamic response with the load current transient from 0.45 A to 0.3 A operating at 4 MHz switching frequency. With the increase in the switching frequency, the voltage and current predictive controller enables faster response and results with relatively lower overshoot voltage. Detailed results related to the dynamic performances of the
1 MHz 2 MHz 4 MHz
Settling Positive perturbation (µs)
Time Negative perturbation (µs)
Negative overshoot
Positive overshoot
(mV)
(mV)
43.8 31.5 23.8
44.0 32.3 21.4
44.0 35.0 30.7
17.4 15.6 24.4
The FPGA-based experimental results show that the proposed controller is a good candidate for an ASIC implementation. In order to make full use of standard digital CMOS process, each parameter must be tunable in order to cancel the nonideal factor influence. So using the statemachine based parameter generator as shown in Fig. 12, the controller is assured to work either adopting fine-tuning to offer immunization to the noise perturbation, or importing parameters for higher switching frequency. The parameter adaptive control method can also be constructed based on this block. In order to implement the programmable parameters that introduce an adjustable control effect, a serial data receiver is connected to din so as to provide the control parameters. The parameter read-in module has its own synchronous clock (clk) and reset (rest) signals. The ADDR enables each shift-register providing parameters for a designated controller. Another advantage of integrating the serial to parallel module is its cancellation of the data-path between shift-register and proposed controller that largely saves hardware resources. VI. C ONCLUSION This paper presents a fully synthesizable DPWM-based dual-state-variable predictive controller for low-power and high-frequency (MHz and over) SMPS. The architecture contains a novel control algorithm and a DMASH 1-1 DPWM. The proposed controller achieves a constant switching frequency with better static and dynamic performances, as well as good immunity to the power and load perturbations. Its
LI et al.: A DIGITAL DUAL-STATE-VARIABLE PREDICTIVE CONTROLLER FOR HIGH SWITCHING FREQUENCY BUCK CONVERTER WITH IMPROVED Σ-∆ DPWM9
TABLE II A G ENERAL C OMPARISON WITH PID C ONTROLLER O PERATING AT 1 MH Z S WITCHING F REQUENCY
Fig. 12.
Controller type
Multiplier amount
Adder amount
Tunable parameters amount
Total equivalent gates
Settling time 0.3 A →0.45 A (µs)
Settling time 0.45 A→0.3 A (µs)
Negative overshoot
Positive overshoot
(mV)
(mV)
Proposed controller PID controller
5 5
7 4
3 5
6997 5059
43.8 235.0
44.0 232.0
44.0 75.2
17.4 40.4
Block diagram of the parameter read-in module
hardware implementation is quite simple: only few memories, multipliers and adders in FPGA/ASIC are needed. The DMASH 1-1 DPWM takes the advantage of the noise-shaping concept and implements a MASH architecture, as well as combines a dither block in order to further eliminate the idle-tone effects. The FPGA implementation is tested along with a lab-scale buck converter (step-down SMPS) where the switching frequency is limited to 4 MHz. The experimental results validate the functionality and performances of the proposed DMASH 1-1 DPWM-based discrete voltage and current predictive controller and confirm the feasibility of an ASIC using a peripheral to program parameters for specific controllers. R EFERENCES [1] Y.-F. Liu, E. Meyer, and X. Liu, “Recent developments in digital control strategies for DC/DC switching power converters,” IEEE Trans. Power Electron., vol. 24, no. 11, pp. 2567–2577, Nov. 2009. [2] Z. Lukic, N. Rahman, and A. Prodic, “Multibit Σ-∆ PWM digital controller IC for DC-DC converters operating at switching frequencies beyond 10 MHz,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1693–1707, Sep. 2007. [3] F. Luo and D. Ma, “Design of digital tri-mode adaptive-output buckboost power converter for power-efficient integrated systems,” IEEE Trans. Ind. Electron., vol. 57, no. 6, pp. 2151–2160, Jun. 2010. [4] B.-Y. Chen and Y.-S. Lai, “New digital-controlled technique for battery charger with constant current and voltage control without current feedback,” IEEE Trans. Ind. Electron., vol. 59, no. 3, pp. 1545–1553, Mar. 2012. [5] F. Gonzalez-Espin, E. Figueres, G. Garcera, R. Gonzalez-Medina, and M. Pascual, “Measurement of the loop gain frequency response of digitally controlled power converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2785–2796, Aug. 2010. [6] V. Yousefzadeh, A. Babazadeh, B. Ramachandran, E. Alarcon, L. Pao, and D. Maksimovic, “Proximate time-optimal digital control for synchronous buck DC-DC converters,” IEEE Trans. Power Electron., vol. 23, no. 4, pp. 2018–2026, Jul. 2008. [7] E. Vidal-Idiarte, C. E. Carrejo, J. Calvente, Marti, and L. nez Salamero, “Two-loop digital sliding mode control of DC-DC power converters based on predictive interpolation,” IEEE Trans. Ind. Electron., vol. 58, no. 6, pp. 2491–2501, Jun. 2011.
[8] S. Saggini, W. Stefanutti, P. Mattavelli, and A. Carrera, “Efficiency estimation in digitally-controlled DC-DC buck converters based on single current sensing,” in Proc. IEEE PESC Conf., Jun. 2008, pp. 3581– 3586. [9] Z. Zhao and A. Prodic, “Limit-cycle oscillations based auto-tuning system for digitally controlled DC-DC power supplies,” IEEE Trans. Power Electron., vol. 22, no. 6, pp. 2211–2222, Nov. 2007. [10] W. Stefanutti, P. Mattavelli, S. Saggini, and M. Ghioni, “Autotuning of digitally controlled DC-DC converters based on relay feedback,” IEEE Trans. Power Electron., vol. 22, no. 1, pp. 199–207, Jan. 2007. [11] E. Zurita-Bustamante, J. Linares-Flores, E. Guzman-Ramirez, and H. Sira-Ramirez, “A comparison between the GPI and PID controllers for the stabilization of a DC-DC buck converter: A field programmable gate array implementation,” IEEE Trans. Ind. Electron., vol. 58, no. 11, pp. 5251–5262, Nov. 2011. [12] V. Mummadi, “Design of robust digital PID controller for H-Bridge softswitching boost converter,” IEEE Trans. Ind. Electron., vol. 58, no. 7, pp. 2883–2897, Jul. 2011. [13] G. Zhou, J. Xu, and Y. Jin, “Elimination of subharmonic oscillation of digital-average-current-controlled switching DC-DC converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2904–2907, Aug. 2010. [14] S. Bibian and H. Jin, “High performance predictive dead-beat digital controller for DC power supplies,” IEEE Trans. Power Electron., vol. 17, no. 3, pp. 420–427, May. 2002. [15] Y. Qiu, H. Liu, and X. Chen, “Digital average current-mode control of PWM DC-DC converters without current sensors,” IEEE Trans. Ind. Electron., vol. 57, no. 5, pp. 1670–1677, May 2010. [16] A. Malinowski and H. Yu, “Comparison of embedded system design for industrial applications,” IEEE Trans. Ind. Informat., vol. 7, no. 2, pp. 244–254, May 2011. [17] M. P. Kazmierkowski, M. Jasinski, and G. Wrona, “DSP-based control of grid-connected power converters operating under grid distortions,” IEEE Trans. Ind. Informat., vol. 7, no. 2, pp. 204–211, May 2011. [18] C.-A. Yeh and Y.-S. Lai, “Digital pulsewidth modulation technique for a synchronous buck DC/DC converter to reduce switching frequency,” IEEE Trans. Ind. Electron., vol. 59, no. 1, pp. 550–561, Jan. 2012. [19] A. Peterchev and S. Sanders, “Quantization resolution and limit cycling in digitally controlled PWM converters,” IEEE Trans. Power Electron., vol. 18, no. 1, pp. 301–308, Jan. 2003. [20] H. Peng, D. Maksimovic, A. Prodic, and E. Alarcon, “Modeling of quantization effects in digitally controlled DC-DC converters,” in Proc. IEEE PESC Conf., vol. 6, Jun. 2004, pp. 4312–4318. [21] J. Xiao, A. Peterchev, J. Zhang, and S. Sanders, “A 4-µA quiescentcurrent dual-mode digitally controlled buck converter IC for cellular phone applications,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2342–2348, Dec. 2004. [22] V. Yousefzadeh, T. Takayama, and D. Maksimovi, “Hybrid DPWM with digital delay-locked loop,” in Proc. IEEE COMPEL Works., Jul. 2006, pp. 142–148. [23] S. Guo, X. Lin-Shi, B. Allard, B. Li, Y. Gao, and Y. Ruan, “Highresolution digital PWM controller for high-frequency low-power SMPS,” in Proc. EPE Conf., Sep. 2009, pp. 1–9. [24] V. Gonzalez-Diaz, M. Garcia-Andrade, G. Flores-Verdad, and F. Maloberti, “Efficient dithering in MASH Sigma-Delta modulators for fractional frequency synthesizers,” IEEE Trans. Circuits Syst. I, vol. 57, no. 9, pp. 2394–2403, Sep. 2010. [25] E. Monmasson, L. Idkhajine, M. N. Cirstea, I. Bahri, A. Tisan, and M. W. Naouar, “FPGAs in industrial control applications,” IEEE Trans. Ind. Informat., vol. 7, no. 2, pp. 224–243, May 2011.
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Bo Li received the B.Sc. and M.Sc. degrees from the Department of Electronics Engineering, Beijing Jiaotong University, China, in 2005 and 2008, respectively. He is currently working towards the Ph.D. degree at Amp`ere-Lab, INSA Lyon (Institut National des Sciences Appliqu´ees de Lyon), France. His current research interests include digital control techniques applied to high frequency switchedmode power supply, low power digital and mixedsignal IC design.
Xuefang Lin-Shi (M’09) received the Ph.D. degree in applied computer science and automatic in 1992 from INSA Lyon (Institut National des Sciences Appliqu´ees de Lyon), France. Since 1993, she has been with the Electrical Engineering department of INSA Lyon, where she is currently a professor. She is now with Amp`ere Laboratory in Lyon. Her research interests concern control applied to electrical drives and power electronics system.
Bruno Allard (M’93-SM’02) was born in 1965. He received the M.Sc. and Ph.D. degrees in engineering from the Institut National des Sciences Applique´ees de Lyon (INSA Lyon), Lyon, France, in 1989 and 1992, respectively. He is a Full Professor at Amp`ereLab, INSA Lyon, Lyon where he is currently the Head Manager. He has led numerous industrial and academic projects. He is the author or coauthor of more than 80 papers and 100 international conference contributions. His research interests include the integration of power systems, either hybrid or monolithic, power semiconductor device modeling and characterization, power electronic system design and low-power monolithic converter design.
Jean-Marie R´etif received the Ph.D. degree in tuning control from the Universit´e Claude Bernard Lyon I, Lyon, France, in 1979. He was with the Energetic and Control Laboratory, Institut National des Sciences Appliqu´ees de Lyon (INSA Lyon), France, where he dealt with different subjects such as process control and optimization of solar heating. Since 1979, he has been with the Amp`ere Laboratory, INSA Lyon, where he has been working on control in the field of electrical engineering.
1
A Digital Dual-state-variable Predictive Controller for High Switching Frequency Buck Converter with Improved Σ-∆ DPWM Bo Li, Xuefang Lin-Shi, Member, IEEE, Bruno Allard, Senior Member, IEEE, Jean-Marie R´etif
Abstract—This paper presents a novel digital controller for the high switching frequency buck converter based on the principle of predictive control. Compared to traditional current-mode predictive controller, the prediction of the inductor current and the output voltage are performed at the same time by adding a control variable to the DPWM signal that can dynamically adjust the time of voltage jump. It accelerates the convergence rate during transient states, while inherently preserving the rejection of power and reference perturbations. The analysis of controller’s operation illustrates the dual-state-variable predictive attributes that lead to the digital implementation. To further enhance the power efficiency of the controller, an 1-1 MASH Σ-∆ DPWM with a feasible dither generation module is proposed to restrain the idle-tone effects without deteriorating the closed-loop stability as well as to preserve reasonable cost in silicon area. Experimental results verify closed-loop operations at switching frequency up to 4 MHz only limited by the discrete buck converter. The converter is well regulated over a large output range with excellent dynamic performances. Index Terms—DC-DC converter, switched-mode power supply, predictive control, digital control, digital pulse-width-modulator.
I. I NTRODUCTION
D
IGITAL control for low-power switched-mode power supplies (SMPS) opens up the possibility of the integration of high switching frequency power converter systems [1]–[5]. Compared to analog counterparts, the digital approach allows the development of controllers which cannot be realized in the analog domain. For example, specific nonlinear controllers can boost the dynamic response to the perturbations from the power stage [6], [7]; the active efficiency monitoring and the digital autotuning can improve the control performances [8]–[10]. Moreover digital control exhibits inherent advantages with respect to integration, for instance, its insensitivity to the process-voltage-temperature (PVT) variations, design reuse and reprogrammability that accelerates time-tomarket (TTM). Digital controller is therefore regarded as an attractive candidate with better performances than the analog counterparts. Manuscript received October 24, 2011. Accepted for publication March 22, 2012. c 2009 IEEE. Personal use of this material is permitted. Copyright However, permission to use this material for any other purposes must be obtained from the IEEE by sending a request to [email protected] Bo Li, Xuefang Lin-Shi, Bruno Allard and Jean-Marie R´etif are with the Universit´e de Lyon, Amp`ere, INSA Lyon, CNRS UMR 5005, Villeurbanne, France, F-69621 (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).
Thanks to the approach based on the look-up table (LUT), the implementation of the linear controller, notably the voltage-mode PID controller, benefits most in terms of the cost of the hardware resource [2], [11], [12]. However, their performances generally depend on the operating point, so that the presence of parasitic elements, time-varying loads and variable supply voltages can deteriorate the control behavior. With the knowledge of inductor current, a double closed-loop control method is often adopted with an outer voltage loop and an inner current loop. This method has proven to be effective with inherent advantages including overcurrent protection and excellent audiosusceptibility [13], [14]. Dead-beat control [14] and current programmed control [13], [15] are widely used for the inner current loop. These control algorithms calculate the duty cycle according to a converter discrete model at every sampling period to make sure the inductor current tracks the reference in the next period. The current reference is generated by a classical voltage control loop. So the prediction is only made for the current loop but not for the voltage loop that restricts the dynamic performances. Moreover, a large part of these solutions have been still devoted to performed on Digital Signal Processor (DSP) or other processors in medium to high power application [16], [17]. Generally these digital control systems present sufficient resources to accommodate the modest switching frequency of the converter in the range of kHz. In these medium to high power application systems, the size is not the primary focus, neither the power consumption. For low-power SMPS application, in order to reduce the size of passive components, the switching frequency can reach MHz and over. To the authors’ knowledge, predictive control has never been employed in the design of a digital control for such highswitching frequency SMPS. However, the target applications of the proposed controller cover the typical operations of battery-powered embedded systems in power range from 100 mW to several watts. In this paper, a current and voltage predictive controller is proposed for a high-switching frequency SMPS. Unlike the double closed-loop control method, the prediction of both the inductor current and the output voltage is performed at the same time by adding an extra control parameter τ1 which corresponds to an interval between the beginning of each switching period and the time of high voltage (see Fig. 1). The proposed controller preserves the merits of the predictive current control and allows to further enhance the dynamic performances while maintaining an excellent rejection of
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adjust control parameters, this paper also discusses an online parameter tuning module giving the possibility that allows an extended compatibility to higher switching frequency. This paper is organized as follows. Section II gives the details of the proposed current and voltage predicitve control. In Section III, a DMASH 1-1 DPWM is described. Simulation and experimental results are discussed in Section IV and V. A conclusion is drawn in Section VI. II. C URRENT AND VOLTAGE P REDICTIVE C ONTROL A. Discrete Model of the Buck Converter
Fig. 1. (a) Block diagram of the buck converter (b) A sample of corresponding current and voltage predictive control waveform
the power supply perturbations, and a robust and automatic switching error correction. Unlike the controller in analog domain, the implementation of a digital controller requires an analog-to-digital converter (ADC) and a digital pulse-width-modulator (DPWM) [18] for which a particular attention must be payed to avoid limit cycle oscillations (LCO) [19], [20]. The critical issue of ADC is to achieve sufficient resolution while to maintain low power consumption. Delay-line derived architectures [21], [22] are feasible solutions. All the proposed ADCs only measure the vicinity of the reference voltage employing the so-called windows concept. The design of ADCs does not fall within the scope of this paper. A high-resolution DPWM is another necessary condition to avoid LCO. From the viewpoint of time domain, many delay-line based architectures are proposed to generate shorter interval than the period of the basic system clock without the need of unachievable clock by counter-comparator architecture [21]. However, these approaches usually depend on a series of tight logic cells that exponentially increase with the increase of DPWM resolution. Frequency domain is another appropriate access to achieve DPWM with sufficient resolution using noise-shaping concept. The effective resolution is achieved by the Σ-∆ modulator through several switching periods without sacrificing larger hardware resource than that of the delay-line method [2]. However the slow convergence due to a low frequency periodic behavior in the lower-order Σ-∆ DPWM, known as idle-tone, produces low-frequency noise in the power stage [2]. The MASH type Σ-∆ DPWM appears to be an effective trade-off between the idle-tone attenuation and the cost of hardware, but proves no amelioration in noise-shaping effect [23]. In this paper, a dithered 1-1 MASH Σ-∆ structure (DMASH 11) is proposed to be a feasible candidate in terms of hardware cost and effective resolution. In addition, as an interface to
As shown in Fig. 1(a), the supply voltage is noted as E. The switched voltage is filtered by an LC tank to provide a constant output Vo to the load RL . Choosing the inductor current IL and the capacitor voltage as the state variable x (t) = , VC the state equations of the buck converter can be written as 1 1 0 0 −L (1) x˙ (t) = 1 x (t) + L 1 u (t) 0 − 0 C C 1 0 y (t) = x (t) (2) 0 1 0 where the input variable u (t) = when the PMOSFET Io E is ON, u (t) = when the NMOSFET is ON. Io Assuming only a small variation of the output current Io during a switching period Te , the input variable can be considered to be constant during Te . So the discrete-time model of the buck converter limited to the first-order can be expressed as Te Te Te2 1 −L 2LC x (k + 1) = T u (k) (3) x (k) + TL2 Te e e 1 − C 2LC C The description of the system state-space allows to analyse the behavior of the buck converter. The aim of the proposed controller is to make the inductor current and the capacitor voltage at the sampling point (k + 1) Te equal to the reference current and voltage at the end of corresponding switching period, respectively. B. Calculation of the Current Variation The PWM waveform pattern of the proposed dual-statevariable predictive control is shown in Fig. 1(b). The switching period is divided into three parts. Providing that all the current variations are defined as ∆Ii (k) = Ii (k + 1) − Ii (k), the change in IL in two adjacent cycles, ∆IL (k), is derived as (4). So the total change in IL in the current cycle is ∆IL (k) =
3 X i=1
∆ILi (k) =
1 (E · T1 (k) − VC (k) · Te ) (5) L
From (5), we can derived that ∆IL (k) is related to T1 and the capacitor voltage VC (k). That is to say, T1 in the next
LI et al.: A DIGITAL DUAL-STATE-VARIABLE PREDICTIVE CONTROLLER FOR HIGH SWITCHING FREQUENCY BUCK CONVERTER WITH IMPROVED Σ-∆ DPWM3
0;
τ1 ; τ1 + T1
τ1 + T1 ; Te
τ1
1 1 R τ1 (−VC (k)) dt = − VC (k) τ1 0 L L 1 1 R T1 (E − V (k)) dt = − (−ET1 + VC (k) T1 ) ∆IL2 (k) = C 0 L L 1 1 R Te (VC (k) Te − VC (k) τ1 − VC (k) T1 ) (−V (k)) dt = − ∆IL3 (k) = C τ +T 1 1 L L ∆IL1 (k) =
switching period can be, therefore, predicted from ∆IL (k) which obliges that the inductor current in the next cycle is compensated with the amount of ∆IL (k). So T1 (k + 1) is represented as T1 (k + 1) =
L Te ∆IL (k) + VC (k) E E
(6)
C. Calculation of the Voltage Variation From the perspective of a current variation, the three parts in one switching cycle can be expressed as (7) where I˙C0 (k) and I˙C1 (k) are the change rates of the capacitor current during the interval of τ1 and T1 respectively. IC (k) denotes the capacitor current at the starting point of each period. Here we define the capacitor voltage variation as ∆VC (k + 1) = VC (k + 1) − VC (k). The corresponding variation of the capacitor voltage in each switching period is, therefore, described as
of the predictive current and voltage. In order to simplify the analysis, (6) and (12) are represented respectively as T1 (k + 1) = f (∆IL (k) , VC (k)) (13) τ1 (k + 1) = g T1 (k + 1) , IC (k) , I˙C0 (k) , ∆VC (k + 1) (14) In order to obtain T1 by (13), VC (k) and ∆IL (k) are necessary values. If we ignore the capacitor ESR, the output voltage can be considered as the required VC (k) so that it can be obtained at every switching period. ∆IL (k) is another necessary variable. The output voltage is a slowly varying signal and can be considered invariant during the current switching period, that is to say, ∆Io (k) ≈ 0. Referring to the definition of ∆VC (k + 1), ∆IL (k) can be expanded as ∆IL (k) = C
1 Rτ1 IC1 (t) dt C 0 1 TR1 τ1 ; τ1 + T1 IC2 (t) dt ∆VC2 (k + 1) = C 0 1 RTe τ1 + T1 ; Te IC3 (t) dt ∆VC3 (k + 1) = C τ1 +T1
0; τ1
∆VC1 (k + 1) =
3 X
∆VCi (k + 1)
i=1
∆IL (k) =
(9)
= b1 (k + 1) × τ1 (k + 1) + b0 (k + 1) where b1 (k + 1) = −
E · T1 (k + 1) LC
d∆VC (k) ∆VC (k + 1) − ∆VC (k) =C (15) dt Te
Substituting the reference capacitor voltage VC,ref (k) for the capacitor voltage in the next cycle VC (k + 1), equation (15) can be rewritten as
(8) Accumulating over the three intervals as described in (8), as well as applying the predictive concept to both control variables τ1 and T1 , the overall voltage variation across the filter capacitor can be derived as ∆VC (k + 1) =
(4)
(10)
E ETe 2 T1 (k + 1) + T1 (k + 1) 2LC LC (11) IC (k) I˙C0 (k) 2 + Te + Te C 2C From (9), (10) and (11), the increase in the capacitor voltage is associated to both τ1 and T1 . τ1 can be then expressed as (12). b0 (k + 1) = −
D. Operation of the Proposed Controller Although (6) and (12) offer calculation method for the modulated signals, as a matter of fact, they cannot give indication about the operation procedure including the generation
C (VC,ref (k) − 2VC (k) + VC (k − 1)) Te
(16)
As above, T1 can be obtained using the capacitor voltage prediction approach without any physical current sensor. In (14), the calculation of τ1 does not only depend on T1 , but also on ∆VC (k + 1), I˙C0 (k) and IC (k). The same voltage prediction approach is adopted so as to interpret ∆VC (k + 1) as ∆VC (k + 1) = VC,ref (k) − VC (k) (17) I˙C0 (k) stands for the reduction rate of the capacitor current during τ1 (k). An additional assumption is that Io (k) varies slowly between the adjacent periods. Also we take into consideration that VL (k) = −VC (k) during the interval τ1 (k) because the ground ends of the inductor and capacitor keep at the same potential (see Fig. 1). The following equation applies in this case ∆IC (k) ∆IL (k) VL (k) VC (k) I˙C0 (k) = = = =− (18) ∆t ∆t L L The following analysis provides a method to estimate IC (k). Provided that the inductor current verifies IL (k + 1) = Io (k + 1) + IC (k + 1), it can be expanded as ∆IL (k) = Io (k) − IL (k) + ∆Io (k) + IC (k + 1)
(19)
The aforementioned assumptions are found to be suitable for achieving target. Firstly, ∆Io (k) approximates to zero if there is no significant load variation. Secondly, the predicated
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0; τ1 τ1 ; τ1 + T1 τ1 + T1 ; Te
τ1 (k + 1) =
IC1 (t) = IC (k) + I˙C0 (k) × t IC2 (t) = IC (k) + I˙C0 (k) × τ1 + I˙C1 (k) × t IC3 (t) = IC (k) + I˙C0 (k) × τ1 + I˙C1 (k) × T1 + I˙C0 (k) × t
(7)
T1 (k + 1) L ∆VC (k + 1) − b0 (k + 1) = Te − + × 2IC (k) Te + I˙C0 (k) Te2 − 2C · ∆VC (k + 1) b1 (k + 1) 2 2E · T1 (k + 1) (12)
capacitor current satisfies IC (k + 1) = IC,ref (k) = 0. Therefore, equation (19) can be simplified as
τ1 and T1 . The dynamic ranges and the corresponding effects on τ1 and T1 can be therefore summarized as • The dynamic range of T1 is limited from 0 to Te and permits the adjustment of IL within the margin given in (22); • The dynamic range of τ1 is limited from 0 to Te − T1 and permits the adjustment of VC with the limits given in (23); • The adjustment of VC does not only depend on τ1 but also on T1 , that is to say, in relationship with ∆IL (k). Based on the above analysis, the maximum voltage change occurs if and only if τ1 = 0, and the minimum one achieves at τ1 = Te − T1 . The basic control scheme is given by the results of T1 (6) and τ1 (12). Since it is updated at every switching period, the scheme achieves the reference voltage in its best effort as mentioned above.
∆IL (k) = Io (k) − IL (k)
III. D ITHERED 1-1 MASH Σ-∆ DPWM
Fig. 2.
The operation of the proposed controller
(20)
According to (20), IC (k) can be solved as IC (k) = IL (k) − Io (k) = −∆IL (k)
(21)
where ∆IL (k) has already been obtained in (16). So the above analysis offers a feasible current predictive approach without sensor so as to obtain τ1 . Fig. 2 sums up the operation of the aforementioned current and voltage predictive controller. Besides the fixed converter parameters, basic principles of predictive control are used only with the measured output voltage and the corresponding reference voltage. τ1 and T1 can be generated from the predicted ∆VC (k + 1) and ∆IL (k). E. Dynamic Range of τ1 and T1 According to (6), a range of T1 (k + 1) from 0 to Te leads to the range of the predictive inductor current variation to make it possible to follow VC,ref (k) after each switching period, following Te Te VC (k) < ∆IL (k) < (E − VC (k)) (22) L L The overall influence on VC , here to be regarded as the output voltage Vo , requires an appropriate voltage margin that permits better dynamic performances, particularly, the immunity to the variation of the supply voltage and the tracking of the reference voltage. From (9), (10) and (11), the two extremes are given by (23). As shown in Fig. 2, the values of ∆IL (k) and ∆VC (k) are necessary factors that influence the two control variables −
As discussed in Section II, the proposed controller will generate the required modulated pattern that varies according to the dual-state-variable prediction. The DPWM module operates meanwhile to convert each generated combination pattern of {T1 , τ1 } into a modulated signal so as to control the switching action of the power MOSFETs. In this section, an improved Σ-∆ DPWM will be introduced to maintain noised-shaping effect as the second-order Σ-∆ DPWM [2] as well as to further reduce the idle-tone influence. Σ-∆ modulator for DPWM is regarded as consuming less power than that of delay-line based ones, as well as being more foreseeable and controllable than that of the dithering method [19]. Note that the DC excitation of the Σ-∆ modulator is the steady state requirements associated directly with the converter output. Whereas the inherent periodic sequence in Σ∆ modulator, known as idle-tone, is particularly serious under DC excitation. This situation is more serious when applied to a power stage with high corner frequency which is also the origin of a potential oscillation at the output of the DC-DC converter. According to the power spectrum of existing Σ-∆ modulator devoted to DPWM, higher order modulator features a better idle-tone attenuation, but brings out more complex hardware architecture. Another approach, MASH 1-1 Σ-∆ DPWM proposed by [23] is still suspicious to archive better performance especially in normal quasi-DC input situation. Provided that an artificially binary noise can be cancelled at the output of the MASH DPWM, the input of the quantizer behaves like a noise and therefore the quantization noise of MASH is likely white. In order to further decrease the effect
LI et al.: A DIGITAL DUAL-STATE-VARIABLE PREDICTIVE CONTROLLER FOR HIGH SWITCHING FREQUENCY BUCK CONVERTER WITH IMPROVED Σ-∆ DPWM5
E · Te IC (k) I˙C0 (k) 2 E 2 T1 (k + 1) + T1 (k + 1) + Te + Te 2LC LC C 2C 2 ˙ E · T1 (k + 1) IC (k) IC0 (k) 2 = b1 × (Te − T1 (k + 1)) + b0 = + Te + Te 2LC C 2C
τ1 =Te − T1
∆VC,min
of the idle-tone, a dither generation module, a pseudo-noise (PN) sequence generator, is added to the latter stage of MASH 1-1 DPWM. This dither module consists of a series of shift registers and several XOR gates connecting certain outputs of the shift register. If we denote c [n] the output of the PN dither generator, we have c [n] = ±1 so that c [n] × c [n] = 1. Inspired by [24], an 11-bit PN dither generator is adopted of which the generator polynomial is 10 7 0 . Fig. 3 shows the block diagram of the proposed DMASH 1-1 DPWM. The overall output signal is given by 2 2 1 1 − z −1 D (z) V (z) = U (z) + 1 − z −1 E2 (z) + n−1 (24) where D (z) is the dither signal, E2 (z) is the truncation error of the second stage. For this design, n = 11, and we set m1 = 4 and m2 = 2. The output spectrum of the DC input whose 1 equivalent duty-cycle equals 0.5 + N indicates the idle-tone 2 attenuation effect as shown in Fig. 4. The simulation result is analyzed by the Welch’s method with a Hanning window size of 8192. In Fig. 4, the noise power peaks begin to occur after the corner frequency of the buck converter, here 10.7 kHz. Another power peak at the frequency of the basic idle-tone Fs appears at N −m1 −m2 (see Fig. 4(b)). All the second-order 2 DPWMs have lower idle-tone noise than that of the first-order DPWM. However, compared to the traditional second-order DPWM, no noise attenuation appears in MASH 1-1 DPWM [23]. The proposed DMASH 1-1 DPWM exhibits further idletone attenuation than all the aforementioned architectures. IV. S IMULATION R ESULTS AND S YSTEM A NALYSIS The fixed-point simulations are carried out in Matlab using a non-ideal buck model written in S-function. The buck converter transforms an input voltage of 3 V to an output voltage of 1.5 V. All the circuit parameters have the same values as in the test board. The default switching frequency fs =1 MHz, filter inductor L=4.7 µH, filter capacitor C=22 µF , and the nominal load RL =5 Ω. The equivalent series resistances of the inductor and the capacitor are RI =0.2 Ω and RC =3 mΩ, respectively. As aforementioned in Section II, the proposed controller can generate an asymmetric modulation pattern that is capable of further boosting the dynamic performance than that of traditional current-mode controllers. In order to take a better comparison of the current regulation effect, here we take the predictive dead-beat controller as a reference [14]. Fig. 5 gives the dynamic behavior in the transient states when the load current changes from 0.3 A to 0.5 A. The adopted predictive dead-beat controller is designed to achieve fast response in not only the current loop but also the voltage loop in which appropriate PI parameters assure a relative fast dynamic response. An obvious observation from Fig. 5(a) (d) and (b)
(23)
−50 Power spectrums of regulated output voltage Vo(dB)
∆VC,max = b0 = −
MOD1 MOD2 MASH 1−1 DMASH 1−1 Reference
−100
−150
−200
−250
3
10
4
5
10
6
10
10
Frequency(Hz)
(a)
−130 Power spectrums of regulated output voltage Vo(dB)
τ1 = 0
MOD1 MOD2 MASH 1−1 DMASH 1−1 Reference
−140 −150 −160 −170 −180 −190 −200 −210 4 10
5
10 Frequency(Hz)
(b) Fig. 4. (a) Power spectrums of output voltage Vo using DMASH 1-1 and existing DPWMs (b) Power spectrums in the vicinity of the corner frequency
(e) is that the regulation rate of dual-state-variable predictive control is significantly faster than that of the dead-beat control. Inherent novel regulation variables in the proposed controller can be used to explain this fast convergence phenomenon which is mapped to the modulated switching signals as shown in Fig. 5(c). In steady state, the voltage and current predictive controller generates the optimized switching signal of which the pattern is like the average current-mode controller. While in transient state, it adjusts both the time of voltage jump and duty cycle of the switching signal. In contrast, such performance is not available in dead-beat control. The converter gives a regulated output that ranges from 0.4 to 2.5 V as shown in Fig. 6(a). When the power supply has a disturbance from 3 to 1.6 V, the regulated output voltage is shown in Fig. 6(b). The slope mode test from 0.8 to 1.36 ms shows that the supply voltage must be larger than 1.96 V. A
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IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS
Fig. 3.
Proposed DMASH 1-1 DPWM Proposed control (b)
(a)
(c) 3.5
Vo
IL
0.6
2.5
1.5
0.5
voltage (V)
current (A)
voltage (V)
Modulated pulse
3
Vref
0.4
2 1.5 1 0.5
0.3
0 1.495 0.998
1
1.002 time (ms)
0.2 0.998
1.004
1
−3
x 10
1.002 time (ms)
−0.5 0.998
1.004
Dead−beat control (e)
(d)
IL
Vref
1.49
2.5 voltage (V)
current (A)
1.495
−3
x 10
Modulated pulse
3
0.6
1.5
1.004
3.5
Vo
1.505
1.002 time (ms) (f)
0.7
voltage (V)
1
−3
x 10
0.5 0.4
2 1.5 1 0.5
0.3
0 1.485 0.998
1
1.002 time (ms)
0.2 0.998
1.004
1
−3
x 10
1.002 time (ms)
−0.5 0.998
1.004 −3
x 10
1
1.002 time (ms)
1.004 −3
x 10
Fig. 5. Dynamic performance of the proposed control and dead-beat control respectively: Voltage response (a) and (d), inductor current regulation (b) and (e), modulated driving pulse (c) and (f)
very short convergence time shown in the transition mode test of Fig. 6(b) guarantees an excellent performance to reject the power disturbance.
(a) Dynamic responses for the reference voltage variation 2.5
1.5 1 Reference voltage Output voltage
0.5 0
0
0.5 1 1.5 time (ms) (b) Dynamic responses for the supply voltage variation
2
Vo−−Output voltage
1.505 Vo Vin
1.5025 1.5 1.4975 1.495
0.8
1
1.2
1.4 time (ms)
1.6
1.8
2
3.1 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5
Vin−−supply voltage
voltage (V)
2
Fig. 6. (a) Dynamic responses for the reference voltage variation as well as the slope trajectory tracking, (b) Dynamic responses for the supply voltage variation in slope mode and transition mode
V. E XPERIMENTAL R ESULTS A. FPGA Platform As an effective verification and validation tool for ASIC, FPGA allows the development of digital controllers with the aid of rich peripherals [25]. To verify the function and timing issues of the proposed voltage and current predictive controller and proposed DPWM, a high switching frequency low power buck converter is connected to a VIRTEX-II Pro XC2VP30 FPGA with 3.0 V input and 1.5 V output voltage as shown in Fig. 7. The output power of the buck converter prototype ranges from 450 mW to 682 mW over the switching frequency range. Some important system parameters are summarized in Table. I. An open-loop environment is designed to test the proposed DPWM. In terms of design specification, dynamic and steady performance can be obtained through a closed-loop test. B. Test of DPWM
LI et al.: A DIGITAL DUAL-STATE-VARIABLE PREDICTIVE CONTROLLER FOR HIGH SWITCHING FREQUENCY BUCK CONVERTER WITH IMPROVED Σ-∆ DPWM7
Fig. 7. Schematic of the experimental controller prototype for a synchronous buck converter TABLE I PARAMETERS OF THE DIGITALLY CONTROLLED SMPS Buck R L C Vin Vo fs ADC DPWM NDP W M NΣ−∆ fclk
Switching mode power converter Nominal load Inductor Capacitor Input voltage Output voltage Switching frequency Analog to digital Converter DMASH 1-1 DPWM Core DPWM resolution Proposed DPWM resolution DPWM counter frequency
Fig. 8. Regulated output Vo of the experimental converter for a digital ramp from 2047 to 0
Step down 5Ω 4.7 µH 22 µF 3.0 V 1.5 V 4 MHz (up to 10 MHz) 10-bit 11-bit 6-bit 5-bit 64 MHz
1) Steady-state Test: A 6-bit counter-comparator based DPWM, also known as the core DPWM within the proposed DPWM, is adopted as a reference. Fig. 8 shows the LC filtered output of the duty cycle for a manually generated ramp signal from 2047 to 0 that is also the duty cycle sweep change for the 11-bit DPWM. An obvious observation from the results of open-loop DPWM test is that the slope of the proposed DPWM is smoother than that of the core DPWM. As the nature of Σ-∆, it conforms to the noise shaping principal that also leads to the increase in the effective resolution. The integral nonlinearity (INL) and the differential nonlinearity (DNL) are measured with a 61.44 Hz full-scale ramp input. At 61.44 KS/s, 60011 sample points are collected. The measured DNL is within ±0.62 LSB and the INL curve never exceeds +0.55/-0.83 LSB over the 3 V dynamic range. 2) Transient-state Test: Fig. 9 shows an example of the dynamic behavioral characteristic in which there is a transition of equivalent input bins from 2047 to 0. The convergence time for our proposed DMASH 1-1 DPWM is 204 µs that is significantly smaller than that of the first order Σ-∆ DPWM. C. Test of the Proposed Controller As introduced in Section V-A, a buck power stage from 3 V to 1.5 V is constructed and regulated by the proposed FPGA-based digital controller. An external 10-bit ADC converts the output voltage of the buck converter to the digital format so as to verify the closed-loop operation. The ADC specifications, such as resolution and conversion delay, play an important role in the controller performances with respect
Fig. 9. Comparison of the regulated output Vo in transient state using the first order Σ-∆ DPWM and proposed DMASH 1-1 DPWM
to the settling time, the output ripple value and LCO. The used ADC (ADC9203) can guarantee satisfactory steady-state and transient-state performances. Due to frequency limits of the discrete buck architecture, tests are currently performed up to 4 MHz, but can be possibly extended to 10 MHz with an integrated controller IC according to the VHDL-AMS simulation results performed on INCISIV, Cadence. Test of the proposed controller is carried out on the FPGA-platform. The involved dead-beat controller cannot perform at so high switching frequency due to the absence of current sensor. So the dynamic behavior of the proposed controller is compared with that of a PID controller. Considering the tradeoff between the dynamic performance and robustness (modulus and delay margins) of a PID controller, the pulsation ωcr is set to 15 times the open-loop pulsation ω0 corresponding to 1475100 rad/s with the closed-loop damping ratio ζcr = 0.7. The discrete-time PID controller, which is tuned to be optimal can then be written as d[n] =0.784 × d[n − 1] + 0.216 × d[n − 2] + 8.366 × e[n] − 16.244 × e[n − 1] + 7.940 × e[n − 2] (25) where d[n] is the discrete value of the PWM output, e[n] is the discrete value of the error signal between the reference
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IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS
(a)
Fig. 11. Transient output voltage at 4 MHz switching frequency during load change from 0.45 A to 0.3 A (R: from 3.3 Ω to 5 Ω) using proposed controller
proposed controller operating at different switching frequencies are reported in Table. III. TABLE III DYNAMIC P ERFORMANCE OF THE P ROPOSED C ONTROLLER UNDER A L OAD P ERTURBATION BETWEEN 0.3 A AND 0.45 A Switching frequency
(b) Fig. 10. Transient output voltage at 1 MHz switching frequency during load change from 0.3 A to 0.45 A (R: from 5 Ω to 3.3 Ω) using (a) proposed controller (b) PID controller
voltage Vref and the regulated output Vo , d[n − i] and e[n − i] are respectively the PWM output and the error values at the ith-cycles prior to the current cycle. Experimental results are presented in Fig. 10. Unlike the predictive dead-beat controller, the two controllers can operate without the aid of a current sensor. The PID controller can support up to 1 MHz switching frequency with the same testbench of the proposed controller. Fig. 10(a) and (b) show the transient output voltage response operating at 1 MHz switching frequency when the load suddenly varies from 0.3 A to 0.45 A (5 Ω to 3.3 Ω). Comparisons of design parameters and operation performances of the two controllers are summarized in Table. II. The proposed controller shows better dynamic performances than the PID controller. It exhibits more than 5 times shorter dynamic response and about half the overshoot voltage. All these improvements only cost less than 35% extra hardware resources. So for a high switching frequency buck converter, the dual-state-variable predictive controller is a better tradeoff taking into account hardware implementation and dynamic performance. Fig. 11 shows the dynamic response with the load current transient from 0.45 A to 0.3 A operating at 4 MHz switching frequency. With the increase in the switching frequency, the voltage and current predictive controller enables faster response and results with relatively lower overshoot voltage. Detailed results related to the dynamic performances of the
1 MHz 2 MHz 4 MHz
Settling Positive perturbation (µs)
Time Negative perturbation (µs)
Negative overshoot
Positive overshoot
(mV)
(mV)
43.8 31.5 23.8
44.0 32.3 21.4
44.0 35.0 30.7
17.4 15.6 24.4
The FPGA-based experimental results show that the proposed controller is a good candidate for an ASIC implementation. In order to make full use of standard digital CMOS process, each parameter must be tunable in order to cancel the nonideal factor influence. So using the statemachine based parameter generator as shown in Fig. 12, the controller is assured to work either adopting fine-tuning to offer immunization to the noise perturbation, or importing parameters for higher switching frequency. The parameter adaptive control method can also be constructed based on this block. In order to implement the programmable parameters that introduce an adjustable control effect, a serial data receiver is connected to din so as to provide the control parameters. The parameter read-in module has its own synchronous clock (clk) and reset (rest) signals. The ADDR enables each shift-register providing parameters for a designated controller. Another advantage of integrating the serial to parallel module is its cancellation of the data-path between shift-register and proposed controller that largely saves hardware resources. VI. C ONCLUSION This paper presents a fully synthesizable DPWM-based dual-state-variable predictive controller for low-power and high-frequency (MHz and over) SMPS. The architecture contains a novel control algorithm and a DMASH 1-1 DPWM. The proposed controller achieves a constant switching frequency with better static and dynamic performances, as well as good immunity to the power and load perturbations. Its
LI et al.: A DIGITAL DUAL-STATE-VARIABLE PREDICTIVE CONTROLLER FOR HIGH SWITCHING FREQUENCY BUCK CONVERTER WITH IMPROVED Σ-∆ DPWM9
TABLE II A G ENERAL C OMPARISON WITH PID C ONTROLLER O PERATING AT 1 MH Z S WITCHING F REQUENCY
Fig. 12.
Controller type
Multiplier amount
Adder amount
Tunable parameters amount
Total equivalent gates
Settling time 0.3 A →0.45 A (µs)
Settling time 0.45 A→0.3 A (µs)
Negative overshoot
Positive overshoot
(mV)
(mV)
Proposed controller PID controller
5 5
7 4
3 5
6997 5059
43.8 235.0
44.0 232.0
44.0 75.2
17.4 40.4
Block diagram of the parameter read-in module
hardware implementation is quite simple: only few memories, multipliers and adders in FPGA/ASIC are needed. The DMASH 1-1 DPWM takes the advantage of the noise-shaping concept and implements a MASH architecture, as well as combines a dither block in order to further eliminate the idle-tone effects. The FPGA implementation is tested along with a lab-scale buck converter (step-down SMPS) where the switching frequency is limited to 4 MHz. The experimental results validate the functionality and performances of the proposed DMASH 1-1 DPWM-based discrete voltage and current predictive controller and confirm the feasibility of an ASIC using a peripheral to program parameters for specific controllers. R EFERENCES [1] Y.-F. Liu, E. Meyer, and X. Liu, “Recent developments in digital control strategies for DC/DC switching power converters,” IEEE Trans. Power Electron., vol. 24, no. 11, pp. 2567–2577, Nov. 2009. [2] Z. Lukic, N. Rahman, and A. Prodic, “Multibit Σ-∆ PWM digital controller IC for DC-DC converters operating at switching frequencies beyond 10 MHz,” IEEE Trans. Power Electron., vol. 22, no. 5, pp. 1693–1707, Sep. 2007. [3] F. Luo and D. Ma, “Design of digital tri-mode adaptive-output buckboost power converter for power-efficient integrated systems,” IEEE Trans. Ind. Electron., vol. 57, no. 6, pp. 2151–2160, Jun. 2010. [4] B.-Y. Chen and Y.-S. Lai, “New digital-controlled technique for battery charger with constant current and voltage control without current feedback,” IEEE Trans. Ind. Electron., vol. 59, no. 3, pp. 1545–1553, Mar. 2012. [5] F. Gonzalez-Espin, E. Figueres, G. Garcera, R. Gonzalez-Medina, and M. Pascual, “Measurement of the loop gain frequency response of digitally controlled power converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2785–2796, Aug. 2010. [6] V. Yousefzadeh, A. Babazadeh, B. Ramachandran, E. Alarcon, L. Pao, and D. Maksimovic, “Proximate time-optimal digital control for synchronous buck DC-DC converters,” IEEE Trans. Power Electron., vol. 23, no. 4, pp. 2018–2026, Jul. 2008. [7] E. Vidal-Idiarte, C. E. Carrejo, J. Calvente, Marti, and L. nez Salamero, “Two-loop digital sliding mode control of DC-DC power converters based on predictive interpolation,” IEEE Trans. Ind. Electron., vol. 58, no. 6, pp. 2491–2501, Jun. 2011.
[8] S. Saggini, W. Stefanutti, P. Mattavelli, and A. Carrera, “Efficiency estimation in digitally-controlled DC-DC buck converters based on single current sensing,” in Proc. IEEE PESC Conf., Jun. 2008, pp. 3581– 3586. [9] Z. Zhao and A. Prodic, “Limit-cycle oscillations based auto-tuning system for digitally controlled DC-DC power supplies,” IEEE Trans. Power Electron., vol. 22, no. 6, pp. 2211–2222, Nov. 2007. [10] W. Stefanutti, P. Mattavelli, S. Saggini, and M. Ghioni, “Autotuning of digitally controlled DC-DC converters based on relay feedback,” IEEE Trans. Power Electron., vol. 22, no. 1, pp. 199–207, Jan. 2007. [11] E. Zurita-Bustamante, J. Linares-Flores, E. Guzman-Ramirez, and H. Sira-Ramirez, “A comparison between the GPI and PID controllers for the stabilization of a DC-DC buck converter: A field programmable gate array implementation,” IEEE Trans. Ind. Electron., vol. 58, no. 11, pp. 5251–5262, Nov. 2011. [12] V. Mummadi, “Design of robust digital PID controller for H-Bridge softswitching boost converter,” IEEE Trans. Ind. Electron., vol. 58, no. 7, pp. 2883–2897, Jul. 2011. [13] G. Zhou, J. Xu, and Y. Jin, “Elimination of subharmonic oscillation of digital-average-current-controlled switching DC-DC converters,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2904–2907, Aug. 2010. [14] S. Bibian and H. Jin, “High performance predictive dead-beat digital controller for DC power supplies,” IEEE Trans. Power Electron., vol. 17, no. 3, pp. 420–427, May. 2002. [15] Y. Qiu, H. Liu, and X. Chen, “Digital average current-mode control of PWM DC-DC converters without current sensors,” IEEE Trans. Ind. Electron., vol. 57, no. 5, pp. 1670–1677, May 2010. [16] A. Malinowski and H. Yu, “Comparison of embedded system design for industrial applications,” IEEE Trans. Ind. Informat., vol. 7, no. 2, pp. 244–254, May 2011. [17] M. P. Kazmierkowski, M. Jasinski, and G. Wrona, “DSP-based control of grid-connected power converters operating under grid distortions,” IEEE Trans. Ind. Informat., vol. 7, no. 2, pp. 204–211, May 2011. [18] C.-A. Yeh and Y.-S. Lai, “Digital pulsewidth modulation technique for a synchronous buck DC/DC converter to reduce switching frequency,” IEEE Trans. Ind. Electron., vol. 59, no. 1, pp. 550–561, Jan. 2012. [19] A. Peterchev and S. Sanders, “Quantization resolution and limit cycling in digitally controlled PWM converters,” IEEE Trans. Power Electron., vol. 18, no. 1, pp. 301–308, Jan. 2003. [20] H. Peng, D. Maksimovic, A. Prodic, and E. Alarcon, “Modeling of quantization effects in digitally controlled DC-DC converters,” in Proc. IEEE PESC Conf., vol. 6, Jun. 2004, pp. 4312–4318. [21] J. Xiao, A. Peterchev, J. Zhang, and S. Sanders, “A 4-µA quiescentcurrent dual-mode digitally controlled buck converter IC for cellular phone applications,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2342–2348, Dec. 2004. [22] V. Yousefzadeh, T. Takayama, and D. Maksimovi, “Hybrid DPWM with digital delay-locked loop,” in Proc. IEEE COMPEL Works., Jul. 2006, pp. 142–148. [23] S. Guo, X. Lin-Shi, B. Allard, B. Li, Y. Gao, and Y. Ruan, “Highresolution digital PWM controller for high-frequency low-power SMPS,” in Proc. EPE Conf., Sep. 2009, pp. 1–9. [24] V. Gonzalez-Diaz, M. Garcia-Andrade, G. Flores-Verdad, and F. Maloberti, “Efficient dithering in MASH Sigma-Delta modulators for fractional frequency synthesizers,” IEEE Trans. Circuits Syst. I, vol. 57, no. 9, pp. 2394–2403, Sep. 2010. [25] E. Monmasson, L. Idkhajine, M. N. Cirstea, I. Bahri, A. Tisan, and M. W. Naouar, “FPGAs in industrial control applications,” IEEE Trans. Ind. Informat., vol. 7, no. 2, pp. 224–243, May 2011.
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Bo Li received the B.Sc. and M.Sc. degrees from the Department of Electronics Engineering, Beijing Jiaotong University, China, in 2005 and 2008, respectively. He is currently working towards the Ph.D. degree at Amp`ere-Lab, INSA Lyon (Institut National des Sciences Appliqu´ees de Lyon), France. His current research interests include digital control techniques applied to high frequency switchedmode power supply, low power digital and mixedsignal IC design.
Xuefang Lin-Shi (M’09) received the Ph.D. degree in applied computer science and automatic in 1992 from INSA Lyon (Institut National des Sciences Appliqu´ees de Lyon), France. Since 1993, she has been with the Electrical Engineering department of INSA Lyon, where she is currently a professor. She is now with Amp`ere Laboratory in Lyon. Her research interests concern control applied to electrical drives and power electronics system.
Bruno Allard (M’93-SM’02) was born in 1965. He received the M.Sc. and Ph.D. degrees in engineering from the Institut National des Sciences Applique´ees de Lyon (INSA Lyon), Lyon, France, in 1989 and 1992, respectively. He is a Full Professor at Amp`ereLab, INSA Lyon, Lyon where he is currently the Head Manager. He has led numerous industrial and academic projects. He is the author or coauthor of more than 80 papers and 100 international conference contributions. His research interests include the integration of power systems, either hybrid or monolithic, power semiconductor device modeling and characterization, power electronic system design and low-power monolithic converter design.
Jean-Marie R´etif received the Ph.D. degree in tuning control from the Universit´e Claude Bernard Lyon I, Lyon, France, in 1979. He was with the Energetic and Control Laboratory, Institut National des Sciences Appliqu´ees de Lyon (INSA Lyon), France, where he dealt with different subjects such as process control and optimization of solar heating. Since 1979, he has been with the Amp`ere Laboratory, INSA Lyon, where he has been working on control in the field of electrical engineering.
