A Functional Hybrid Memristor Crossbar-Array/CMOS System for Data ...
A Functional Hybrid Memristor Crossbar-Array/CMOS System for Data Storage and Neuromorphic Applications Kuk-Hwan Kim, Siddharth Gaba, Dana Wheeler, Jose Cruz‐Albrecht, Tahir Hussain, Narayan Srinivasa and Wei Lu
Supporting Online Material
Figure S1. (a) Schematic of the sneak path problem. When the target cell is in the off-state, a high read current may still be mistakenly measured due to current flowing through other cells in the on-state in the array. Sneak paths always include at least one memory cell which is reverse biased. Therefore, the sneak path problem can be mitigated if the resistive switching device also exhibits current-rectifying characteristics (b).
1
Figure S2. I-V characteristics of a device in the voltage range of -1 V to 3 V. Even though the current through the device is low at negative bias, the device remains in the on-state, as verified from subsequent voltage sweeps. The device can be erased with larger negative voltages (< -1.5 V).
2
Figure S3. Reconstructed 40×40 bitmap images obtained by storing and retrieving data from 4 larger 20×20 sub-arrays. Some error starts to appear due to disturb of the existing cell states possibly due to voltage glitches from the mechanical switches used in the switching matrix system, and non-synchronized protecting voltages due to different RC delays in different bit locations. A complete memory system with on-chip programming and sensing circuitry will likely significantly address the disturb problem.
3
Figure S4. Potential distribution without the current-rectifying characteristics at the crosspoints but with the application of external diodes to the unselected electrodes. The worst case is simulated with the target cell (cell (0,40), upper left) in off-state (500 MΩ) and all others in on-state (500 KΩ). With the application of a Vs = 3.5V write voltage and symmetric Vp = 1.7 V protecting voltages applied to the unselected electrodes, only 0.5V is actually applied across the target cell due to parasitic current paths through the half-selected devices resulting in a voltage divider effect with the external series-resistor.
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Figure S5. Simulated potential distribution from the circuit configuration in Fig. 3d. The worst case is simulated with the target cell (cell (0,40), upper left) in off-state (500 MΩ) and all others in on-state (500 KΩ). The potentials of the bottom electrodes are raised by currents through the half-selected cells at the same row of the target cell, as shown in the change in color in the top-most row. A Vs = 3.5V write voltage is applied to the target cell in all cases. (a) Application of symmetric protecting voltages. In this scenario Vp = 1.7 V is applied to the unselected bottom electrodes and the unselected top electrodes. A large negative potential ( ~ - 1.7 V) which can disturb the state of the unselected memory cells can build up across all the unselected memory cells, as represented by the blue color in cells (1,39) to (40,0). (b) Application of asymmetric protecting voltages. Here Vpw = 3.0 V is applied to the unselected word-lines (top electrodes), while Vpb =1.7 V is applied to the unselected bit-lines (bottom electrodes). As a result, the unselected devices are biased with a -0.8 V negative voltage in the worst-case which will not disturb the state of the unselected memory cells. This configuration was used to obtain the data in Figure 4.
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Device fabrication and measurement The resistance switching devices were fabricated by the following process. First, 20 nmthick tungsten film was deposited by sputter, and then 20 nm-thick boron-doped SixGe1-x film was deposited by thermal CVD at 425°C followed by 20 nm-thick amorphous Si film deposition by plasma enhanced CVD. The film stacks were patterned with ebeam lithography and
successive
high-density
plasma
etching
and
planarized
with
spin-on-glass
(semiconductor grade 700B, Filmtronics). After etch back to expose the surface of the a-Si layer, the top electrodes were patterned with ebeam lithography and lift-off. Contact of the nanowire electrodes in the crossbar array with underlying CMOS circuits was achieved through alignment (using pre-fabricated alignment marks) of nanowire electrodes to tungsten vias fabricated on the chip during CMOS processing. The CMOS decoder circuit was implemented using a transmission gate structure, and current paths through the CMOS circuits are bi-directional. DC I-V measurements of the devices were performed by using a custom-built data acquisition system and a Keithley 4200 semiconductor parameter analyzer. Crossbar array operation and measurements were performed through a switch matrix system (Keithley 3706 mainframe with 6ｘ16 switch cards) which provided the data and address IO to the CMOS inputs. The programming pulses were provided by a NI USB-6259 data acquisition system and custom software. A fixed series-resistor (Rs = 500 KΩ) was used to limit the current during the binary device operation (Figures 1 and 2) while different series resistance values (0.025 – 10 MΩ) were used to control the final device resistance during multi-level storage (Figures 3 and 4). 6
Supporting Online Material
Figure S1. (a) Schematic of the sneak path problem. When the target cell is in the off-state, a high read current may still be mistakenly measured due to current flowing through other cells in the on-state in the array. Sneak paths always include at least one memory cell which is reverse biased. Therefore, the sneak path problem can be mitigated if the resistive switching device also exhibits current-rectifying characteristics (b).
1
Figure S2. I-V characteristics of a device in the voltage range of -1 V to 3 V. Even though the current through the device is low at negative bias, the device remains in the on-state, as verified from subsequent voltage sweeps. The device can be erased with larger negative voltages (< -1.5 V).
2
Figure S3. Reconstructed 40×40 bitmap images obtained by storing and retrieving data from 4 larger 20×20 sub-arrays. Some error starts to appear due to disturb of the existing cell states possibly due to voltage glitches from the mechanical switches used in the switching matrix system, and non-synchronized protecting voltages due to different RC delays in different bit locations. A complete memory system with on-chip programming and sensing circuitry will likely significantly address the disturb problem.
3
Figure S4. Potential distribution without the current-rectifying characteristics at the crosspoints but with the application of external diodes to the unselected electrodes. The worst case is simulated with the target cell (cell (0,40), upper left) in off-state (500 MΩ) and all others in on-state (500 KΩ). With the application of a Vs = 3.5V write voltage and symmetric Vp = 1.7 V protecting voltages applied to the unselected electrodes, only 0.5V is actually applied across the target cell due to parasitic current paths through the half-selected devices resulting in a voltage divider effect with the external series-resistor.
4
Figure S5. Simulated potential distribution from the circuit configuration in Fig. 3d. The worst case is simulated with the target cell (cell (0,40), upper left) in off-state (500 MΩ) and all others in on-state (500 KΩ). The potentials of the bottom electrodes are raised by currents through the half-selected cells at the same row of the target cell, as shown in the change in color in the top-most row. A Vs = 3.5V write voltage is applied to the target cell in all cases. (a) Application of symmetric protecting voltages. In this scenario Vp = 1.7 V is applied to the unselected bottom electrodes and the unselected top electrodes. A large negative potential ( ~ - 1.7 V) which can disturb the state of the unselected memory cells can build up across all the unselected memory cells, as represented by the blue color in cells (1,39) to (40,0). (b) Application of asymmetric protecting voltages. Here Vpw = 3.0 V is applied to the unselected word-lines (top electrodes), while Vpb =1.7 V is applied to the unselected bit-lines (bottom electrodes). As a result, the unselected devices are biased with a -0.8 V negative voltage in the worst-case which will not disturb the state of the unselected memory cells. This configuration was used to obtain the data in Figure 4.
5
Device fabrication and measurement The resistance switching devices were fabricated by the following process. First, 20 nmthick tungsten film was deposited by sputter, and then 20 nm-thick boron-doped SixGe1-x film was deposited by thermal CVD at 425°C followed by 20 nm-thick amorphous Si film deposition by plasma enhanced CVD. The film stacks were patterned with ebeam lithography and
successive
high-density
plasma
etching
and
planarized
with
spin-on-glass
(semiconductor grade 700B, Filmtronics). After etch back to expose the surface of the a-Si layer, the top electrodes were patterned with ebeam lithography and lift-off. Contact of the nanowire electrodes in the crossbar array with underlying CMOS circuits was achieved through alignment (using pre-fabricated alignment marks) of nanowire electrodes to tungsten vias fabricated on the chip during CMOS processing. The CMOS decoder circuit was implemented using a transmission gate structure, and current paths through the CMOS circuits are bi-directional. DC I-V measurements of the devices were performed by using a custom-built data acquisition system and a Keithley 4200 semiconductor parameter analyzer. Crossbar array operation and measurements were performed through a switch matrix system (Keithley 3706 mainframe with 6ｘ16 switch cards) which provided the data and address IO to the CMOS inputs. The programming pulses were provided by a NI USB-6259 data acquisition system and custom software. A fixed series-resistor (Rs = 500 KΩ) was used to limit the current during the binary device operation (Figures 1 and 2) while different series resistance values (0.025 – 10 MΩ) were used to control the final device resistance during multi-level storage (Figures 3 and 4). 6
