A High-Speed Low-Power Hybrid Analog-to-Digital Converter ...
Graduate Category: Engineering and Technology Degree Level: PhD Abstract ID# 654
A High-Speed Low-Power Hybrid Analog-to-Digital Converter Architecture for Wireless Portable Medical Devices Seyed Alireza Zahrai, Faculty Advisor: Marvin Onabajo, Analog and Mixed-Signal Integrated Circuit Laboratory Comparator Asynchronous Binary Search (CABS) ADC
In recent years, telemedicine has become popular because it makes access to healthcare more convenient with lower cost, thereby saving lives through early diagnosis and real-time monitoring. The goal of this research is to design a high-speed analog-to-digital converter (ADC) for portable communication chips in telemedicine applications that require low power consumption to extend the lifetimes of batteries. The high-speed and low-power performance is achieved by devising a hybrid architecture that combines the advantages of two different types of ADCs.
The 5-bits CABS architecture [1] is capable of high conversion rates while consuming relatively low power thanks to its asynchronous operation. It consumes 400µW with a 250Mhz clock. VXP 7Vref/8 VXN Vref/8
VXP 3Vref/4 VXN Vref/4 VXP Vref/2
+ -
VXN Vref/2
+ -
Vo1_p
+ -
+ -
+ -
+ -
Vo1_p
VXP 5Vref/8 VXN 3Vref/8
Vo1_n
SAR_Clock
+ -
+ -
+ -
+ -
+ -
+ -
VXN Vref/32
+ -
+ -
VXN 3Vref/4
+ -
+ -
VXP 3Vref/8
+ -
VXN Vo2_n 5Vref/8
+ -
Vo2_p
+ -
VXP Vref/8 VXN 7Vref/8
+ -
+ -
+ -
Outputs are reset to zero when the clock is zero.
Vo15_p
Vo7_n
+ -
VXP 29Vref/32 VXN 3Vref/32
+ -
+ -
Vo6_p
Vo15_n Vo6_n
Vo5_p
Vo5_n
Vo2_p
Vo1_n
Consumes power only when it is clocked
+ -
Vo3_n
VXP Vref/4
Dynamic latched comparator:
Vo7_p
Vo3_p
Vo3_p Vo3_n
+ -
VXP 31Vref/32
Encoder (Custom designed by logic gates)
Introduction
VXP 3Vref/32
+ -
VXN 29Vref/32
+ -
+ -
M7
M8 M9
M10 M11
Clock
M12 Clock
Voutp
Voutn
B4 B3 B2 B1 B0
M6
M5
M1
VIP
M2
VRP
VRN
M3
M4
VIN
Vo4_p
Vo8_p
Vo4_n
Clock + -
VXP Vref/32 VXN 31Vref/32
Vo2_n
+ -
Mtail1
Mtail2
+ -
Vo8_n
Simulation Results
Proposed Hybrid ADC Architecture The use of a Flash ADC is not power efficient with high resolution due to the large number of power-hungry comparators. Research Approach: Development of a Hybrid ADC architecture with one low-resolution Flash ADC accompanying by multiple time-interleaved successive approximation register (SAR) ADCs in the next stage → Combines the high-speed advantage of a low-resolution Flash ADC with the power efficiency of SAR ADCs. In the first stage, a flash ADC resolves the three most significant bits of the analog input signal, and the remaining five bits are determined by four time-interleaved low-power SAR ADCs in the second Clock Signals stage, leading to an overall VIP SHDAC 1 Buffer hybrid ADC having 8-bit VIN resolution operating with a 1GHz sampling clock. Buffer Flash ADC 3 bits
3 bits
Clk @ 1 GS/s
CABS_CLK_1
SAMP_CLK_1
CABS ADC 2 5 bits 5 bits
SHDAC 2
CABS_CLK_2
SAMP_CLK_2
Timing diagram of the hybrid ADC: 1ns
0ns
2ns
3ns
4ns
Phase 1
CABS ADC 3 5 bits 5 bits
Buffer
SHDAC 3
CABS_CLK_3
SAMP_CLK_3
Phase 2 Phase 3
CABS ADC 4 5 bits 5 bits
Buffer
SHDAC 4
Bit Allignment Unit (Sets of Latches)
CABS ADC 1 5-bits 5 bits
8 bits @ 1GS/s
Phase 4 CABS_CLK_4 3 bits
SAMP_CLK_4
8 bit code
ADC_Output
Sample-and-Hold and Digital-to-Analog Converter (SHDAC) The SHDAC circuit samples the input voltage and also shifts it to the optimal voltage range of the second stage based on the flash ADC output bits. A unity-gain buffer is needed to suppress the loading effect of the SAR ADC’s input capacitance.
VRP=850m V 62.5m V
VIP
111 110
101 100 VCM=600m V
62.5m V 0.6 V 011 010
000
VIN
VRN=350m V
VIN SAMP_CLK4Cu
2Cu
Cu
VRP
VOP
ɸ2
CB0
VOP
VRN
VXP ɸ1
VCM
VCM
CB1
CB1
Cu
CB0
S0
VCM S0
CB2
VRN CB3
CB3
VRP CB2
S1
VCM S1
CB4
VRN CB5
CB5
VRP CB4
S2
VCM
Cu
2Cu
4Cu S2
VIP
ɸ1
Cu
VON
ADC Performance Comparison Table Specification
This work
[2]
[3]
[4]
[5]
Sampling Rate (GS/s)
1
1.5
1
2
1
Number of Bits
8
7
10
6
6
SNDR @ NQ (dB)
47.5
38.2
51.4
33.1
33.4
ENOB @ NQ (dB)
7.60
6.05
8.25
5.21
5.25
CMOS Technology (nm)
130
90
65
45
65
Supply Voltage (V)
1.2
1.2
1
1.2
1
Power (mW)
17
204
18.9
14.4
62
FOM (fJ/conv. step)
87.6
2053
62.1
195
1629
Spectrum of the 8-bit 1GS/s hybrid ADC output: (a) fin = 6.84 MHz, (b) fin = 491.21 MHz.
Simulated DNL & INL of the hybrid ADC.
Conclusion The proposed 8-bit hybrid ADC architecture takes advantage of a 1GS/s 3-bit Flash ADC’s high-speed characteristics and the low-power nature of four 5-bit 250MS/s time-interleaved SAR ADCs, leading to 8-bit 1GS/s operation. A combined sample-and-hold and digital-to-analog converter (SHDAC) circuit was introduced for front-end sampling and shifting of the sampled voltage to the optimum operating region of the next stage, which alleviates voltage swing requirements and thereby reduces power consumption of amplifiers. The simulation results suggest that the ADC can achieve a SNDR above 47.4dB with an estimated power of 17mW in 130nm CMOS technology with 1.2V supply. In comparison to the state-of-the-art, the presented architecture consumes low power and has a competitive FOM, especially considering the lower transition frequency (fT) of the technology compared to the majority of works in Table.
References
001
SAMP_CLK
The hybrid ADC was simulated in 130nm CMOS technology with a mix of blocks implemented as transistor-level designs (a) (CABS ADC with encoder, buffer amplifiers) and macro-models (Switches, flash ADC, bit alignment unit). Total estimated power : approx. 17mW. Figure of merit (FOM) with an input close to the Nyquist rate: 87.6 fJ/step (b) FOM = power / (fS × 2ENOB)
VXN
VON ɸ2
[1] G. Van der Plas and B. Verbruggen, “A 150 MS/s 133 µW 7 bit ADC in 90 nm Digital CMOS,” IEEE J. SolidState Circuits, vol. 43, no. 12, pp. 2631-2640, Dec. 2008. [2] J. Pernillo and M. P. Flynn, “A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS,” IEEE Trans. Circuits and Systems II: Express Briefs, vol. 58, no. 12, pp. 837-841, Dec. 2011. [3] S. Lee, A. P. Chandrakasan, and H-S. Lee, “A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration,” IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2846-2856, Dec. 2014. [4] B. Sung et. al., “A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration,” in Proc. IEEE Asian Solid-State Circuits Conf., pp. 281-284, Nov. 2013. [5] C.-J. Tseng, C. F. Lai, and H.-S. Chen, “A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration,” IEEE Trans. Circuits And Systems I: Regular Papers, vol. 31, no. 10, pp. 2805-2815, Oct. 2014.
A High-Speed Low-Power Hybrid Analog-to-Digital Converter Architecture for Wireless Portable Medical Devices Seyed Alireza Zahrai, Faculty Advisor: Marvin Onabajo, Analog and Mixed-Signal Integrated Circuit Laboratory Comparator Asynchronous Binary Search (CABS) ADC
In recent years, telemedicine has become popular because it makes access to healthcare more convenient with lower cost, thereby saving lives through early diagnosis and real-time monitoring. The goal of this research is to design a high-speed analog-to-digital converter (ADC) for portable communication chips in telemedicine applications that require low power consumption to extend the lifetimes of batteries. The high-speed and low-power performance is achieved by devising a hybrid architecture that combines the advantages of two different types of ADCs.
The 5-bits CABS architecture [1] is capable of high conversion rates while consuming relatively low power thanks to its asynchronous operation. It consumes 400µW with a 250Mhz clock. VXP 7Vref/8 VXN Vref/8
VXP 3Vref/4 VXN Vref/4 VXP Vref/2
+ -
VXN Vref/2
+ -
Vo1_p
+ -
+ -
+ -
+ -
Vo1_p
VXP 5Vref/8 VXN 3Vref/8
Vo1_n
SAR_Clock
+ -
+ -
+ -
+ -
+ -
+ -
VXN Vref/32
+ -
+ -
VXN 3Vref/4
+ -
+ -
VXP 3Vref/8
+ -
VXN Vo2_n 5Vref/8
+ -
Vo2_p
+ -
VXP Vref/8 VXN 7Vref/8
+ -
+ -
+ -
Outputs are reset to zero when the clock is zero.
Vo15_p
Vo7_n
+ -
VXP 29Vref/32 VXN 3Vref/32
+ -
+ -
Vo6_p
Vo15_n Vo6_n
Vo5_p
Vo5_n
Vo2_p
Vo1_n
Consumes power only when it is clocked
+ -
Vo3_n
VXP Vref/4
Dynamic latched comparator:
Vo7_p
Vo3_p
Vo3_p Vo3_n
+ -
VXP 31Vref/32
Encoder (Custom designed by logic gates)
Introduction
VXP 3Vref/32
+ -
VXN 29Vref/32
+ -
+ -
M7
M8 M9
M10 M11
Clock
M12 Clock
Voutp
Voutn
B4 B3 B2 B1 B0
M6
M5
M1
VIP
M2
VRP
VRN
M3
M4
VIN
Vo4_p
Vo8_p
Vo4_n
Clock + -
VXP Vref/32 VXN 31Vref/32
Vo2_n
+ -
Mtail1
Mtail2
+ -
Vo8_n
Simulation Results
Proposed Hybrid ADC Architecture The use of a Flash ADC is not power efficient with high resolution due to the large number of power-hungry comparators. Research Approach: Development of a Hybrid ADC architecture with one low-resolution Flash ADC accompanying by multiple time-interleaved successive approximation register (SAR) ADCs in the next stage → Combines the high-speed advantage of a low-resolution Flash ADC with the power efficiency of SAR ADCs. In the first stage, a flash ADC resolves the three most significant bits of the analog input signal, and the remaining five bits are determined by four time-interleaved low-power SAR ADCs in the second Clock Signals stage, leading to an overall VIP SHDAC 1 Buffer hybrid ADC having 8-bit VIN resolution operating with a 1GHz sampling clock. Buffer Flash ADC 3 bits
3 bits
Clk @ 1 GS/s
CABS_CLK_1
SAMP_CLK_1
CABS ADC 2 5 bits 5 bits
SHDAC 2
CABS_CLK_2
SAMP_CLK_2
Timing diagram of the hybrid ADC: 1ns
0ns
2ns
3ns
4ns
Phase 1
CABS ADC 3 5 bits 5 bits
Buffer
SHDAC 3
CABS_CLK_3
SAMP_CLK_3
Phase 2 Phase 3
CABS ADC 4 5 bits 5 bits
Buffer
SHDAC 4
Bit Allignment Unit (Sets of Latches)
CABS ADC 1 5-bits 5 bits
8 bits @ 1GS/s
Phase 4 CABS_CLK_4 3 bits
SAMP_CLK_4
8 bit code
ADC_Output
Sample-and-Hold and Digital-to-Analog Converter (SHDAC) The SHDAC circuit samples the input voltage and also shifts it to the optimal voltage range of the second stage based on the flash ADC output bits. A unity-gain buffer is needed to suppress the loading effect of the SAR ADC’s input capacitance.
VRP=850m V 62.5m V
VIP
111 110
101 100 VCM=600m V
62.5m V 0.6 V 011 010
000
VIN
VRN=350m V
VIN SAMP_CLK4Cu
2Cu
Cu
VRP
VOP
ɸ2
CB0
VOP
VRN
VXP ɸ1
VCM
VCM
CB1
CB1
Cu
CB0
S0
VCM S0
CB2
VRN CB3
CB3
VRP CB2
S1
VCM S1
CB4
VRN CB5
CB5
VRP CB4
S2
VCM
Cu
2Cu
4Cu S2
VIP
ɸ1
Cu
VON
ADC Performance Comparison Table Specification
This work
[2]
[3]
[4]
[5]
Sampling Rate (GS/s)
1
1.5
1
2
1
Number of Bits
8
7
10
6
6
SNDR @ NQ (dB)
47.5
38.2
51.4
33.1
33.4
ENOB @ NQ (dB)
7.60
6.05
8.25
5.21
5.25
CMOS Technology (nm)
130
90
65
45
65
Supply Voltage (V)
1.2
1.2
1
1.2
1
Power (mW)
17
204
18.9
14.4
62
FOM (fJ/conv. step)
87.6
2053
62.1
195
1629
Spectrum of the 8-bit 1GS/s hybrid ADC output: (a) fin = 6.84 MHz, (b) fin = 491.21 MHz.
Simulated DNL & INL of the hybrid ADC.
Conclusion The proposed 8-bit hybrid ADC architecture takes advantage of a 1GS/s 3-bit Flash ADC’s high-speed characteristics and the low-power nature of four 5-bit 250MS/s time-interleaved SAR ADCs, leading to 8-bit 1GS/s operation. A combined sample-and-hold and digital-to-analog converter (SHDAC) circuit was introduced for front-end sampling and shifting of the sampled voltage to the optimum operating region of the next stage, which alleviates voltage swing requirements and thereby reduces power consumption of amplifiers. The simulation results suggest that the ADC can achieve a SNDR above 47.4dB with an estimated power of 17mW in 130nm CMOS technology with 1.2V supply. In comparison to the state-of-the-art, the presented architecture consumes low power and has a competitive FOM, especially considering the lower transition frequency (fT) of the technology compared to the majority of works in Table.
References
001
SAMP_CLK
The hybrid ADC was simulated in 130nm CMOS technology with a mix of blocks implemented as transistor-level designs (a) (CABS ADC with encoder, buffer amplifiers) and macro-models (Switches, flash ADC, bit alignment unit). Total estimated power : approx. 17mW. Figure of merit (FOM) with an input close to the Nyquist rate: 87.6 fJ/step (b) FOM = power / (fS × 2ENOB)
VXN
VON ɸ2
[1] G. Van der Plas and B. Verbruggen, “A 150 MS/s 133 µW 7 bit ADC in 90 nm Digital CMOS,” IEEE J. SolidState Circuits, vol. 43, no. 12, pp. 2631-2640, Dec. 2008. [2] J. Pernillo and M. P. Flynn, “A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS,” IEEE Trans. Circuits and Systems II: Express Briefs, vol. 58, no. 12, pp. 837-841, Dec. 2011. [3] S. Lee, A. P. Chandrakasan, and H-S. Lee, “A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration,” IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2846-2856, Dec. 2014. [4] B. Sung et. al., “A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration,” in Proc. IEEE Asian Solid-State Circuits Conf., pp. 281-284, Nov. 2013. [5] C.-J. Tseng, C. F. Lai, and H.-S. Chen, “A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration,” IEEE Trans. Circuits And Systems I: Regular Papers, vol. 31, no. 10, pp. 2805-2815, Oct. 2014.
