A Low-Power Polar Demodulator for Impedance Spectroscopy Based ...
A Low-Power Polar Demodulator for Impedance Spectroscopy Based on a Novel Sampling Scheme Soon-Jae Kweon, Jeong-Ho Park, Seong-Heon Shin, and Hyung-Joun Yoo The Department of Electrical Engineering and the Mobile Sensor and IT Convergence Center Korea Advanced Institute of Science and Technology 373-1 Guseong-dong, Daejeon, Republic of Korea [email protected], [email protected], [email protected], [email protected] Abstract— This paper proposes a low-power polar demodulator for electrical impedance spectroscopy. The magnitude and phase of impedance are measured by a novel sampling scheme and an XOR-based scheme, respectively. The novel sampling scheme only requires switched capacitor circuits and clock signals that are already used in the analog-to-digital conversion and the phase measurement. Since the proposed demodulator does not require any additional circuits for the magnitude measurement, low power consumption and small die areas can be achieved. The proposed demodulator designed using a 0.18-μm CMOS process consumes about 10-mW average power with 0.23-mm2 active area. (a)
Keywords-Demodulator, electrical impedance spectroscopy, impedance, magnitude, phase, polar, sampling.
I.
vr (t ) iin (t ) RREF I IN sin t RREF .
INTRODUCTION
Electrical impedance spectroscopy (EIS), which analyzes impedance over a frequency range, is widely used in electrochemical and biomedical applications [1]. To analyze the impedance of a material, a sinusoidal signal is injected into the target material, and the signal affected by this material is analyzed. Conventionally, real and imaginary parts of the impedance were extracted by a quadrature mixer and lowpass filters. However, long measurement time and synchronized signals were required [2], [3]. To overcome these limitations, polar demodulators were introduced [2]-[4]. Although the phase was measured by simple digital logics, such as XNOR, XOR, or SR latch, the magnitude was measured by power consuming analog circuits including a received signal strength indicator [2], a switching modulator and a lowpass filter [3], or a peak detector [4]. In addition, these analog circuits occupied large die areas due to large size capacitors. This paper proposes a low-power polar demodulator for EIS using a novel sampling scheme. This novel sampling scheme for magnitude measurement reuses switched capacitor circuits and clocks that are already used in other circuits of the demodulator. Therefore, low power consumption and small die areas could be achieved. II.
(b)
Figure 1. (a) Block diagram and (b) signal diagram of the proposed polar demodulator
PROPOSED POLAR DEMODULATOR
Fig. 1 shows the block diagram and signal diagram of the proposed polar demodulator. When a sinusoidal current signal iin(t) is injected into the reference resistor (RREF), it generates a voltage signal vr(t) which can be expressed as
(1)
Another voltage signal vm(t) generated by the impedance of the target material (ZM) has a time delay (Td) with respect to vr(t), and is expressed as vm (t ) iin (t ) Z M I IN sin t Td Z M .
(2)
Two instrumentation amplifiers (IAs) amplify vr(t) and vm(t). Two comparators generate two clock signals, which are expressed as ϕr(t) and ϕm(t), using the amplified signals. An XOR creates ϕp(t) whose pulse width equals Td caused by ZM [3]. The phase of ZM can be obtained as Z M
Td 360. Tin
(3)
Switched capacitors circuits sample the amplified vr(t) and vm(t) at T1+Td and T1 using the clocks ϕm(t) and ϕr(t), respectively. The ratio between these two sampled values is expressed as I IN sin T1 Td Z M Z GIA vm T1 M . GIA vr T1 Td I IN sin T1 Td RREF RREF
(4)
Equation (4) is obtained since 2πf=π/T1. By multiplying (4) by RREF, the magnitude of ZM can be obtained.
This work was supported by IC Design Education Center (IDEC).
-page number-
ISOCC 2015
3000
Calculation Simulation (tt/27)
Reactance (ohm)
2500 0.8kHz 2000
0.4kHz
1.6kHz
1500 0.2kHz 3.2kHz
1000
0.1kHz
6.4kHz
500
12.8kHz 0
102.4kHz 0
1000
2000
3000
4000
5000
Resistance (ohm)
(a) (a)
(b)
2.5
Figure 2. (a) Block diagram of the IA (b) Schematic of the comparator
Magnitude error (tt/27) Phase error (tt/27) Magnitude error (ss/85) Phase error (ss/85) Magnitude error (ff/40) Phase error (ff/40)
2.0
Error (%)
1.5 1.0 0.5 0.0 -0.5 -1.0
0.125 0.25 0.5
1
2
4
8
16
32
64 128
Frequency (kHz)
(b) Figure 3. Chip layout. The marked area shows 1: the IA, 2: two comparators and an XOR, 3: the switched capacitor circuit, 4: digital buffers, 5: an analog buffer
Fig. 2 (a) shows the block diagram of the IA using a three op-amp topology [5]. The gain of the IA is varied from 0 dB to 48 dB with a 6 dB gain step. Fig. 2 (b) shows the schematic of the comparator using an inverter-based amplifier [6]. The process compensated inverters are used to reduce the effects of the temperature and process variations [7]. The comparator has a delay of about 3 ns. III.
SIMULATION RESULTS
The proposed polar demodulator was designed in a 0.18m CMOS process and the chip layout is shown in Fig. 3. Fig. 4 (a) shows the simulated Cole-Cole plot. An equivalent circuit of ZM is assumed to be a 200-ohm resistor in series with the parallel combination of a 45-nF capacitor and a 5-kohm resistor [3]. The frequency varies from 0.1 kHz to 102.4 kHz in logarithmic scale. The simulated Cole-Cole plot shows a good agreement with the theoretical one. Fig. 4 (b) shows the PVT simulation results for magnitude and phase errors. The maximum magnitude error is about 1.9% when a 102.4-kHz signal is used in ss/85˚C. This is due to the increased delay of the comparator. Table I summarizes the performances of several polar demodulators. The proposed polar demodulator has smaller die area and lower power consumption compared to previous works. The magnitude error in ss/85˚C is lower than those of the previous works as well.
Figure 4. (a) Simulation results for Cole-Cole plot (b) PVT simulation results for magnitude error and phase error TABLE I. Parameters
This worka
[2]b
[3]b
[4]b
Process (m)
0.18
0.35
0.35
0.18
1.8
3.0
±2.5
±0.9
Active area (mm )
0.23
0.30
0.40
0.40
Power consumption (mW)
10
N/A
21
28
Frequency range (kHz)
0.1-100
1-1000
0.1-100
0.1-105
Magnitude error (%)
Keywords-Demodulator, electrical impedance spectroscopy, impedance, magnitude, phase, polar, sampling.
I.
vr (t ) iin (t ) RREF I IN sin t RREF .
INTRODUCTION
Electrical impedance spectroscopy (EIS), which analyzes impedance over a frequency range, is widely used in electrochemical and biomedical applications [1]. To analyze the impedance of a material, a sinusoidal signal is injected into the target material, and the signal affected by this material is analyzed. Conventionally, real and imaginary parts of the impedance were extracted by a quadrature mixer and lowpass filters. However, long measurement time and synchronized signals were required [2], [3]. To overcome these limitations, polar demodulators were introduced [2]-[4]. Although the phase was measured by simple digital logics, such as XNOR, XOR, or SR latch, the magnitude was measured by power consuming analog circuits including a received signal strength indicator [2], a switching modulator and a lowpass filter [3], or a peak detector [4]. In addition, these analog circuits occupied large die areas due to large size capacitors. This paper proposes a low-power polar demodulator for EIS using a novel sampling scheme. This novel sampling scheme for magnitude measurement reuses switched capacitor circuits and clocks that are already used in other circuits of the demodulator. Therefore, low power consumption and small die areas could be achieved. II.
(b)
Figure 1. (a) Block diagram and (b) signal diagram of the proposed polar demodulator
PROPOSED POLAR DEMODULATOR
Fig. 1 shows the block diagram and signal diagram of the proposed polar demodulator. When a sinusoidal current signal iin(t) is injected into the reference resistor (RREF), it generates a voltage signal vr(t) which can be expressed as
(1)
Another voltage signal vm(t) generated by the impedance of the target material (ZM) has a time delay (Td) with respect to vr(t), and is expressed as vm (t ) iin (t ) Z M I IN sin t Td Z M .
(2)
Two instrumentation amplifiers (IAs) amplify vr(t) and vm(t). Two comparators generate two clock signals, which are expressed as ϕr(t) and ϕm(t), using the amplified signals. An XOR creates ϕp(t) whose pulse width equals Td caused by ZM [3]. The phase of ZM can be obtained as Z M
Td 360. Tin
(3)
Switched capacitors circuits sample the amplified vr(t) and vm(t) at T1+Td and T1 using the clocks ϕm(t) and ϕr(t), respectively. The ratio between these two sampled values is expressed as I IN sin T1 Td Z M Z GIA vm T1 M . GIA vr T1 Td I IN sin T1 Td RREF RREF
(4)
Equation (4) is obtained since 2πf=π/T1. By multiplying (4) by RREF, the magnitude of ZM can be obtained.
This work was supported by IC Design Education Center (IDEC).
-page number-
ISOCC 2015
3000
Calculation Simulation (tt/27)
Reactance (ohm)
2500 0.8kHz 2000
0.4kHz
1.6kHz
1500 0.2kHz 3.2kHz
1000
0.1kHz
6.4kHz
500
12.8kHz 0
102.4kHz 0
1000
2000
3000
4000
5000
Resistance (ohm)
(a) (a)
(b)
2.5
Figure 2. (a) Block diagram of the IA (b) Schematic of the comparator
Magnitude error (tt/27) Phase error (tt/27) Magnitude error (ss/85) Phase error (ss/85) Magnitude error (ff/40) Phase error (ff/40)
2.0
Error (%)
1.5 1.0 0.5 0.0 -0.5 -1.0
0.125 0.25 0.5
1
2
4
8
16
32
64 128
Frequency (kHz)
(b) Figure 3. Chip layout. The marked area shows 1: the IA, 2: two comparators and an XOR, 3: the switched capacitor circuit, 4: digital buffers, 5: an analog buffer
Fig. 2 (a) shows the block diagram of the IA using a three op-amp topology [5]. The gain of the IA is varied from 0 dB to 48 dB with a 6 dB gain step. Fig. 2 (b) shows the schematic of the comparator using an inverter-based amplifier [6]. The process compensated inverters are used to reduce the effects of the temperature and process variations [7]. The comparator has a delay of about 3 ns. III.
SIMULATION RESULTS
The proposed polar demodulator was designed in a 0.18m CMOS process and the chip layout is shown in Fig. 3. Fig. 4 (a) shows the simulated Cole-Cole plot. An equivalent circuit of ZM is assumed to be a 200-ohm resistor in series with the parallel combination of a 45-nF capacitor and a 5-kohm resistor [3]. The frequency varies from 0.1 kHz to 102.4 kHz in logarithmic scale. The simulated Cole-Cole plot shows a good agreement with the theoretical one. Fig. 4 (b) shows the PVT simulation results for magnitude and phase errors. The maximum magnitude error is about 1.9% when a 102.4-kHz signal is used in ss/85˚C. This is due to the increased delay of the comparator. Table I summarizes the performances of several polar demodulators. The proposed polar demodulator has smaller die area and lower power consumption compared to previous works. The magnitude error in ss/85˚C is lower than those of the previous works as well.
Figure 4. (a) Simulation results for Cole-Cole plot (b) PVT simulation results for magnitude error and phase error TABLE I. Parameters
This worka
[2]b
[3]b
[4]b
Process (m)
0.18
0.35
0.35
0.18
1.8
3.0
±2.5
±0.9
Active area (mm )
0.23
0.30
0.40
0.40
Power consumption (mW)
10
N/A
21
28
Frequency range (kHz)
0.1-100
1-1000
0.1-100
0.1-105
Magnitude error (%)
