A low-voltage CMOS low-dropout regulator with ... - Semantic Scholar
A LOW-VOLTAGE CMOS LOW-DROPOUT REGULATOR WITH ENHANCED LOOP RESPONSE Ka Nang Leung, Philip K. T. Mok and Sai Kit Lau Department of Electrical and Electronic Engineering The Hong Kong University of Science and Technology Clear Water Bay, Hong Kong SAR Tel: (852) 2358-8517 Fax: (852) 2358-1485 Emails: [email protected] and [email protected] ABSTRACT A 1.5-V 100-mA CMOS low-dropout regulator based on a novel structure, with a double pole-zero cancellation scheme and a linearly operated power PMOS transistor at dropout to enhance the loop-gain response, is presented. The circuit realization is well-studied and developed with respect to the loop-gain response, the transient response, the output noise and the output accuracy, as well as the standby power consumption. Implemented in a 0.6Pm CMOS process, experimental results show that the regulator provides a full load transient response of less than 1-Ps settling time and less than 50-mV overshoots and undershoots. Moreover, it provides a ripple rejection of better than -26 dB and an output noise of 0.07 PV/sqrt Hz at 100 kHz. 1. INTRODUCTION Low-dropout voltage regulator (LDO) has demonstrated lownoise high-accuracy and fast-response performance and thereby is widely utilized to power up advanced analogue and radiofrequency integrated circuits. Recently, LDO design has become more challenging due to the increasing demand of highperformance LDOs, of which low-voltage fast-transient LDOs are especially important [1]. Methods to improve the classical LDO structure have been proposed [1]-[4]. However, structural limitation, which is the main obstacle to simultaneously achieving stability, high output-voltage accuracy and short response time, still cannot be overcome.
proposed in this paper. An advanced frequency compensation approach is also presented to stabilize the proposed LDO for obtaining high stability and fast transient responses simultaneously. Moreover, the silicon area of the passive components is minimized. 2. PROPOSED LOW-DROPOUT REGULATOR The structure of the proposed LDO is shown in Fig. 1. It is composed of two moderate-gain stages. The first one, as in the classical LDO, is the error amplifier to provide error signal for voltage regulation, and the second gain stage has a high output swing. Due to the cascade architecture, the loop gain depends on the products of the voltage gains of the two gain stages. The high loop gain provides good line and load regulations [2], [11]. The circuit structures of the error amplifier and the second gain stage are very simple. The circuit diagram in Fig. 1 shows that the error amplifier is a differential pair (M2 and M3) with active load (M4 and M5), while the second gain stage is a commonsource stage (M6) with a bias-current source (M7). The output swing of the second stage is much better than the source follower in turning on or off the power transistor, and therefore this configuration is suitable for low-voltage LDO designs.
∆VG /Av2
power transistor I OUT
negative gain stage Rf2 error amplifier
Cf2
COUT
voltage reference
M8
M1
M7
MPT
VOUT
Resr
Rf1
input-voltage supply
off-chip capacitor and its ESR I OUT
∆VG IBIAS
M2
M3 Rf2
VIN
This work was supported by the Research Grant Council of Hong Kong SAR Government, China, under Project no. HKUST6022/01E.
;,(((
MPT
VREF VIN
In fact, the structural limitation of the classical LDOs is mainly due to the associated single pole-zero cancellation scheme, in which an off-chip capacitor with a high equivalent series resistance (ESR) is required to achieve low-frequency pole-zero cancellation [1]-[10]. The resultant loop gain is not sufficiently high to achieve good line and load regulations [2], [11] and the loop-gain bandwidth is also not sufficiently wide for short response time [1], [10], [11]. In addition, the required high ESR introduces undesirable large overshoots and undershoots during load transient responses [1], [10]. Low-voltage design is also limited by the voltage buffers inside the classical LDOs. Further improvement on the classical structure is difficult due to the constraint of LDO stability. Undoubtedly, additional circuitries for improving the performance of the classical LDOs increase the circuit complexity and so consume more power. Therefore, instead, a novel LDO with a very simple circuit structure is
∆VG
,
VREF
M4
M5
∆VG /Av2
M6 Rf1
Cf2
COUT
VOUT
Resr
Fig. 1: Structure and circuit diagram of the proposed LDO.
,6&$6
The power transistor is designed to operate in linear region at dropout for a smaller transistor size. Although the voltage gain of the power transistor is less than unity, the loop gain is not degraded due to the error amplifier and the second gain stage. A loop gain of more than 80 dB can be easily achieved in the proposed design and is already sufficient for good line and load regulations [11]. In the proposed design, the required transistor size is reduced by two-third. The smaller gate capacitance is undoubtedly an advantage to improve the slew rate at the gate of the power transistor and to improve the frequency response of the proposed LDO structure [11]. A CMOS voltage reference, which is based on the principle of the temperature dependence of threshold-voltage difference, is used [12]. The CMOS voltage reference does not depend on parasitic BJT and can be designed as well as optimized by a resistance ratio and a transistor-size ratio [12]. The proposed LDO has three LHP poles, which are created at the LDO output (p1), the second-stage output (p2) and the erroramplifier output (p3), respectively. The corresponding pole frequencies can be expressed by p1
1 COUT rop
p2
1 C g Roa
OI OUT COUT
cancellations must be performed within one decade of frequency. Moreover, pf is designed such that it is higher than the designed unity-gain frequency (UGF = 1 MHz in the proposed design) by at least two times of frequency for a sufficient phase margin. Compared with the loop-gain response of the classical LDO, both loop gain and UGF of the proposed LDO are higher than those of the classical LDO. This provides better line and load regulations as well as faster transient responses. Moreover, zesr in the proposed LDO has a higher frequency than that (zcesr) in the classical LDO implying that a smaller ESR under the same output capacitance is needed. The smaller ESR is important in reducing the overshoots and undershoots [10]. L(j ω) in dB
p1
pc1
zesr p2
(2)
p3
The frequency compensation can be achieved by two pole-zero cancellations. One LHP zero (zesr) is the same as the classical LDOs and is generated by COUT and Resr as given by z esr 1 COUT Resr (4) while another LHP zero (zf) is created by the feedback resistors and Cf2 as given by z f 1 C f 2Rf 2 (5)
This method makes use of the feedback resistor that must be present in any LDO design to create the zero, and therefore the additional chip area is only due to Cf2. As the feedback resistors are generally large (about several hundreds k: to several M:) to minimize the power loss at the feedback resistors, the required Cf2 is very small. In the proposed design, a Cf2 of about 1 pF is needed. The coupling noise by the small Cf2 is therefore negligible. Moreover, the transient response is not affected as Cf2 is connected to the LDO output. In fact, a LHP pole (pf) is created simultaneously with zf, and its position is given by
1 C f 2 R f 1 // R f 2
pole-zero cancellations
(1)
p3 1 C a Roea (3) where Roea and Roa are the output resistances of the first and second gain stage, respectively, while Ca and Cg is the gate capacitances of the second stage and the power transistor operating in linear region, respectively. Since there are two cascade gain stages to ensure a high loop gain, the gain of each stage needs not be too high. As a result, both Roea and Roa are relatively smaller than the output resistance of the error amplifier in the classical LDOs.
pf
Proposed LDO
loop-gain improvement
(6)
From (5) and (6), zf
proposed in this paper. An advanced frequency compensation approach is also presented to stabilize the proposed LDO for obtaining high stability and fast transient responses simultaneously. Moreover, the silicon area of the passive components is minimized. 2. PROPOSED LOW-DROPOUT REGULATOR The structure of the proposed LDO is shown in Fig. 1. It is composed of two moderate-gain stages. The first one, as in the classical LDO, is the error amplifier to provide error signal for voltage regulation, and the second gain stage has a high output swing. Due to the cascade architecture, the loop gain depends on the products of the voltage gains of the two gain stages. The high loop gain provides good line and load regulations [2], [11]. The circuit structures of the error amplifier and the second gain stage are very simple. The circuit diagram in Fig. 1 shows that the error amplifier is a differential pair (M2 and M3) with active load (M4 and M5), while the second gain stage is a commonsource stage (M6) with a bias-current source (M7). The output swing of the second stage is much better than the source follower in turning on or off the power transistor, and therefore this configuration is suitable for low-voltage LDO designs.
∆VG /Av2
power transistor I OUT
negative gain stage Rf2 error amplifier
Cf2
COUT
voltage reference
M8
M1
M7
MPT
VOUT
Resr
Rf1
input-voltage supply
off-chip capacitor and its ESR I OUT
∆VG IBIAS
M2
M3 Rf2
VIN
This work was supported by the Research Grant Council of Hong Kong SAR Government, China, under Project no. HKUST6022/01E.
;,(((
MPT
VREF VIN
In fact, the structural limitation of the classical LDOs is mainly due to the associated single pole-zero cancellation scheme, in which an off-chip capacitor with a high equivalent series resistance (ESR) is required to achieve low-frequency pole-zero cancellation [1]-[10]. The resultant loop gain is not sufficiently high to achieve good line and load regulations [2], [11] and the loop-gain bandwidth is also not sufficiently wide for short response time [1], [10], [11]. In addition, the required high ESR introduces undesirable large overshoots and undershoots during load transient responses [1], [10]. Low-voltage design is also limited by the voltage buffers inside the classical LDOs. Further improvement on the classical structure is difficult due to the constraint of LDO stability. Undoubtedly, additional circuitries for improving the performance of the classical LDOs increase the circuit complexity and so consume more power. Therefore, instead, a novel LDO with a very simple circuit structure is
∆VG
,
VREF
M4
M5
∆VG /Av2
M6 Rf1
Cf2
COUT
VOUT
Resr
Fig. 1: Structure and circuit diagram of the proposed LDO.
,6&$6
The power transistor is designed to operate in linear region at dropout for a smaller transistor size. Although the voltage gain of the power transistor is less than unity, the loop gain is not degraded due to the error amplifier and the second gain stage. A loop gain of more than 80 dB can be easily achieved in the proposed design and is already sufficient for good line and load regulations [11]. In the proposed design, the required transistor size is reduced by two-third. The smaller gate capacitance is undoubtedly an advantage to improve the slew rate at the gate of the power transistor and to improve the frequency response of the proposed LDO structure [11]. A CMOS voltage reference, which is based on the principle of the temperature dependence of threshold-voltage difference, is used [12]. The CMOS voltage reference does not depend on parasitic BJT and can be designed as well as optimized by a resistance ratio and a transistor-size ratio [12]. The proposed LDO has three LHP poles, which are created at the LDO output (p1), the second-stage output (p2) and the erroramplifier output (p3), respectively. The corresponding pole frequencies can be expressed by p1
1 COUT rop
p2
1 C g Roa
OI OUT COUT
cancellations must be performed within one decade of frequency. Moreover, pf is designed such that it is higher than the designed unity-gain frequency (UGF = 1 MHz in the proposed design) by at least two times of frequency for a sufficient phase margin. Compared with the loop-gain response of the classical LDO, both loop gain and UGF of the proposed LDO are higher than those of the classical LDO. This provides better line and load regulations as well as faster transient responses. Moreover, zesr in the proposed LDO has a higher frequency than that (zcesr) in the classical LDO implying that a smaller ESR under the same output capacitance is needed. The smaller ESR is important in reducing the overshoots and undershoots [10]. L(j ω) in dB
p1
pc1
zesr p2
(2)
p3
The frequency compensation can be achieved by two pole-zero cancellations. One LHP zero (zesr) is the same as the classical LDOs and is generated by COUT and Resr as given by z esr 1 COUT Resr (4) while another LHP zero (zf) is created by the feedback resistors and Cf2 as given by z f 1 C f 2Rf 2 (5)
This method makes use of the feedback resistor that must be present in any LDO design to create the zero, and therefore the additional chip area is only due to Cf2. As the feedback resistors are generally large (about several hundreds k: to several M:) to minimize the power loss at the feedback resistors, the required Cf2 is very small. In the proposed design, a Cf2 of about 1 pF is needed. The coupling noise by the small Cf2 is therefore negligible. Moreover, the transient response is not affected as Cf2 is connected to the LDO output. In fact, a LHP pole (pf) is created simultaneously with zf, and its position is given by
1 C f 2 R f 1 // R f 2
pole-zero cancellations
(1)
p3 1 C a Roea (3) where Roea and Roa are the output resistances of the first and second gain stage, respectively, while Ca and Cg is the gate capacitances of the second stage and the power transistor operating in linear region, respectively. Since there are two cascade gain stages to ensure a high loop gain, the gain of each stage needs not be too high. As a result, both Roea and Roa are relatively smaller than the output resistance of the error amplifier in the classical LDOs.
pf
Proposed LDO
loop-gain improvement
(6)
From (5) and (6), zf
