A low-voltage CMOS rail-to-rail operational ... - Semantic Scholar
A Low-Voltage CMOS Rail-To-Rail Operational Amplifier Using Double P-Channel Differential Input Pairs Chun-Jen Huang and Hong-Yi Huang [email protected] [email protected] Department of Electronic Engineering Fu-Jen Catholic University Taiwan ABSTRACT This work presents a low-voltage CMOS amplifier. The amplifier combines a p-channel differential input pair and a level-shift p-channel differential input pair to obtain railto-rail signaling. Simulations using a 0.35um 2p4m CMOS process at 1V supply voltage, the amplifier performs 76 dB dc gain, 5.27 MHz unit-gain bandwidth, 288uW power dissipation and 84o phase margin at 15 pF output load.
I. INTRODUCTION With the increasing demands of portable applications, reducing the power dissipation and operating at low supply voltages are the trends of CMOS amplifiers design. The Op Amp is the basic building cell in a mixed-signal circuit. To achieve a rail-to-rail signaling at the inputs, the complementary differential input pairs are selected [1]. However, when the supply voltage is below Vt,NMOS+ |Vt,PMOS|+VDS,NMOS+|VDS,PMOS|, there is a dead zone in the middle of supply voltage [1]. Therefore, the operating supply of the complementary differential input pairs are limited by two threshold voltages plus two overdrive voltages. To operate the amplifier at low supply voltage, a basic approach is to connect the source and the bulk terminals to eliminate the body effect. Beside, selecting a large aspect ratio (W/L) can reduce the overdrive voltage. Additional, several approaches have been reported to achieve low operating voltage, such as applying a feed forward technique or a negative feedback technique at the input stage [1], the use of “virtual transistor” [2], floatinggate transistors [3] or bulk-driven transistors [4]. Using the skills of current driven bulk [5] and floating voltage controlled voltage source [6] can also reduce the operating supply voltage. The complementary differential input pairs using the feed forward technique show an offset voltage resulting from the variation of the input commonmode voltage. The negative feedback technique requires an extra injecting current to improve the slew rate. The
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complicated control of “virtual transistor” [2] is composed of a frequency divider, a clock booster and a bias voltage generator. A special process is necessary for the floating gate transistor [3] that increases the cost. The bulk-driven transistors [4] have smaller transconductance and worse frequency response than the conventional amplifiers. The floating voltage controlled voltage source [6] is applied to a unit-gain buffer only. It has not been implemented in high-gain Op Amps. In this work, a scheme using double p-channel differential pairs is presented. A rail-to-rail signaling can be obtained at very low supply voltage. The circuit structure and the operation of the amplifier are introduced in section II. The post simulation results and comparisons are given in section III. Section IV concludes the summary. II. CIRCUIT STRUCTURE AND OPERATING PRINCIPLE
˩˖ˠ
́ ˀ˶ ˻ ˴ ́ ́ ˸ ˿ʳ̃ ˴ ˼̅ʳ̂ ́ ˗˸ ˴ ˷ ʳ̍̂ ́ ˸ ̃ ˀ˶ ˻ ˴ ́ ́ ˸ ˿ʳ̃ ˴ ˼̅ʳ̂ ́
Fig. 1 Complementary differential input pairs. The complementary differential pairs can achieve rail-to-rail signaling at the inputs. There is still a limitation at very low supply voltage. Fig. 1 shows the input dead zone of the complementary differential pairs. Fig. 2 shows the proposed double p-channel differential input pairs composed of a p-channel differential input pair (M1A, M2A) and level-shift p-channel differential input pair (M1~M4). The differential pairs are parts of a folded cascode amplifier. The p-channel differential input pairs are chosen because of an n-well process. The bulk
,
,6&$6
terminals of the devices in the differential input pairs are connected to their source terminals to eliminate the body effect. Connecting the output node of the amplifier to its negative input terminal, a unit-gain buffer is formed. Fig. 3 plots the waveforms of the unit-gain amplifiers. At 0.8V supply voltage, a single p-channel and a single level-shift p-channel differential input pair can only obtain 0-0.4V and 0.4-0.8V output swings, respectively. Combining the two differential input pairs, a rail-to-rail input commonmode range can be obtained as shown in Fig. 4.
ˠˆ ˠ˅˔
˩˼́ ʾ
˩˼̃ ˀ ˜˵ ́ ˄
˩˼̃ ʾ ˠ˄
ˠ˅
double p-channel
Fig.4 Simulated waveforms of a unit-gain buffer using double p-channel differential input pairs. Fig. 5 shows the complete circuit structure of the railto-rail amplifier using double p-channel differential input pairs. The input stage is composed of a p-channel differential pair (M1A, M2A), a level-shift p-channel differential pair (M1, M2, M3, M4), and bias current sources (M7, M7A, M12, M13). The input common-mode range VCM1 of the p-channel differential pair M1A and M2A is
ˠˇ ˠ˄˔
Vin
0ЉVCM1ЉVDD -VSD,M7A -VSG,M1A
˜˵ ́ ˅
The input common-mode range VCM2 of the levelshift p-channel differential pair M1~M4 is
Fig. 2 The double p-channel differential input pairs. If VGS3 and VGS4 are less than Vt,NMOS, the sourcefollower devices M3 and M4 are turned off. Consequently, Vip+ and Vip- are almost shorted to ground through the path of Ibn1 and Ibn2. Then, M1 and M2 are turned on. Even if M3 and M4 work in weak inversion, the small signal can still pass to Vip+ and Vip-. Since M1 and M2 operate at strong inversion in most of range, the small signal can be amplified without severe degradation. If VGS3 and VGS4 are larger than Vt,NMOS, the devices M3 and M4 are turned on. The input common-mode voltage VCM’ of Vip+ and Vip- are equal to VCM -Vt,NMOS where VCM is the common-mode voltage of the level-shift differential input pair. In other words, VCM is equal to VCM’+Vt,NMOS. Therefore, the differential input pair M1A and M2A can operate at a higher input common-mode voltage.
VGS,M3+VDS,M12 Љ VCM 2 Љ VDD -VSD,M7 - VSG,M1 +VGS,M3 (2) To achieve a rail-to-rail signaling at the inputs, the following conditions have to be satisfied. The W/L ratios of M1~M4 must be large enough to sustain VSG, M1Ѝ VGS,,M3ЍVtnЍ-Vtp
level-shift p-channel
(3)
Therefore, VGS,M3+VDS,M12ЉVCM 2Љ VDD -VSD,M7
(4)
The upper limit of VCM1 has to be larger than the lower limit of VCM2. VGS,M3+VDS,M12ЉVDD -VSD,M7A -VSG,M1A
(5)
Therefore, VDDЊVSG,M1A+VGS,M3+VSD,M7A+VDS,M12
p-channel
(1)
Vin
(6)
Combining Eq. (1) and Eq. (4) ,
Fig. 3 Simulated waveforms of unit-gain buffers of a single p-channel and a single level-shift p-channel differential pairs.
,
VCM=VCM1+VCM2
(7)
0ЉVCMЉ VDD -VSD, M7AЍ VDD
(8)
With proper sizing of M7 and M7A to reduce VSD,M7A, the input common-mode voltage can be from ground to VDD. Fig. 6 plots the overlapped operating input commonmode range of the two differential input pairs.
respectively. A rail-to-rail signaling of a unit-gain buffer can be obtained at 0.6V supply voltage. An open-loop rail-to-rail output swing can be derived at 0.8V supply voltage. The proposed amplifier has a better bandwidth and slew rate due to a simpler circuit structure.
ˢ̉˸ ̅˿˴ ̃ ̃ ˸ ˷ ˩˖ˠʳ˄ ˩˖ˠʳ˅
REFERENCES [1]
˩˖ˠ
Fig. 6 Overlapped operating range of the two differential input pairs
[2]
. III. POST SIMULATION RESULTS & COMPARISONS
[3]
Table I lists the device dimensions of the amplifier. Long channel devices are chosen for smaller device threshold voltages. The devices (M14~M17) in the cascode structure use longer channel length for the same reason. It is expected that at least one of the differential input pair keeps active during the transition. At 1V supply voltage, the p-channel pair is off when VCM is 0.6V. In this condition, M1A and M2A are off, M7A operates in linear region. The level-shift p-channel differential input pair (M1~M4, M12, M13), current summing circuit (M8, M9, M14~M17) and output stage (M10, M18) operate in saturation region. The 0.35um CMOS n-well process device modes are used for spice simulation. The typical threshold voltages of the n-channel and p-channel devices are 0.52V and –0.74V, respectively. We obtain VSG,M1A=0.4V, VGS,M3=0.562V, VSD, M7AЍ0V and VDS,M12 =0.096V from the simulation. The results satisfy Eq. (6). Fig.8 shows the layout of complete circuit. Table II summarizes the post simulation results and comparisons. The proposed amplifier has a simpler circuit structure than the others. A higher bandwidth is obtained. With similar power consumption, the proposed amplifier has better slew rates. The simulation results at lower supply voltages are listed in Table III. Fig. 7 plots the simulation waveforms of the amplifier as a unit-gain buffer at 0.6V supply voltage. It appears that the proposal structure can reach rail-to-rail signaling. The minimum supply voltage of an open-loop amplifier to obtain a rail-to-rail output swing is 0.8V. Under this condition, the amplifier has 49.1dB dc gain, 0.76MHz unit-gain bandwidth and 86o phase margin at 15pF output load.
[4]
[5]
[6]
J. Francisco Duque-Carrillo, Jose L. Ausin and Guido Torelli, “1-V rail-to-rail operational amplifiers in standard CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, No. 1, pp.33-43, Jan. 2000. Yong Hui Tang and Randall L. Geiger, “A 0.6V ultra low voltage operational amplifier,” in Proc. 2002 ISCAS, vol. 3, pp.611-614 May 2002. J. Ranirez-Angulo S.C. Choi and G. Gonzalez-Altamirano, “Low-voltage circuit building blocks using multiple-input floating gate transistors,” IEEE Trans. Circuits Syst. I, vol. 42, No.11, pp.971-974, Nov. 1995. Benjanmin J. Blalock, Phillip E. Allen and Gabriel A. Rincon-Mora, “Designing 1-V Op Amps using standard digital CMOS technology” IEEE Trans. Circuits Syst. II, vol. 45, No.7, pp.760-780, Jul. 1998. Torsten Lehmann and Marco Cassia,“1-V power Supply CMOS cascode amplifier,” IEEE J. Solid-State Circuits, Vol. 36, No. 7, pp.1082-1086, Jul. 2001. J. Ranirez-Angulo, A. Torralba, R.G. Carvajal and J. Jombs, “Low-voltage CMOS amplifier with wide inputoutput swing based on a novel scheme” IEEE Trans. Circuits Syst. I, vol. 47, No.5, pp.772-774, May. 2000.
Vin Vout
Fig. 7 Simulation waveforms of an unit-gain buffer at 0.6V supply voltage.
IV. CONCLUSION A scheme using double p-channel differential input pairs is applied to a CMOS rail-to-rail amplifier for lowvoltage operation. The typical threshold voltages for a 0.35um CMOS n-well process are 0.52V and –0.74V,
,
Table I Device dimensions of the amplifier. MOS
W (um)
L (um)
M1,M2,M1A,M2A
200
2
M3,M4,M11,M12,M13
120
2
M6,M7,M7A,M8,M9
400
2
M14,M15,M16,M17
300
4
M5
100
2
M10
1600
2
M18
475
2
Rb=27.5Kȍ, Rm=2.25Kȍ,Cm=8pF,CL=15pF
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ˠˉ
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ˠˌ
ˠ˄˃
ˠˇ ˠ˄˔
ˠ˅˔ ˩˼́ ʾ
˩˼́ ˀ
ˠ˄ˇ
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˥˵ ˩˼̃ ˀ
˩˼̃ ʾ ˠ˄
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˖̈ ̅̅˸ ́ ̇ʳ̆ ̈ ̀ ̀ ˼́ ˺ ʳ˶ ˼̅˶ ̈ ˼̇
˗̂ ̈ ˵ ˿˸ ʳ̃ ˀ˶ ˻ ˴ ́ ́ ˸ ˿ʳ˷ ˼˹˹˸ ̅˸ ́ ̇˼˴ ˿ʳ˼́ ̃ ̈ ̇ʳ̃ ˴ ˼̅̆
Fig. 5 Complete circuit of the double p-channel differential input pairs rail-to-rail amplifier. Table II Comparisons of low voltage Op Amps at 1V supply voltage. Feedfoward Feedback Ref [1] Ref [1]
Parameters Process
1.2um
Vtn,Vtp (V)
1.2um
0.75, -0.75 0.75, -0.75
Supply voltage (V) ICMR (V)
C.D.B. Ref [5]
This work
0.5um
0.35um
0.6,-0.6
0.52,-0.74
1
1
1
1
rail to rail
rail to rail
0.0~0.65
0.01~0.99
Power dissipation (uW)
410
208
-
288
dc gain (dB )
87
70.5
62-69
75.9
2
5.27
Unit-gian bandwidth (MHz)
1.9
P.M. Output swing (V)
61 -
Load, CL (pF)
15
15
-
15
CMRR (dB)
62
58
-
76.8
PSRR+ (dB)
-
-
-
69.9
PSRR- (dB)
o
2.1 73 -
o
o
57 0.35-0.75
o
84 0.05~0.94
-
-
-
69.2
Slew rate V/us (SR+)
0.8
0.9
0.5
3.2
Slew rate V/us (SR-)
1
1.7
-
3.9
-4~6
-2
-
-
Offset (mV)
Fig. 8 Layout of complete circuit.
Table III Performance of post simulation at different operating voltages. Parameters
˩̂ ̈ ̇
˖̀
ˠ˄˅
˕˼˴ ̆ ʳ˶ ˼̅˶ ̈ ˼̇
˥̀
ˠ˅
2P4M 0.35um CMOS technology Vtn=0.52V, Vtp=-0.74V, C L=15pF
Supply voltage (V)
1
0.9
0.8
0.7
0.6
ICMR (V)
0.01~0.99
0.01~0.89
0.01~0.79
0.01~0.69
0.01~0.58
Power dissipation (uW)
288
177
92
34
7
dc gain (dB)
75.9
72.2
49.1
32.9
23.4
Unit gian Bandwidth (MHz)
5.27
2.12
0.76
0.16
0.02
P.M. Output swing (V)
84o 0.05~0.943
91o 0.05~0.84
86o 0.06~0.69
87o 0.1~0.37
91o 0.1~0.2
CMRR (dB)
76.8
67.2
58.0
51.5
48.1
PSRR+ (dB)
69.9
83.6
50.5
41.4
23.9
PSRR- (dB)
69.2
66.9
62.0
59.4
64.8
Slew rate v/us (SR+)
3.2
2.1
1
0.3
0.05
Slew rate v/us (SR-) Noise (nV/√Hz) T.H.D. at 1KHz, 0.5 Vpp (%)
3.9 66 0.08
2.7 105 0.22
1.4 104 0.91
0.4 103 4
0.08 101 12
,
ˠ˄ˋ
˖˟
ˢ ̈ ̇̃ ̈ ̇ʳ̆ ̇˴ ˺ ˸
I. INTRODUCTION With the increasing demands of portable applications, reducing the power dissipation and operating at low supply voltages are the trends of CMOS amplifiers design. The Op Amp is the basic building cell in a mixed-signal circuit. To achieve a rail-to-rail signaling at the inputs, the complementary differential input pairs are selected [1]. However, when the supply voltage is below Vt,NMOS+ |Vt,PMOS|+VDS,NMOS+|VDS,PMOS|, there is a dead zone in the middle of supply voltage [1]. Therefore, the operating supply of the complementary differential input pairs are limited by two threshold voltages plus two overdrive voltages. To operate the amplifier at low supply voltage, a basic approach is to connect the source and the bulk terminals to eliminate the body effect. Beside, selecting a large aspect ratio (W/L) can reduce the overdrive voltage. Additional, several approaches have been reported to achieve low operating voltage, such as applying a feed forward technique or a negative feedback technique at the input stage [1], the use of “virtual transistor” [2], floatinggate transistors [3] or bulk-driven transistors [4]. Using the skills of current driven bulk [5] and floating voltage controlled voltage source [6] can also reduce the operating supply voltage. The complementary differential input pairs using the feed forward technique show an offset voltage resulting from the variation of the input commonmode voltage. The negative feedback technique requires an extra injecting current to improve the slew rate. The
;,(((
complicated control of “virtual transistor” [2] is composed of a frequency divider, a clock booster and a bias voltage generator. A special process is necessary for the floating gate transistor [3] that increases the cost. The bulk-driven transistors [4] have smaller transconductance and worse frequency response than the conventional amplifiers. The floating voltage controlled voltage source [6] is applied to a unit-gain buffer only. It has not been implemented in high-gain Op Amps. In this work, a scheme using double p-channel differential pairs is presented. A rail-to-rail signaling can be obtained at very low supply voltage. The circuit structure and the operation of the amplifier are introduced in section II. The post simulation results and comparisons are given in section III. Section IV concludes the summary. II. CIRCUIT STRUCTURE AND OPERATING PRINCIPLE
˩˖ˠ
́ ˀ˶ ˻ ˴ ́ ́ ˸ ˿ʳ̃ ˴ ˼̅ʳ̂ ́ ˗˸ ˴ ˷ ʳ̍̂ ́ ˸ ̃ ˀ˶ ˻ ˴ ́ ́ ˸ ˿ʳ̃ ˴ ˼̅ʳ̂ ́
Fig. 1 Complementary differential input pairs. The complementary differential pairs can achieve rail-to-rail signaling at the inputs. There is still a limitation at very low supply voltage. Fig. 1 shows the input dead zone of the complementary differential pairs. Fig. 2 shows the proposed double p-channel differential input pairs composed of a p-channel differential input pair (M1A, M2A) and level-shift p-channel differential input pair (M1~M4). The differential pairs are parts of a folded cascode amplifier. The p-channel differential input pairs are chosen because of an n-well process. The bulk
,
,6&$6
terminals of the devices in the differential input pairs are connected to their source terminals to eliminate the body effect. Connecting the output node of the amplifier to its negative input terminal, a unit-gain buffer is formed. Fig. 3 plots the waveforms of the unit-gain amplifiers. At 0.8V supply voltage, a single p-channel and a single level-shift p-channel differential input pair can only obtain 0-0.4V and 0.4-0.8V output swings, respectively. Combining the two differential input pairs, a rail-to-rail input commonmode range can be obtained as shown in Fig. 4.
ˠˆ ˠ˅˔
˩˼́ ʾ
˩˼̃ ˀ ˜˵ ́ ˄
˩˼̃ ʾ ˠ˄
ˠ˅
double p-channel
Fig.4 Simulated waveforms of a unit-gain buffer using double p-channel differential input pairs. Fig. 5 shows the complete circuit structure of the railto-rail amplifier using double p-channel differential input pairs. The input stage is composed of a p-channel differential pair (M1A, M2A), a level-shift p-channel differential pair (M1, M2, M3, M4), and bias current sources (M7, M7A, M12, M13). The input common-mode range VCM1 of the p-channel differential pair M1A and M2A is
ˠˇ ˠ˄˔
Vin
0ЉVCM1ЉVDD -VSD,M7A -VSG,M1A
˜˵ ́ ˅
The input common-mode range VCM2 of the levelshift p-channel differential pair M1~M4 is
Fig. 2 The double p-channel differential input pairs. If VGS3 and VGS4 are less than Vt,NMOS, the sourcefollower devices M3 and M4 are turned off. Consequently, Vip+ and Vip- are almost shorted to ground through the path of Ibn1 and Ibn2. Then, M1 and M2 are turned on. Even if M3 and M4 work in weak inversion, the small signal can still pass to Vip+ and Vip-. Since M1 and M2 operate at strong inversion in most of range, the small signal can be amplified without severe degradation. If VGS3 and VGS4 are larger than Vt,NMOS, the devices M3 and M4 are turned on. The input common-mode voltage VCM’ of Vip+ and Vip- are equal to VCM -Vt,NMOS where VCM is the common-mode voltage of the level-shift differential input pair. In other words, VCM is equal to VCM’+Vt,NMOS. Therefore, the differential input pair M1A and M2A can operate at a higher input common-mode voltage.
VGS,M3+VDS,M12 Љ VCM 2 Љ VDD -VSD,M7 - VSG,M1 +VGS,M3 (2) To achieve a rail-to-rail signaling at the inputs, the following conditions have to be satisfied. The W/L ratios of M1~M4 must be large enough to sustain VSG, M1Ѝ VGS,,M3ЍVtnЍ-Vtp
level-shift p-channel
(3)
Therefore, VGS,M3+VDS,M12ЉVCM 2Љ VDD -VSD,M7
(4)
The upper limit of VCM1 has to be larger than the lower limit of VCM2. VGS,M3+VDS,M12ЉVDD -VSD,M7A -VSG,M1A
(5)
Therefore, VDDЊVSG,M1A+VGS,M3+VSD,M7A+VDS,M12
p-channel
(1)
Vin
(6)
Combining Eq. (1) and Eq. (4) ,
Fig. 3 Simulated waveforms of unit-gain buffers of a single p-channel and a single level-shift p-channel differential pairs.
,
VCM=VCM1+VCM2
(7)
0ЉVCMЉ VDD -VSD, M7AЍ VDD
(8)
With proper sizing of M7 and M7A to reduce VSD,M7A, the input common-mode voltage can be from ground to VDD. Fig. 6 plots the overlapped operating input commonmode range of the two differential input pairs.
respectively. A rail-to-rail signaling of a unit-gain buffer can be obtained at 0.6V supply voltage. An open-loop rail-to-rail output swing can be derived at 0.8V supply voltage. The proposed amplifier has a better bandwidth and slew rate due to a simpler circuit structure.
ˢ̉˸ ̅˿˴ ̃ ̃ ˸ ˷ ˩˖ˠʳ˄ ˩˖ˠʳ˅
REFERENCES [1]
˩˖ˠ
Fig. 6 Overlapped operating range of the two differential input pairs
[2]
. III. POST SIMULATION RESULTS & COMPARISONS
[3]
Table I lists the device dimensions of the amplifier. Long channel devices are chosen for smaller device threshold voltages. The devices (M14~M17) in the cascode structure use longer channel length for the same reason. It is expected that at least one of the differential input pair keeps active during the transition. At 1V supply voltage, the p-channel pair is off when VCM is 0.6V. In this condition, M1A and M2A are off, M7A operates in linear region. The level-shift p-channel differential input pair (M1~M4, M12, M13), current summing circuit (M8, M9, M14~M17) and output stage (M10, M18) operate in saturation region. The 0.35um CMOS n-well process device modes are used for spice simulation. The typical threshold voltages of the n-channel and p-channel devices are 0.52V and –0.74V, respectively. We obtain VSG,M1A=0.4V, VGS,M3=0.562V, VSD, M7AЍ0V and VDS,M12 =0.096V from the simulation. The results satisfy Eq. (6). Fig.8 shows the layout of complete circuit. Table II summarizes the post simulation results and comparisons. The proposed amplifier has a simpler circuit structure than the others. A higher bandwidth is obtained. With similar power consumption, the proposed amplifier has better slew rates. The simulation results at lower supply voltages are listed in Table III. Fig. 7 plots the simulation waveforms of the amplifier as a unit-gain buffer at 0.6V supply voltage. It appears that the proposal structure can reach rail-to-rail signaling. The minimum supply voltage of an open-loop amplifier to obtain a rail-to-rail output swing is 0.8V. Under this condition, the amplifier has 49.1dB dc gain, 0.76MHz unit-gain bandwidth and 86o phase margin at 15pF output load.
[4]
[5]
[6]
J. Francisco Duque-Carrillo, Jose L. Ausin and Guido Torelli, “1-V rail-to-rail operational amplifiers in standard CMOS technology,” IEEE J. Solid-State Circuits, vol. 35, No. 1, pp.33-43, Jan. 2000. Yong Hui Tang and Randall L. Geiger, “A 0.6V ultra low voltage operational amplifier,” in Proc. 2002 ISCAS, vol. 3, pp.611-614 May 2002. J. Ranirez-Angulo S.C. Choi and G. Gonzalez-Altamirano, “Low-voltage circuit building blocks using multiple-input floating gate transistors,” IEEE Trans. Circuits Syst. I, vol. 42, No.11, pp.971-974, Nov. 1995. Benjanmin J. Blalock, Phillip E. Allen and Gabriel A. Rincon-Mora, “Designing 1-V Op Amps using standard digital CMOS technology” IEEE Trans. Circuits Syst. II, vol. 45, No.7, pp.760-780, Jul. 1998. Torsten Lehmann and Marco Cassia,“1-V power Supply CMOS cascode amplifier,” IEEE J. Solid-State Circuits, Vol. 36, No. 7, pp.1082-1086, Jul. 2001. J. Ranirez-Angulo, A. Torralba, R.G. Carvajal and J. Jombs, “Low-voltage CMOS amplifier with wide inputoutput swing based on a novel scheme” IEEE Trans. Circuits Syst. I, vol. 47, No.5, pp.772-774, May. 2000.
Vin Vout
Fig. 7 Simulation waveforms of an unit-gain buffer at 0.6V supply voltage.
IV. CONCLUSION A scheme using double p-channel differential input pairs is applied to a CMOS rail-to-rail amplifier for lowvoltage operation. The typical threshold voltages for a 0.35um CMOS n-well process are 0.52V and –0.74V,
,
Table I Device dimensions of the amplifier. MOS
W (um)
L (um)
M1,M2,M1A,M2A
200
2
M3,M4,M11,M12,M13
120
2
M6,M7,M7A,M8,M9
400
2
M14,M15,M16,M17
300
4
M5
100
2
M10
1600
2
M18
475
2
Rb=27.5Kȍ, Rm=2.25Kȍ,Cm=8pF,CL=15pF
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˩˼́ ˀ
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ˠ˄ˈ
˥˵ ˩˼̃ ˀ
˩˼̃ ʾ ˠ˄
ˠ˄˄
ˠ˄ˆ
ˠ˄ˉ
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˖̈ ̅̅˸ ́ ̇ʳ̆ ̈ ̀ ̀ ˼́ ˺ ʳ˶ ˼̅˶ ̈ ˼̇
˗̂ ̈ ˵ ˿˸ ʳ̃ ˀ˶ ˻ ˴ ́ ́ ˸ ˿ʳ˷ ˼˹˹˸ ̅˸ ́ ̇˼˴ ˿ʳ˼́ ̃ ̈ ̇ʳ̃ ˴ ˼̅̆
Fig. 5 Complete circuit of the double p-channel differential input pairs rail-to-rail amplifier. Table II Comparisons of low voltage Op Amps at 1V supply voltage. Feedfoward Feedback Ref [1] Ref [1]
Parameters Process
1.2um
Vtn,Vtp (V)
1.2um
0.75, -0.75 0.75, -0.75
Supply voltage (V) ICMR (V)
C.D.B. Ref [5]
This work
0.5um
0.35um
0.6,-0.6
0.52,-0.74
1
1
1
1
rail to rail
rail to rail
0.0~0.65
0.01~0.99
Power dissipation (uW)
410
208
-
288
dc gain (dB )
87
70.5
62-69
75.9
2
5.27
Unit-gian bandwidth (MHz)
1.9
P.M. Output swing (V)
61 -
Load, CL (pF)
15
15
-
15
CMRR (dB)
62
58
-
76.8
PSRR+ (dB)
-
-
-
69.9
PSRR- (dB)
o
2.1 73 -
o
o
57 0.35-0.75
o
84 0.05~0.94
-
-
-
69.2
Slew rate V/us (SR+)
0.8
0.9
0.5
3.2
Slew rate V/us (SR-)
1
1.7
-
3.9
-4~6
-2
-
-
Offset (mV)
Fig. 8 Layout of complete circuit.
Table III Performance of post simulation at different operating voltages. Parameters
˩̂ ̈ ̇
˖̀
ˠ˄˅
˕˼˴ ̆ ʳ˶ ˼̅˶ ̈ ˼̇
˥̀
ˠ˅
2P4M 0.35um CMOS technology Vtn=0.52V, Vtp=-0.74V, C L=15pF
Supply voltage (V)
1
0.9
0.8
0.7
0.6
ICMR (V)
0.01~0.99
0.01~0.89
0.01~0.79
0.01~0.69
0.01~0.58
Power dissipation (uW)
288
177
92
34
7
dc gain (dB)
75.9
72.2
49.1
32.9
23.4
Unit gian Bandwidth (MHz)
5.27
2.12
0.76
0.16
0.02
P.M. Output swing (V)
84o 0.05~0.943
91o 0.05~0.84
86o 0.06~0.69
87o 0.1~0.37
91o 0.1~0.2
CMRR (dB)
76.8
67.2
58.0
51.5
48.1
PSRR+ (dB)
69.9
83.6
50.5
41.4
23.9
PSRR- (dB)
69.2
66.9
62.0
59.4
64.8
Slew rate v/us (SR+)
3.2
2.1
1
0.3
0.05
Slew rate v/us (SR-) Noise (nV/√Hz) T.H.D. at 1KHz, 0.5 Vpp (%)
3.9 66 0.08
2.7 105 0.22
1.4 104 0.91
0.4 103 4
0.08 101 12
,
ˠ˄ˋ
˖˟
ˢ ̈ ̇̃ ̈ ̇ʳ̆ ̇˴ ˺ ˸
