A New Built-in Redundancy Analysis Algorithm
A New Built-in Redundancy Analysis Algorithm Based On Multiple Memory Blocks Jooyoung Kim, Keewon Cho, Woosung Lee, and Sungho Kang Dept. of Electrical and Electronic Engineering Yonsei University Seoul, Korea {kimjy9850, ckw1505, uoos}@soc.yonsei.ac.kr, and [email protected] Abstract—With the development of memory density, the probability of occurring faults in memory also increases. To overcome this problem, many built-in redundancy analysis (BIRA) algorithms have been proposed to repair the faults using redundancy cells in memory. Most of previous algorithms have focused on single memory block with local spare cell architecture. However, many memories in system consist of multiple local memory blocks with various spare cell architectures. Thus, the proposed algorithm is based on not only local spare cell but also various spare cell architectures. The experimental results show that repair rate, and hardware overhead of BIRA with various spare cell architectures in multiple memory blocks. The proposed algorithm is practical solution for multiple memory blocks which have global spare cell and common spare cell.
II.
The proposed algorithm uses many sub-analyzers to repair the target memory [4]. The number of sub-analyzers is calculated by the combination of the number of spare cells. As the number of spare cells increases, hardware overhead of the proposed algorithm also increases. Because, hardware overhead of the proposed algorithm is proportionate to the number of sub-analyzers. For example, the memory blocks in Fig. 1 have total five spare cells and these spare cells are total four kinds of spare cells. In this case, total 60 sub-analyzers are used to repair the faults in the target memory. The flow of the proposed algorithm likes as follow. First, all the solutions are detected by all the sub-analyzers when the fault addresses are searched in a row. If first fault address is entered in the all the sub-analyzers, each sub-analyzer calculate the fault addresses. When the fault address is stored in the subanalyzers, that address is checked to find out if newly fault address is same as the previous faults. If new additional fault is detected, that fault is entered in the sub-analyzer to repair the target memory. In contrast, new additional fault address is discarded when new fault address is same with the previous faults addresses. This flow is maintained until all the fault addresses are detected. When the total flow is finished, the solution which is successful to repair the target memory is selected by the proposed algorithm. When several solutions are successful to repair the target memory, one of the solutions is selected in order to achieve main purpose. Example in Fig. 1 have solution that global row spare in address 3, local row spare in address 5 in first memory, local row spare in address 6, and common column spare in address 3 and address 6 in second memory.
Keywords-built-in redundancy analysis (BIRA); global spare cell; common spare cell; multipleple memory block
I.
PROPOSED ARGORITHM
INTRODUCTION
With the growth of memory capacity and density, it is hard to achieve high yield of memory. Thus, it is important to repair the faults using redundancy cells to increase the yield of memory. Also, ideal BIRA algorithm must satisfy not only yield but also fast analysis speed and small hardware overhead. Because, total test cost is affected by analysis speed and BIRA hardware overhead. However, there is a trade-off among the repair rate, analysis speed and the hardware overhead. Since repair rate the most important factor to design BIRA, in this paper, a new BIRA with the optimal repair rate and fast analysis speed are proposed in order to reduce test cost. Most BIRA algorithms adopt a row spare cell and column spare cell architecture. However, memories in the system are composed of multiple local blocks with local spare cells, global spare cells and common spare cells [1-3]. Global spare cells and common spare cells are added in the various spare cell architectures. First, using global spare cells to repair the faults is useful when many faults occurred in the same word-line in the multiple memory blocks. Global spare cell scan be used multiple memory blocks to repair the same row address faults. However, global spare cells are not suitable for the different row line faults. Second, common spare cells are defined as the spare cells which can be used for repairing faults in the entire memory blocks. The advantage of common spare cells is that higher repair rate can be achieved compared to that of local spare cells.
Figure 1. Example of the proposed algorithm.
"(This work was supported by IDEC(IPC, EDA Tool, MPW)"
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ISOCC 2015
III.
EXPERIMENTAL RESULT
For the experiments, a 1024 X 1024 two memories are used and faults are injected using the Polya-Eggenberger distribution [5]. Total four architectures shown in Fig. 2 are used in experiment. First, each memory has two local row spare cells and two local spare cells. This architecture is standard to compare the other architecture. Next, the architecture includes four common column spare cells to repair the faults occurred in each side memory. The architectures have two global row spare cells to repair all the faults occurred in the same word-line in the multiple memory blocks. Experimental result shows repair rate, and hardware overhead of the each architecture.
Figure 3. Hardware overhead comparison.
Fig. 3 shows hardware overhead comparison of the architectures in experimental result. Hardware overhead of the proposed algorithm is proportionate to the number of the subanalyzers. Thus, the number of the sub-analyzers of the each architecture means hardware overhead of the each architecture. Hardware overhead of the second architecture is the highest because second architecture has total eight spare cells. The combination of these spare cells is 420 that is the biggest number in all the architectures. Comparison with other architectures, hardware overhead of the second architecture is the biggest. Third architecture has 90 sub-analyzers that is second rank in experimental result. The number of subanalyzers in first and fourth architecture is each 36 and 15.
Figure 4. Repair rate comparison.
IV.
CONCLUSION
As the memory density increases, it becomes more important to use an efficient BIRA for memory repair in terms of the high repair rate and low hardware overhead. The previous approaches are used for only single memory block architecture. In order to overcome this problem, a new BIRA algorithm which is based on global spare cells and common spare cells is proposed. The experimental results show that the performance of the proposed algorithm in terms of the repair rate and hardware overhead. Therefore, the proposed algorithm can be a practical solution for multiple memory blocks which have global spare cell and common spare cell.
Fig. 4 shows repair rate of the each architectures. Faults are distributed by Polya-Eggenberger and each experiment is executed 10,000 times. Repair rate of the second architecture that has four common column spare cells and two local spare cells each memory is always the highest regardless of the number of faults. Repair rate of fourth architecture also high than first and third architectures which have two local column spare cells. This means that common spare cells contribute high repair rate of the architecture. All repair rates of the architectures drastically decrease when the number of faults increases.
ACKNOWLEDGMENT
Experimental results of the proposed algorithm show that second architecture has the highest repair rate but also that has the highest hardware overhead. Thus, fourth architecture that has four common column spare cells and two global row spare cells has high repair rate and the lowest hardware overhead is suitable for the average condition in normal multiple memory blocks.
"(This work was supported by IDEC(IPC, EDA Tool, MPW)" REFERENCES [1]
[2]
[3]
[4]
[5]
Figure 2. Architectures in experimental result.
-2-
T.-W. Tseng, J.-F. Li, and D.-M. Chang, “A built-in redundancyanalysis scheme for RAMs with 2D redundancy using 1D local bitmap,” in Proc. Des., utom. Test Eur. (DATE), Munich, Germany, Mar. 2006, pp. 53–58. S.-K. Lu and et al. Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(2), February 2010. T.-W. Tseng and J.-F. Li, “A Low-Cost Built-In RedundancyAnalysis Scheme for Word-Oriented RAMs With 2-D Redundancy”, IEEE Trans. VLSI Systems, vol. 19, no. 11, pp. 1983-1995, 2011. T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in self-repair analyzer (CRESTA) for embedded DRAMs,” in Proc. Int. Test Conf. (ITC), 2000, pp. 567–574. C. Lee, W. Kang, D. Cho, and S. Kang, “A new fuse architecture and a new post-share redundancy scheme for yield enhancement in 3-Dstacked memories,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 5, pp.786-797, May 2014.
ISOCC 2015
II.
The proposed algorithm uses many sub-analyzers to repair the target memory [4]. The number of sub-analyzers is calculated by the combination of the number of spare cells. As the number of spare cells increases, hardware overhead of the proposed algorithm also increases. Because, hardware overhead of the proposed algorithm is proportionate to the number of sub-analyzers. For example, the memory blocks in Fig. 1 have total five spare cells and these spare cells are total four kinds of spare cells. In this case, total 60 sub-analyzers are used to repair the faults in the target memory. The flow of the proposed algorithm likes as follow. First, all the solutions are detected by all the sub-analyzers when the fault addresses are searched in a row. If first fault address is entered in the all the sub-analyzers, each sub-analyzer calculate the fault addresses. When the fault address is stored in the subanalyzers, that address is checked to find out if newly fault address is same as the previous faults. If new additional fault is detected, that fault is entered in the sub-analyzer to repair the target memory. In contrast, new additional fault address is discarded when new fault address is same with the previous faults addresses. This flow is maintained until all the fault addresses are detected. When the total flow is finished, the solution which is successful to repair the target memory is selected by the proposed algorithm. When several solutions are successful to repair the target memory, one of the solutions is selected in order to achieve main purpose. Example in Fig. 1 have solution that global row spare in address 3, local row spare in address 5 in first memory, local row spare in address 6, and common column spare in address 3 and address 6 in second memory.
Keywords-built-in redundancy analysis (BIRA); global spare cell; common spare cell; multipleple memory block
I.
PROPOSED ARGORITHM
INTRODUCTION
With the growth of memory capacity and density, it is hard to achieve high yield of memory. Thus, it is important to repair the faults using redundancy cells to increase the yield of memory. Also, ideal BIRA algorithm must satisfy not only yield but also fast analysis speed and small hardware overhead. Because, total test cost is affected by analysis speed and BIRA hardware overhead. However, there is a trade-off among the repair rate, analysis speed and the hardware overhead. Since repair rate the most important factor to design BIRA, in this paper, a new BIRA with the optimal repair rate and fast analysis speed are proposed in order to reduce test cost. Most BIRA algorithms adopt a row spare cell and column spare cell architecture. However, memories in the system are composed of multiple local blocks with local spare cells, global spare cells and common spare cells [1-3]. Global spare cells and common spare cells are added in the various spare cell architectures. First, using global spare cells to repair the faults is useful when many faults occurred in the same word-line in the multiple memory blocks. Global spare cell scan be used multiple memory blocks to repair the same row address faults. However, global spare cells are not suitable for the different row line faults. Second, common spare cells are defined as the spare cells which can be used for repairing faults in the entire memory blocks. The advantage of common spare cells is that higher repair rate can be achieved compared to that of local spare cells.
Figure 1. Example of the proposed algorithm.
"(This work was supported by IDEC(IPC, EDA Tool, MPW)"
-1-
ISOCC 2015
III.
EXPERIMENTAL RESULT
For the experiments, a 1024 X 1024 two memories are used and faults are injected using the Polya-Eggenberger distribution [5]. Total four architectures shown in Fig. 2 are used in experiment. First, each memory has two local row spare cells and two local spare cells. This architecture is standard to compare the other architecture. Next, the architecture includes four common column spare cells to repair the faults occurred in each side memory. The architectures have two global row spare cells to repair all the faults occurred in the same word-line in the multiple memory blocks. Experimental result shows repair rate, and hardware overhead of the each architecture.
Figure 3. Hardware overhead comparison.
Fig. 3 shows hardware overhead comparison of the architectures in experimental result. Hardware overhead of the proposed algorithm is proportionate to the number of the subanalyzers. Thus, the number of the sub-analyzers of the each architecture means hardware overhead of the each architecture. Hardware overhead of the second architecture is the highest because second architecture has total eight spare cells. The combination of these spare cells is 420 that is the biggest number in all the architectures. Comparison with other architectures, hardware overhead of the second architecture is the biggest. Third architecture has 90 sub-analyzers that is second rank in experimental result. The number of subanalyzers in first and fourth architecture is each 36 and 15.
Figure 4. Repair rate comparison.
IV.
CONCLUSION
As the memory density increases, it becomes more important to use an efficient BIRA for memory repair in terms of the high repair rate and low hardware overhead. The previous approaches are used for only single memory block architecture. In order to overcome this problem, a new BIRA algorithm which is based on global spare cells and common spare cells is proposed. The experimental results show that the performance of the proposed algorithm in terms of the repair rate and hardware overhead. Therefore, the proposed algorithm can be a practical solution for multiple memory blocks which have global spare cell and common spare cell.
Fig. 4 shows repair rate of the each architectures. Faults are distributed by Polya-Eggenberger and each experiment is executed 10,000 times. Repair rate of the second architecture that has four common column spare cells and two local spare cells each memory is always the highest regardless of the number of faults. Repair rate of fourth architecture also high than first and third architectures which have two local column spare cells. This means that common spare cells contribute high repair rate of the architecture. All repair rates of the architectures drastically decrease when the number of faults increases.
ACKNOWLEDGMENT
Experimental results of the proposed algorithm show that second architecture has the highest repair rate but also that has the highest hardware overhead. Thus, fourth architecture that has four common column spare cells and two global row spare cells has high repair rate and the lowest hardware overhead is suitable for the average condition in normal multiple memory blocks.
"(This work was supported by IDEC(IPC, EDA Tool, MPW)" REFERENCES [1]
[2]
[3]
[4]
[5]
Figure 2. Architectures in experimental result.
-2-
T.-W. Tseng, J.-F. Li, and D.-M. Chang, “A built-in redundancyanalysis scheme for RAMs with 2D redundancy using 1D local bitmap,” in Proc. Des., utom. Test Eur. (DATE), Munich, Germany, Mar. 2006, pp. 53–58. S.-K. Lu and et al. Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(2), February 2010. T.-W. Tseng and J.-F. Li, “A Low-Cost Built-In RedundancyAnalysis Scheme for Word-Oriented RAMs With 2-D Redundancy”, IEEE Trans. VLSI Systems, vol. 19, no. 11, pp. 1983-1995, 2011. T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in self-repair analyzer (CRESTA) for embedded DRAMs,” in Proc. Int. Test Conf. (ITC), 2000, pp. 567–574. C. Lee, W. Kang, D. Cho, and S. Kang, “A new fuse architecture and a new post-share redundancy scheme for yield enhancement in 3-Dstacked memories,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 5, pp.786-797, May 2014.
ISOCC 2015
