A Single Inductor Multiple Output Converter with ... - Semantic Scholar
A Single Inductor Multiple Output Converter with Adaptive Delta Current Mode Control Anmol Sharma
Y. Shanthi Pavan
Broadband Silicon Technology Center Texas Instruments (India) Pvt. Limited Bangalore, India
Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, India
Abstract—The authors propose a Single Inductor Multiple Output Converter (SIMO) with adaptive delta current mode control. A new time multiplexing scheme is also proposed for this type of control. With this control, the need of off-chip components for stability is eliminated. Use of single inductor for all outputs further eliminates additional magnetic components. This control makes the converter free from line and load regulation problems. It gives a good transient performance and reduces cross-regulation. To the best of authors' knowledge, no multiple output converter has been reported with adaptive delta current mode control. At the switching frequency of 500KHz, it achieves 80% efficiency for 1.5W of output power. The two outputs are regulated to 1.1V and 15V with an input supply of 3.3V. Excluding the inductor and capacitors, it is a fully integrated monolithic circuit, designed in a 3.3V, 0.4µm, CMOS process.
I.
INTRODUCTION
The present day electronic systems require multiple power supplies for different modules in different semiconductor processes. Each additional power supply costs additional components. For portable applications like cell-phones, PDAs etc., these additional components give rise to an undesirable increase in board-area, weight. For high volume products, cost of each additional component, gets multiplied by the volume of the product. Hence in recent years a lot of effort is put to integrate power supplies on single chip and to reduce external off-chip components for a given number of power supplies. Single Inductor Multiple Output converter is one such approach in which multiple output supplies are generated using a single inductor. Recently some SIMO converters are proposed with voltage mode control [1]. These converters require external off-chip components for stability and/or optimum line-load regulation performance. Most of these converters lack the advantages of current mode control. Another issue is cross-regulation in which transient on one supply output of SIMO affects the other output [2].
control provides infinite DC gain to the converter thereby eliminating DC line and load regulation problems. The transient response and cross-regulation performance is greatly enhanced due to current mode nature of control and usage of adaptive steps to control the inductor current. The rest of the paper is organized as follows. Section II discusses the power stage topology taken as an example to demonstrate this control. It also describes a new time multiplexing scheme. Section III discusses the control of converter in detail. Section IV covers the circuit implementation of the proposed concept. II.
A. The Power Stage A SIMO buck-boost converter is taken as an example to demonstrate the adaptive delta current mode control. This is possibly one of the most generic configuration in which one can generate multiple outputs, which can be independently lower or higher than the input supply. This converter is designed to generate two outputs 1.1V (with load 0.5A) and 15V (with load 65mA) from an input 3.3V. However the same control can be extended to more than two outputs and to any power stage topology. Figure 1 shows the power stage topology of the converter. The power switches are marked S1 to S4. The inductor can build up current through paths S1-S4 or S1-S3a. The path S1-S3a can be proved to be better for efficiency than S1-S4 because it reduces the r.m.s. value of current in inductor and hence the losses. However this path can’t be used if Vo1 (1.1V) is unloaded. The charging of output Vo1 takes place through S2-S3a and charging of Vo2 (14V) takes place through S1-S3b or S2-S3b. Again the path S1-S3b is more efficient and is always chosen for charging Vo2. S3
The proposed SIMO power converter reduces all the above stated problems. Here the converter operates with adaptive delta current mode control, a control to be tried first time on such power converters. With this control, the need of external components for stability is eliminated. The nature of
0-7803-9390-2/06/$20.00 ©2006 IEEE
POWER STAGE AND THE TIME MULTIPLEXING
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V IN
a
V o1 S1
S3 b
V o2 S2
S4
Figure 1. Power Stage Topology
ISCAS 2006
B. Time Multiplexing Scheme There are many time-multiplexing schemes discussed in literature [2]-[3]. All treat N-output SIMO as N separate subconverters. Hence there is a separate ON-time (time during which inductor builds-up current) and separate OFF-time (time during which inductor current reduces and energy is transferred to output) for each sub-converter. However in the proposed time multiplexing scheme, the whole converter is controlled with one cumulative system error (defined in next section) and not based on individual errors. This enables only one ON-time for all the outputs, which reduces the number of switching activities in a given period (T). E.g. for two outputs in a conventional time multiplexing scheme [2], there needs to be two ON- period and two OFF periods per cycle. There is one ON and one OFF period for the first subconverter and similarly for the other sub-converter.
There are two different variants of this new timemultiplexing scheme: "Ratio based" time-multiplexing (Fig. 2(a)) and "Need based" time multiplexing (Fig. 2(b)). In both the schemes there is only one ON period per cycle. In "Ratio based" scheme, the inductor builds up current in ON period (ton) based on the target set by current mode loop. The ‘Iref’ line shows the target of current set for the converter to be achieved in ton period. There are however two OFF periods (toff1, toff2). During toff1, the converter charges Vo1 output and during toff2, it charges Vo2. The two periods are decided based upon error present in both the outputs. A logical way to do this would be to charge the output, which is more erroneous for longer time, and the other output for a shorter time. Hence in this scheme toff1 and toff2 are calculated as fractions e1/(e1+e2) and e2/(e1+e2) respectively of (T-ton). e1 and e2 are the normalized errors. By normalized error we mean error in normalized outputs. E.g. A 1V error in 14V output is equivalent (in terms of percentage) to 0.1V error in 1.4V S1 & S3a S2 & S3a
(a)
ton
toff1
toff2
S1 & S3b
Inductor Current a
b
Iref c t1
d
Ip
T
t
S1 & S3a ton
(b)
toff1
ton
toff2
S2 & S3a T S1 & S3b
Figure 2. Proposed Time Multiplexing Schemes. (a) Ratio-Based timemultiplexing. (b) Need-Based time-multiplexing.
output. Hence the outputs are normalized to 1V to calculate the errors e1 and e2. It can be seen that it has 3 transitions of switches happening in one period (T) as compared to 4 of conventional schemes. In "Need based" scheme there is only one OFF period per cycle (toff1 or toff2) i.e. only one of the outputs is charged in a given cycle (T). Here the output whose normalized error is more than other output is charged in any given period. This scheme ensures that the percentage error in both outputs remains to minimal and no output has more percentage error w.r.t. other at any given point of time. As can be seen that this scheme further reduces number of switching transitions in a given cycle to half of the conventional time-multiplexing schemes. This reduces the switching losses and simplifies the control of power switches. In Fig. 2(b), toff1 and toff2 come in consecutive cycles. However it may not be always the case. E.g. If any of output is un-loaded then the charging period (toff1 or toff2) for that output is going to be skipped for many cycles. Hence there is a pulse skipping based upon the load on the outputs. Therefore this time multiplexing leads to PFM (PulseFrequency-Modulation) operation with variable pulse width. It can be seen that in these time multiplexing schemes the converter doesn't spend any time on the output which doesn't need attention, unlike conventional schemes where there is a fixed time allocated to each sub-converter. Converter discussed in this paper adopts "Need-based" time multiplexing scheme because of simplicity of its circuit implementation. The scheme of Fig. 2(a) requires a calculation of error fraction, which is not very easy to be implemented in circuit. III.
ADAPTIVE DELTA CONTROL OF CONVERTER
A similar scheme [4] is used in communication systems to track the signal and for Analog to Digital conversion. It is called “Adaptive Delta Modulation”. Here this concept is extended to power converters to regulate output voltages. Before explaining the control let us define "cumulative system error", etot. It is the total error in the system. A simple way to find total error is to add up all the errors in all the supply outputs. But this error doesn't give a true representation of system error because of following reasons: (1) Since the output voltage levels are different hence the errors should not be summed up directly. Instead of this, the normalized errors (discussed before) should be added up. (2) It may happen that a negative error in one supply output (i.e. output overshoots the expected output) masks the positive error (i.e. output is lower than expected) of other supply. To prevent this, both the errors should be rectified below zero i.e. only positive errors should be added and a negative error should be given a value equal to zero error. Now let us explain the control. We shall take an example in which there is a step load given at both the outputs. With this load step, the total output power required from converter increases. So the inductor current (IL) has to be increased from Iref1 to Iref2 as shown in Fig. 3(a). First the output voltages start going down with step-load. This error is detected by the current mode loop and a new target of inductor current (Iref1a) is set for the coming cycle. Now the
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loop forces the inductor to get to this new value of Iref. Once this value is achieved, the inductor gets in contact with the output, which is most erroneous (as was discussed in "Needbased" scheme). This is shown by decrease in inductor current in Fig. 3(a). Then in the next cycle again, the "Iref" is re-evaluated which the loop tries to achieve in subsequent cycle. As the etot keeps reducing the step change in Iref also keeps reducing as shown in Fig. 3(a). The loop keeps doing it until both the outputs achieve zero error. Hence we can see that the final value of "Iref" i.e. Iref2 is not known in the beginning but eventually the converter settles to this new value. Fig. 3(b) describes how this value of "Iref" is calculated. If there is no error in any of the outputs, then the converter tries to reduce the inductor current to bring the converter in low energy and hence more efficient state. This is shown by etot ≤ 0 state. However if there is any error, then it checks if the error is decreasing with time. If the error decreases with time then there is no need to change inductor current because with this current, the error will eventually come to 0. "etoti" stands for error in ith cycle. If error is not decreasing with time, then converter increments Iref by a step n × Istep. The Iref target is increased blindly if "etot" is more than a threshold error "ethrsh". Doing this improves the transient response of the converter. The value of "n" is directly proportional to the value of "etot" i.e. for large values of "etot”, value of "n" is large and for small values of "etot", value of "n" is small. Hence it can be seen that there is an adaptive step change in the value of "Iref".
I
Iref1d
Iref1e
Iref2
Iref1c Iref1b
(a) Iref1a
IL
etoti
(b)
Next Cycle (i+1)
2T
3T
That is the reason why it is named as Adaptive Control. When converter reaches near zero cumulative error, then the step size is extremely small, which causes no significant ripple in the outputs. Therefore the converter always tries to reach to that value of inductor current, which is just sufficient enough to keep the error in both outputs as zero. With this arrangement, the converter attains final value of "Iref2" very fast because of initial large increment steps. It leads to good transient performance. A. Need for Adaptive Steps : The converter is modeled in MATLAB SIMULINK to check for this new control. This modeling is based on state space equations of the components (inductor, capacitor etc.). The adaptive control is seen to have better transient response. It also prevents the converter to build large signal oscillations. Fig. 4(a) shows the MATLAB inductor current with fixed step, which exhibits oscillations. Fig. 4(b) shows the inductor current with Adaptive steps, which exhibits no large signal oscillations. With this control we don't need any slope compensation as is required for conventional current mode control [5]. B.
Line-Load Regulation and Cross-Regulation : This converter is free from DC line and load regulation problems. If we carefully examine the control strategy, it is easy to see that the converter loop has some form of an integrator of the type n × I L .dt , where "n" is a function of
Iref1 T
Figure 4. MATLAB plots of Inductor current. (a) With fixed steps. (b) With Adaptive Step.
4T
etoti≤0? Yes Irefi=Iref(i-1)-m* Istep
5T
No
6T
7T
etoti≥etot(i−1) or
t
∫
No
etoti≥ethrsh? Yes Irefi=Iref(i-1)+n*Istep
Irefi=Iref(i-1)
Figure 3. (a) Adaptive delta control of inductor current. (b) Iref generation algorithm.
"etot" as was explained earlier in this section. This 1/s transfer function in the control loop gives infinite DC gain, which implies no DC line and load regulation because the loop gain suppresses any change in output voltage due to line, load or any other factor. In conventional converters, usually an intentional integrator is put in the control loop for this, which requires external components. The proposed scheme however doesn't require any external components for this purpose. The converter also have lesser cross-regulation than voltage mode schemes [2]. This is because in voltage mode schemes, duty cycle of each sub-converter is controlled variable and the quantity which is responsible for crossregulation is inductor current. This current mode scheme directly controls the inductor current, leading to less
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influence of one supply on inductor current and hence on the other output. C. Theoretical Calculations Converter’s time-domain behavior can be approximated to one cycle of Fig. 2(a), and the quantities ton, toff1, toff2 can be considered averaged over many cycles. We need ton, t1 and Ip to characterize the entire converter, as shown in Fig. 2(a). Hence we need three equations. First equation is got by simple equilibrium volt-second product rule: Total rise in Inductor current (during ton)= Total fall in Inductor current (during toff1 and toff2), which yields:
(a)
(b)
(VIN −Vo1) ⋅ ton / L = [Vo1 ⋅ (t1 − ton) / L] + (Vo2 −VIN ) ⋅ (T − t1) / L .
Figure 6. Step-load response of converter. (a) Vo2 . (b) Vo1.
The remaining two equations are got by calculating average inductor current during toff1, toff2 and equating them to load currents at Vo1, Vo2 respectively. This design uses L=10µH and the Vo1, Vo2 decoupling capacitors as 100µF and 33µF respectively. IV.
CIRCUIT IMPLEMENTATION AND RESULTS
Figure 5 shows the circuit implementation of the control scheme. A complete implementation can be found in [6]. "Error-Gen" block generates the cumulative system error. Its implementation is a simple adder-subtractor with rectifier to rectify errors below zero. The cumulative error goes to an Analog to Digital converter (3 bit flash A to D in the present example), which generates digital error for the digital controller. Digital controller is a simple up-down counter (6 bit in this case). If the Iref value is to be incremented then it counts up. By how much steps to count up or down is determined by value of etot (adaptive control). That is the reason why a digital etot is fed into this block. The controller uses this error to calculate "n". The value of Iref generated this way is in digital form and a Digital to Analog converter is required to convert this digital current to analog current. This current is then compared with sensed inductor current in the ton period, as in done in any current mode control. When inductor current equals Iref, then ton period is terminated.
Digital Controller
6 bit 4 bit Switch Control
3 bit
A to D Converter
[1] [2]
Switch Driver
S1 S2 S4
Power Stage
S3a,b
incr_Iref
V.
Direction Gen.
etot
CONCLUSIONS
In this paper a new technique to control SIMO converters is presented. This technique is shown to have several advantages over conventional schemes like good transient performance, lesser switching losses and cross-regulation, no need of external components for stability and elimination of dc line-load regulation. A dual output buck-boost converter based on this control was designed and simulated in 0.4 µm CMOS process, which validates this concept. In addition the design can be extended to any other single-output or multiple-output power-converter topology. REFERENCES
Sensed Inductor Current
D to A Converter
Current Comp.
The block "Direction-Gen" compares the present sample of etot to the previous sample and asserts a signal incr_Iref (if present error is more than previous) to increment the count of controller as per the Iref generation algorithm of Fig. 3(b). This block can be easily implemented in Analog domain as a switched capacitor circuit in which previous sample of etot is stored on a capacitor and present sample is compared with it. The digital controller provides control signals to the powerswitch driver, which drives power transistors in the power stage in non-overlapping fashion. The power stage is already described in Fig. 1. The circuit implemented in this way is simulated using SPICE simulator. Fig. 6 shows the results of this simulation. A small ripple can be seen in outputs (1.1V and 15V) due to limited resolution of Iref D to A Converter.
Vo1 Vo2
[3]
Vref
[4]
Error Gen.
[5] [6]
Figure 5. Implementation of the Converter
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D. Ma and Wing-Hung Ki, “Single-Inductor Multiple-Output Switching Converters,” IEEE PESC, vol 1, Jun 2001, pp. 226-231. D. Ma, Wing-Hung Ki, Chi-Ying Tsui, “A pseudo-CCM/DCM SIMO Switching Converter With Freewheel Switching,” IEEE J. Solid-State Circuits, vol 38, June 2003, pp. 1007-1014. T. Li, "Single inductor multiple output boost regulator," U.S. Patent 6 075 295, June 13, 2000. Simon Haykin, “Communication Systems,” 4th Edition., John Wiley & Sons Inc., 2001. R.W. Erickson, D. Maksimovic, “Fundamentals of power electronics,” 2nd Edition, Kluwer Academic Publishers. Anmol Sharma, “Design of a Single Inductor Dual Output BuckBoost Converter with Current Mode control,” M.S. Thesis, Indian Institute of Technology Madras, June 2005.
Y. Shanthi Pavan
Broadband Silicon Technology Center Texas Instruments (India) Pvt. Limited Bangalore, India
Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, India
Abstract—The authors propose a Single Inductor Multiple Output Converter (SIMO) with adaptive delta current mode control. A new time multiplexing scheme is also proposed for this type of control. With this control, the need of off-chip components for stability is eliminated. Use of single inductor for all outputs further eliminates additional magnetic components. This control makes the converter free from line and load regulation problems. It gives a good transient performance and reduces cross-regulation. To the best of authors' knowledge, no multiple output converter has been reported with adaptive delta current mode control. At the switching frequency of 500KHz, it achieves 80% efficiency for 1.5W of output power. The two outputs are regulated to 1.1V and 15V with an input supply of 3.3V. Excluding the inductor and capacitors, it is a fully integrated monolithic circuit, designed in a 3.3V, 0.4µm, CMOS process.
I.
INTRODUCTION
The present day electronic systems require multiple power supplies for different modules in different semiconductor processes. Each additional power supply costs additional components. For portable applications like cell-phones, PDAs etc., these additional components give rise to an undesirable increase in board-area, weight. For high volume products, cost of each additional component, gets multiplied by the volume of the product. Hence in recent years a lot of effort is put to integrate power supplies on single chip and to reduce external off-chip components for a given number of power supplies. Single Inductor Multiple Output converter is one such approach in which multiple output supplies are generated using a single inductor. Recently some SIMO converters are proposed with voltage mode control [1]. These converters require external off-chip components for stability and/or optimum line-load regulation performance. Most of these converters lack the advantages of current mode control. Another issue is cross-regulation in which transient on one supply output of SIMO affects the other output [2].
control provides infinite DC gain to the converter thereby eliminating DC line and load regulation problems. The transient response and cross-regulation performance is greatly enhanced due to current mode nature of control and usage of adaptive steps to control the inductor current. The rest of the paper is organized as follows. Section II discusses the power stage topology taken as an example to demonstrate this control. It also describes a new time multiplexing scheme. Section III discusses the control of converter in detail. Section IV covers the circuit implementation of the proposed concept. II.
A. The Power Stage A SIMO buck-boost converter is taken as an example to demonstrate the adaptive delta current mode control. This is possibly one of the most generic configuration in which one can generate multiple outputs, which can be independently lower or higher than the input supply. This converter is designed to generate two outputs 1.1V (with load 0.5A) and 15V (with load 65mA) from an input 3.3V. However the same control can be extended to more than two outputs and to any power stage topology. Figure 1 shows the power stage topology of the converter. The power switches are marked S1 to S4. The inductor can build up current through paths S1-S4 or S1-S3a. The path S1-S3a can be proved to be better for efficiency than S1-S4 because it reduces the r.m.s. value of current in inductor and hence the losses. However this path can’t be used if Vo1 (1.1V) is unloaded. The charging of output Vo1 takes place through S2-S3a and charging of Vo2 (14V) takes place through S1-S3b or S2-S3b. Again the path S1-S3b is more efficient and is always chosen for charging Vo2. S3
The proposed SIMO power converter reduces all the above stated problems. Here the converter operates with adaptive delta current mode control, a control to be tried first time on such power converters. With this control, the need of external components for stability is eliminated. The nature of
0-7803-9390-2/06/$20.00 ©2006 IEEE
POWER STAGE AND THE TIME MULTIPLEXING
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V IN
a
V o1 S1
S3 b
V o2 S2
S4
Figure 1. Power Stage Topology
ISCAS 2006
B. Time Multiplexing Scheme There are many time-multiplexing schemes discussed in literature [2]-[3]. All treat N-output SIMO as N separate subconverters. Hence there is a separate ON-time (time during which inductor builds-up current) and separate OFF-time (time during which inductor current reduces and energy is transferred to output) for each sub-converter. However in the proposed time multiplexing scheme, the whole converter is controlled with one cumulative system error (defined in next section) and not based on individual errors. This enables only one ON-time for all the outputs, which reduces the number of switching activities in a given period (T). E.g. for two outputs in a conventional time multiplexing scheme [2], there needs to be two ON- period and two OFF periods per cycle. There is one ON and one OFF period for the first subconverter and similarly for the other sub-converter.
There are two different variants of this new timemultiplexing scheme: "Ratio based" time-multiplexing (Fig. 2(a)) and "Need based" time multiplexing (Fig. 2(b)). In both the schemes there is only one ON period per cycle. In "Ratio based" scheme, the inductor builds up current in ON period (ton) based on the target set by current mode loop. The ‘Iref’ line shows the target of current set for the converter to be achieved in ton period. There are however two OFF periods (toff1, toff2). During toff1, the converter charges Vo1 output and during toff2, it charges Vo2. The two periods are decided based upon error present in both the outputs. A logical way to do this would be to charge the output, which is more erroneous for longer time, and the other output for a shorter time. Hence in this scheme toff1 and toff2 are calculated as fractions e1/(e1+e2) and e2/(e1+e2) respectively of (T-ton). e1 and e2 are the normalized errors. By normalized error we mean error in normalized outputs. E.g. A 1V error in 14V output is equivalent (in terms of percentage) to 0.1V error in 1.4V S1 & S3a S2 & S3a
(a)
ton
toff1
toff2
S1 & S3b
Inductor Current a
b
Iref c t1
d
Ip
T
t
S1 & S3a ton
(b)
toff1
ton
toff2
S2 & S3a T S1 & S3b
Figure 2. Proposed Time Multiplexing Schemes. (a) Ratio-Based timemultiplexing. (b) Need-Based time-multiplexing.
output. Hence the outputs are normalized to 1V to calculate the errors e1 and e2. It can be seen that it has 3 transitions of switches happening in one period (T) as compared to 4 of conventional schemes. In "Need based" scheme there is only one OFF period per cycle (toff1 or toff2) i.e. only one of the outputs is charged in a given cycle (T). Here the output whose normalized error is more than other output is charged in any given period. This scheme ensures that the percentage error in both outputs remains to minimal and no output has more percentage error w.r.t. other at any given point of time. As can be seen that this scheme further reduces number of switching transitions in a given cycle to half of the conventional time-multiplexing schemes. This reduces the switching losses and simplifies the control of power switches. In Fig. 2(b), toff1 and toff2 come in consecutive cycles. However it may not be always the case. E.g. If any of output is un-loaded then the charging period (toff1 or toff2) for that output is going to be skipped for many cycles. Hence there is a pulse skipping based upon the load on the outputs. Therefore this time multiplexing leads to PFM (PulseFrequency-Modulation) operation with variable pulse width. It can be seen that in these time multiplexing schemes the converter doesn't spend any time on the output which doesn't need attention, unlike conventional schemes where there is a fixed time allocated to each sub-converter. Converter discussed in this paper adopts "Need-based" time multiplexing scheme because of simplicity of its circuit implementation. The scheme of Fig. 2(a) requires a calculation of error fraction, which is not very easy to be implemented in circuit. III.
ADAPTIVE DELTA CONTROL OF CONVERTER
A similar scheme [4] is used in communication systems to track the signal and for Analog to Digital conversion. It is called “Adaptive Delta Modulation”. Here this concept is extended to power converters to regulate output voltages. Before explaining the control let us define "cumulative system error", etot. It is the total error in the system. A simple way to find total error is to add up all the errors in all the supply outputs. But this error doesn't give a true representation of system error because of following reasons: (1) Since the output voltage levels are different hence the errors should not be summed up directly. Instead of this, the normalized errors (discussed before) should be added up. (2) It may happen that a negative error in one supply output (i.e. output overshoots the expected output) masks the positive error (i.e. output is lower than expected) of other supply. To prevent this, both the errors should be rectified below zero i.e. only positive errors should be added and a negative error should be given a value equal to zero error. Now let us explain the control. We shall take an example in which there is a step load given at both the outputs. With this load step, the total output power required from converter increases. So the inductor current (IL) has to be increased from Iref1 to Iref2 as shown in Fig. 3(a). First the output voltages start going down with step-load. This error is detected by the current mode loop and a new target of inductor current (Iref1a) is set for the coming cycle. Now the
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loop forces the inductor to get to this new value of Iref. Once this value is achieved, the inductor gets in contact with the output, which is most erroneous (as was discussed in "Needbased" scheme). This is shown by decrease in inductor current in Fig. 3(a). Then in the next cycle again, the "Iref" is re-evaluated which the loop tries to achieve in subsequent cycle. As the etot keeps reducing the step change in Iref also keeps reducing as shown in Fig. 3(a). The loop keeps doing it until both the outputs achieve zero error. Hence we can see that the final value of "Iref" i.e. Iref2 is not known in the beginning but eventually the converter settles to this new value. Fig. 3(b) describes how this value of "Iref" is calculated. If there is no error in any of the outputs, then the converter tries to reduce the inductor current to bring the converter in low energy and hence more efficient state. This is shown by etot ≤ 0 state. However if there is any error, then it checks if the error is decreasing with time. If the error decreases with time then there is no need to change inductor current because with this current, the error will eventually come to 0. "etoti" stands for error in ith cycle. If error is not decreasing with time, then converter increments Iref by a step n × Istep. The Iref target is increased blindly if "etot" is more than a threshold error "ethrsh". Doing this improves the transient response of the converter. The value of "n" is directly proportional to the value of "etot" i.e. for large values of "etot”, value of "n" is large and for small values of "etot", value of "n" is small. Hence it can be seen that there is an adaptive step change in the value of "Iref".
I
Iref1d
Iref1e
Iref2
Iref1c Iref1b
(a) Iref1a
IL
etoti
(b)
Next Cycle (i+1)
2T
3T
That is the reason why it is named as Adaptive Control. When converter reaches near zero cumulative error, then the step size is extremely small, which causes no significant ripple in the outputs. Therefore the converter always tries to reach to that value of inductor current, which is just sufficient enough to keep the error in both outputs as zero. With this arrangement, the converter attains final value of "Iref2" very fast because of initial large increment steps. It leads to good transient performance. A. Need for Adaptive Steps : The converter is modeled in MATLAB SIMULINK to check for this new control. This modeling is based on state space equations of the components (inductor, capacitor etc.). The adaptive control is seen to have better transient response. It also prevents the converter to build large signal oscillations. Fig. 4(a) shows the MATLAB inductor current with fixed step, which exhibits oscillations. Fig. 4(b) shows the inductor current with Adaptive steps, which exhibits no large signal oscillations. With this control we don't need any slope compensation as is required for conventional current mode control [5]. B.
Line-Load Regulation and Cross-Regulation : This converter is free from DC line and load regulation problems. If we carefully examine the control strategy, it is easy to see that the converter loop has some form of an integrator of the type n × I L .dt , where "n" is a function of
Iref1 T
Figure 4. MATLAB plots of Inductor current. (a) With fixed steps. (b) With Adaptive Step.
4T
etoti≤0? Yes Irefi=Iref(i-1)-m* Istep
5T
No
6T
7T
etoti≥etot(i−1) or
t
∫
No
etoti≥ethrsh? Yes Irefi=Iref(i-1)+n*Istep
Irefi=Iref(i-1)
Figure 3. (a) Adaptive delta control of inductor current. (b) Iref generation algorithm.
"etot" as was explained earlier in this section. This 1/s transfer function in the control loop gives infinite DC gain, which implies no DC line and load regulation because the loop gain suppresses any change in output voltage due to line, load or any other factor. In conventional converters, usually an intentional integrator is put in the control loop for this, which requires external components. The proposed scheme however doesn't require any external components for this purpose. The converter also have lesser cross-regulation than voltage mode schemes [2]. This is because in voltage mode schemes, duty cycle of each sub-converter is controlled variable and the quantity which is responsible for crossregulation is inductor current. This current mode scheme directly controls the inductor current, leading to less
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influence of one supply on inductor current and hence on the other output. C. Theoretical Calculations Converter’s time-domain behavior can be approximated to one cycle of Fig. 2(a), and the quantities ton, toff1, toff2 can be considered averaged over many cycles. We need ton, t1 and Ip to characterize the entire converter, as shown in Fig. 2(a). Hence we need three equations. First equation is got by simple equilibrium volt-second product rule: Total rise in Inductor current (during ton)= Total fall in Inductor current (during toff1 and toff2), which yields:
(a)
(b)
(VIN −Vo1) ⋅ ton / L = [Vo1 ⋅ (t1 − ton) / L] + (Vo2 −VIN ) ⋅ (T − t1) / L .
Figure 6. Step-load response of converter. (a) Vo2 . (b) Vo1.
The remaining two equations are got by calculating average inductor current during toff1, toff2 and equating them to load currents at Vo1, Vo2 respectively. This design uses L=10µH and the Vo1, Vo2 decoupling capacitors as 100µF and 33µF respectively. IV.
CIRCUIT IMPLEMENTATION AND RESULTS
Figure 5 shows the circuit implementation of the control scheme. A complete implementation can be found in [6]. "Error-Gen" block generates the cumulative system error. Its implementation is a simple adder-subtractor with rectifier to rectify errors below zero. The cumulative error goes to an Analog to Digital converter (3 bit flash A to D in the present example), which generates digital error for the digital controller. Digital controller is a simple up-down counter (6 bit in this case). If the Iref value is to be incremented then it counts up. By how much steps to count up or down is determined by value of etot (adaptive control). That is the reason why a digital etot is fed into this block. The controller uses this error to calculate "n". The value of Iref generated this way is in digital form and a Digital to Analog converter is required to convert this digital current to analog current. This current is then compared with sensed inductor current in the ton period, as in done in any current mode control. When inductor current equals Iref, then ton period is terminated.
Digital Controller
6 bit 4 bit Switch Control
3 bit
A to D Converter
[1] [2]
Switch Driver
S1 S2 S4
Power Stage
S3a,b
incr_Iref
V.
Direction Gen.
etot
CONCLUSIONS
In this paper a new technique to control SIMO converters is presented. This technique is shown to have several advantages over conventional schemes like good transient performance, lesser switching losses and cross-regulation, no need of external components for stability and elimination of dc line-load regulation. A dual output buck-boost converter based on this control was designed and simulated in 0.4 µm CMOS process, which validates this concept. In addition the design can be extended to any other single-output or multiple-output power-converter topology. REFERENCES
Sensed Inductor Current
D to A Converter
Current Comp.
The block "Direction-Gen" compares the present sample of etot to the previous sample and asserts a signal incr_Iref (if present error is more than previous) to increment the count of controller as per the Iref generation algorithm of Fig. 3(b). This block can be easily implemented in Analog domain as a switched capacitor circuit in which previous sample of etot is stored on a capacitor and present sample is compared with it. The digital controller provides control signals to the powerswitch driver, which drives power transistors in the power stage in non-overlapping fashion. The power stage is already described in Fig. 1. The circuit implemented in this way is simulated using SPICE simulator. Fig. 6 shows the results of this simulation. A small ripple can be seen in outputs (1.1V and 15V) due to limited resolution of Iref D to A Converter.
Vo1 Vo2
[3]
Vref
[4]
Error Gen.
[5] [6]
Figure 5. Implementation of the Converter
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D. Ma and Wing-Hung Ki, “Single-Inductor Multiple-Output Switching Converters,” IEEE PESC, vol 1, Jun 2001, pp. 226-231. D. Ma, Wing-Hung Ki, Chi-Ying Tsui, “A pseudo-CCM/DCM SIMO Switching Converter With Freewheel Switching,” IEEE J. Solid-State Circuits, vol 38, June 2003, pp. 1007-1014. T. Li, "Single inductor multiple output boost regulator," U.S. Patent 6 075 295, June 13, 2000. Simon Haykin, “Communication Systems,” 4th Edition., John Wiley & Sons Inc., 2001. R.W. Erickson, D. Maksimovic, “Fundamentals of power electronics,” 2nd Edition, Kluwer Academic Publishers. Anmol Sharma, “Design of a Single Inductor Dual Output BuckBoost Converter with Current Mode control,” M.S. Thesis, Indian Institute of Technology Madras, June 2005.
