Adaptive Response Surface Modeling-based ... - Semantic Scholar
Adaptive Response Surface Modeling-based Method for Analog Circuit Sizing! Donghoon Han and Abhijit Chatterjee Georgia Institute of Technology, Atlanta, GA 30332
{dhhan, chat}@ece.gatech.edu
ABTRACT In this paper we propose a novel simulation-based analog circuit sizing method which is capable of significantly reducing the computational cost via adaptive response surface modeling. The proposed algorithm is based on the selective evaluation of a response surface model coupled with numerical circuit simulation and the adaptive update of the model for accuracy. An effective sampling scheme for modeling using two related criteria that are crucial for speedup and convergence towards an optimal solution is presented. One provides sufficient samples for model accuracy and convergence, whereas the other prevents oversampling of the design space after the model is saturated. Multivariate adaptive regression splines (MARS) are used to construct a model of the selected cost function. Results for several test functions and two test cases are discussed. I. INTRODUCTION As the demands of system-on-chip integrated circuits increase, the design of analog circuits has become a bottleneck in the design phase due to the lack of mature CAD synthesis tools as compared to digital circuits and systems. In this paper, we focus on an automatic transistor level analog circuit sizing method that can be integrated into a complete analog circuit synthesis framework. Distinct research directions in analog circuit sizing can be found in literature [1] and are as follows: 1) equation-based approaches in which a predefined equation set, that defines functions mapping between design parameters and specifications, is utilized in the optimization process, and 2) simulation-based methods in which the optimization process is driven by measurement of circuit performance using SPICE simulation. Each of these methods has its own application-dependent advantages and disadvantages. The simulation-based approach can be applied to any circuit for which a SPICE netlist is available, but is expensive from the viewpoint of simulation cost. Therefore, researchers in this area have focused on the reduction of simulation cost based on ideas such as task parallelization and the design of algorithms This work has been partially supported by DARPA NEOCAD program, NSF ITR under the contract number CCR-032555, and MACRO 2003-DT-660.
with a high rate of convergence. In this paper, we propose a simulation-based circuit sizing method using an adaptive cost model. The goal is to perform a minimum number of SPICE simulations to obtain an optimum set of design parameters for the given target specifications. Previously, model based approaches were proposed for the design of magnetic devices [2] and RF circuits [3]. The method for design of magnetic devices is based on simulated annealing and needs a number of function evaluations that increases exponentially with the number of input parameters. Therefore, the method is applicable to design problems with small numbers of input parameters. The approach for RF circuits is based on the use of genetic algorithms with embedded SPICE simulations and the use of design knowledge. In [4] equation-based behavioral models suitable for optimization via geometric programming methods are proposed and results are shown for some commonly used building blocks. We propose a different approach that can be imported into a typical simulated annealing based optimization framework. The basic idea is to use an accurate cost model to evaluate cost values within a limited region of the design space. This cost model can be evaluated rapidly without running any circuit simulations. Whenever the new candidate is generated at each iteration, an adaptive sampling scheme is used to update the model (which is valid for the limited region for the current candidate) via a minimum number of SPICE simulations in such a way that model inaccuracy is kept within specific bounds. The adaptive sampling approach is determined by the strategy of simulated annealing and the statistics of the differences between the actual and estimated target specification values (estimated from the model). The key features of the proposed method are as follows: 1) Significant reduction of the computational cost due to fewer SPICE simulations and 2) Method is applicable to any circuit for which SPICE netlist is available and results in designs with full SPICE accuracy. The paper is organized as follows: Section 2 presents the basic concepts. In Section 3, we describe the adaptive sampling scheme and cost model. Then, we present numerical results for different test functions and circuit sizing results for two practical cases in Sections 4 and 5. Finally, we provide concluding remarks.
II. PROPOSED APPROACH A. Circuit Sizing Circuit sizing is an optimization process to find a design parameter set x that makes a circuit under design satisfy target specifications. In general, design parameter set x includes transistor dimensions, passive component values, and bias currents in transistor-level circuit sizing. Without loss of generality this process can be converted into a single optimization problem and be stated as find x* ∈ D such that Ψ ( f ( x* )) ≤ Ψ ( f ( x)) , x ∈ D,
where D ⊂ \ n denotes the space of input parameter set, f(·) is a set of objective functions derived from performance specifications, and Ψ(·) is a cost function that converts multiple objective function f(·) into a single one. Typical structure of circuit sizing is shown in Figure 1 and is mainly composed of optimizer and evaluator. Depending on the type of evaluator, circuit sizing method can be divided into simulation-based approach and equation-based approach. To get an optimum solution, global optimizer such as simulated annealing, genetic algorithm, etc. is in widespread as optimizer.
quality of the final solution obtained is not affected by the use of the cost model. The basic structure of the proposed algorithm, that satisfies these two conditions, is shown in Figure 2. Compared to typical circuit sizing shown in Figure 1, the proposed method has three additional components: evaluating the cost model, updating the cost model, and deciding where in the design space to evaluate cost values. The resulting adaptive modeling based approach provides sufficient samples for accuracy and also avoids over-sampling for optimization.
Figure 2. Conceptual structure of the proposed method.
III. COST FUNCTION MODELING
The flow graph of the proposed algorithm is shown in Figure 3 with stress on additional parts. Figure 3 with stress on additional parts. Figure 1. Structure of typical circuit sizing.
B. Conceptual Structure The basic idea of the proposed method is very simple. The cost model is used to evaluate cost values instead of running expensive SPICE simulations. The mathematical function that maps the design parameters x to a cost value Ψ, is called the cost model. The optimization cost is computed directly by evaluating the cost model for a given set of design parameters without the need to run SPICE simulations. Assuming that the modeling process is a small component of the optimization procedure (this is true for circuit sizing), the advantage of cost modeling is obvious. The computational cost for evaluating the model is very low when compared to cost evaluation via direct SPICE simulation. However, generating the cost model itself requires a number of SPICE runs and this may be more expensive than running multiple SPICE simulations to evaluate the cost function during optimization (simulation-driven cost evaluation). Hence, the cost model-based approach is only favorable when (a) the number of samples needed to generate the cost model is smaller than the number of function evaluations needed during the optimization process and 2) the
Figure 3. The flow graph of the proposed algorithm.
There are several well-known methods for design space sampling such as the Latin hypercube and Taguchi methods, fractional factorial design, etc. These are designed to cover the given input and output domains with geometrically equal
weight. Note that in general, there is a trade-off between accuracy and coverage of the input range. Highly accurate and “fully covered” models require large sample sets and are computationally expensive for modeling. Our goal is to perform as few SPICE evaluations as possible to obtain a cost model with the objective of using the cost model to drive the design towards the most optimal solution. For this, it is not necessary to have a very accurate cost function especially around those design points that are far from the optimal. As long as the gradients of the cost model point in the right direction for points far away from the optimal, there is a high likelihood that the algorithm will converge to the “correct” solution. As the algorithm converges to the optimal, the cost model is updated frequently for more accuracy. A. Sampling Criterion I The proposed sampling scheme is based on two criteria. The first criterion determines whether the cost is to be evaluated via use of the cost model (preferred) or by circuit simulation (for reasons of accuracy) and provides sufficient samples for refining the cost model. During simulated annealing, the cost model is used for cost evaluation. Every time a perturbation is “accepted”, however, a SPICE simulation is also performed to determine the error in the model and to re-evaluate the acceptance criterion. In addition the cost model is updated for the new sample generated. Through this simple sampling scheme, more accuracy is obtained for near-optimal samples and vice versa and the cost model is very accurate near its optimum point. In general, the cost model reaches a state in which it does not need additional samples for accuracy. To avoid over-sampling, we use the sampling criterion described below. B. Sampling Criterion II ˆ The relations between cost function Ψ and the model Ψ can be stated as ˆ ( x) + ε Ψ ( x) = Ψ (1) ˆ where ε denotes the error between Ψ and Ψ . Assuming that ε has a normal distribution with mean µε and standard ˆ with deviation σ ε , the range of Ψ can be estimated from Ψ probability as ˆ ( x) + µ − nσ < Ψ ( x) < Ψ ˆ ( x) + µ + nσ Ψ (2) ε ε ε ε where n determines the confidence of the above equation. For examples, the equation with n=1 covers 68% data and the one with n=2 do 95.5% data. Based on the current best cost value, Ψbest, and the statistics, µε and σ ε , for the last M consecutive error values, the condition, that needs SPICE simulation for the current candidate point, can be defined as ˆ ( x) + µ − nσ Ψ best > Ψ (3) ε ε ˆ Otherwise, we assume that Ψ is trustworthy. For the case in which σ ε is large for roughly fitted model, cost evaluation is mainly determined by sampling criterion I. However, as the
optimization process progresses and the model becomes accurate, sampling criterion II becomes a major role to select a proper evaluator. Finally, when the cost model is very accurate and also σ ε approaches zero, most of the evaluation is done via the use of the cost model. Therefore, many expensive SPICE simulations can be avoided. C. Adaptive Modeling The key factors of modeling are accuracy and modeling time. In this paper, to increase model accuracy and reduce modeling time, local model that is valid only for the current candidate is made at each iteration. That is, interpolation using neighboring data around the current candidate can be done. Therefore, it requires smaller number of samples and achieve higher accuracy due to the smaller valid region of model when compared to global modeling covering the whole input domain or local modeling for arbitrary input on a limited domain. Finally, modeling process takes very small portion in circuit sizing process. At initial stage, model has low accuracy because of low sampling. However, considering the statistical acceptance of simulated annealing that is designed to accept higher cost to alleviate local minima, low accuracy does not affect the whole process of simulated annealing. As the process iterates, sufficient samples are logged from SPICE simulation and high model accuracy can be achieved. In this paper, Multivariate Adaptive Regression Splines (MARS), proposed by Friedman [5], is used for modeling. IV. NUMERICAL RESULTS
Some experiments are performed using the test functions proposed by Dixon and Szegö. Table 1 shows the results of the proposed method, typical simulated annealing, and differential evolution (DE), where optimization parameters such as initial temperature, cooling schedule, etc. are identical for the proposed method and simulated annealing. The results for DE in Table 1 are reported in [6]. The simulated annealing that we use is based on Cauchy annealing. Sample size for initial cost model is set to 20 × N and 3σ is used for sampling criteria II, where N is the input dimension of a function. The algorithms are stopped when the relative error f − f opt / fopt becomes smaller than 1%, where f is the current cost value and fopt is the global optimum value. Table 1. Average number of function evaluations with relative error
{dhhan, chat}@ece.gatech.edu
ABTRACT In this paper we propose a novel simulation-based analog circuit sizing method which is capable of significantly reducing the computational cost via adaptive response surface modeling. The proposed algorithm is based on the selective evaluation of a response surface model coupled with numerical circuit simulation and the adaptive update of the model for accuracy. An effective sampling scheme for modeling using two related criteria that are crucial for speedup and convergence towards an optimal solution is presented. One provides sufficient samples for model accuracy and convergence, whereas the other prevents oversampling of the design space after the model is saturated. Multivariate adaptive regression splines (MARS) are used to construct a model of the selected cost function. Results for several test functions and two test cases are discussed. I. INTRODUCTION As the demands of system-on-chip integrated circuits increase, the design of analog circuits has become a bottleneck in the design phase due to the lack of mature CAD synthesis tools as compared to digital circuits and systems. In this paper, we focus on an automatic transistor level analog circuit sizing method that can be integrated into a complete analog circuit synthesis framework. Distinct research directions in analog circuit sizing can be found in literature [1] and are as follows: 1) equation-based approaches in which a predefined equation set, that defines functions mapping between design parameters and specifications, is utilized in the optimization process, and 2) simulation-based methods in which the optimization process is driven by measurement of circuit performance using SPICE simulation. Each of these methods has its own application-dependent advantages and disadvantages. The simulation-based approach can be applied to any circuit for which a SPICE netlist is available, but is expensive from the viewpoint of simulation cost. Therefore, researchers in this area have focused on the reduction of simulation cost based on ideas such as task parallelization and the design of algorithms This work has been partially supported by DARPA NEOCAD program, NSF ITR under the contract number CCR-032555, and MACRO 2003-DT-660.
with a high rate of convergence. In this paper, we propose a simulation-based circuit sizing method using an adaptive cost model. The goal is to perform a minimum number of SPICE simulations to obtain an optimum set of design parameters for the given target specifications. Previously, model based approaches were proposed for the design of magnetic devices [2] and RF circuits [3]. The method for design of magnetic devices is based on simulated annealing and needs a number of function evaluations that increases exponentially with the number of input parameters. Therefore, the method is applicable to design problems with small numbers of input parameters. The approach for RF circuits is based on the use of genetic algorithms with embedded SPICE simulations and the use of design knowledge. In [4] equation-based behavioral models suitable for optimization via geometric programming methods are proposed and results are shown for some commonly used building blocks. We propose a different approach that can be imported into a typical simulated annealing based optimization framework. The basic idea is to use an accurate cost model to evaluate cost values within a limited region of the design space. This cost model can be evaluated rapidly without running any circuit simulations. Whenever the new candidate is generated at each iteration, an adaptive sampling scheme is used to update the model (which is valid for the limited region for the current candidate) via a minimum number of SPICE simulations in such a way that model inaccuracy is kept within specific bounds. The adaptive sampling approach is determined by the strategy of simulated annealing and the statistics of the differences between the actual and estimated target specification values (estimated from the model). The key features of the proposed method are as follows: 1) Significant reduction of the computational cost due to fewer SPICE simulations and 2) Method is applicable to any circuit for which SPICE netlist is available and results in designs with full SPICE accuracy. The paper is organized as follows: Section 2 presents the basic concepts. In Section 3, we describe the adaptive sampling scheme and cost model. Then, we present numerical results for different test functions and circuit sizing results for two practical cases in Sections 4 and 5. Finally, we provide concluding remarks.
II. PROPOSED APPROACH A. Circuit Sizing Circuit sizing is an optimization process to find a design parameter set x that makes a circuit under design satisfy target specifications. In general, design parameter set x includes transistor dimensions, passive component values, and bias currents in transistor-level circuit sizing. Without loss of generality this process can be converted into a single optimization problem and be stated as find x* ∈ D such that Ψ ( f ( x* )) ≤ Ψ ( f ( x)) , x ∈ D,
where D ⊂ \ n denotes the space of input parameter set, f(·) is a set of objective functions derived from performance specifications, and Ψ(·) is a cost function that converts multiple objective function f(·) into a single one. Typical structure of circuit sizing is shown in Figure 1 and is mainly composed of optimizer and evaluator. Depending on the type of evaluator, circuit sizing method can be divided into simulation-based approach and equation-based approach. To get an optimum solution, global optimizer such as simulated annealing, genetic algorithm, etc. is in widespread as optimizer.
quality of the final solution obtained is not affected by the use of the cost model. The basic structure of the proposed algorithm, that satisfies these two conditions, is shown in Figure 2. Compared to typical circuit sizing shown in Figure 1, the proposed method has three additional components: evaluating the cost model, updating the cost model, and deciding where in the design space to evaluate cost values. The resulting adaptive modeling based approach provides sufficient samples for accuracy and also avoids over-sampling for optimization.
Figure 2. Conceptual structure of the proposed method.
III. COST FUNCTION MODELING
The flow graph of the proposed algorithm is shown in Figure 3 with stress on additional parts. Figure 3 with stress on additional parts. Figure 1. Structure of typical circuit sizing.
B. Conceptual Structure The basic idea of the proposed method is very simple. The cost model is used to evaluate cost values instead of running expensive SPICE simulations. The mathematical function that maps the design parameters x to a cost value Ψ, is called the cost model. The optimization cost is computed directly by evaluating the cost model for a given set of design parameters without the need to run SPICE simulations. Assuming that the modeling process is a small component of the optimization procedure (this is true for circuit sizing), the advantage of cost modeling is obvious. The computational cost for evaluating the model is very low when compared to cost evaluation via direct SPICE simulation. However, generating the cost model itself requires a number of SPICE runs and this may be more expensive than running multiple SPICE simulations to evaluate the cost function during optimization (simulation-driven cost evaluation). Hence, the cost model-based approach is only favorable when (a) the number of samples needed to generate the cost model is smaller than the number of function evaluations needed during the optimization process and 2) the
Figure 3. The flow graph of the proposed algorithm.
There are several well-known methods for design space sampling such as the Latin hypercube and Taguchi methods, fractional factorial design, etc. These are designed to cover the given input and output domains with geometrically equal
weight. Note that in general, there is a trade-off between accuracy and coverage of the input range. Highly accurate and “fully covered” models require large sample sets and are computationally expensive for modeling. Our goal is to perform as few SPICE evaluations as possible to obtain a cost model with the objective of using the cost model to drive the design towards the most optimal solution. For this, it is not necessary to have a very accurate cost function especially around those design points that are far from the optimal. As long as the gradients of the cost model point in the right direction for points far away from the optimal, there is a high likelihood that the algorithm will converge to the “correct” solution. As the algorithm converges to the optimal, the cost model is updated frequently for more accuracy. A. Sampling Criterion I The proposed sampling scheme is based on two criteria. The first criterion determines whether the cost is to be evaluated via use of the cost model (preferred) or by circuit simulation (for reasons of accuracy) and provides sufficient samples for refining the cost model. During simulated annealing, the cost model is used for cost evaluation. Every time a perturbation is “accepted”, however, a SPICE simulation is also performed to determine the error in the model and to re-evaluate the acceptance criterion. In addition the cost model is updated for the new sample generated. Through this simple sampling scheme, more accuracy is obtained for near-optimal samples and vice versa and the cost model is very accurate near its optimum point. In general, the cost model reaches a state in which it does not need additional samples for accuracy. To avoid over-sampling, we use the sampling criterion described below. B. Sampling Criterion II ˆ The relations between cost function Ψ and the model Ψ can be stated as ˆ ( x) + ε Ψ ( x) = Ψ (1) ˆ where ε denotes the error between Ψ and Ψ . Assuming that ε has a normal distribution with mean µε and standard ˆ with deviation σ ε , the range of Ψ can be estimated from Ψ probability as ˆ ( x) + µ − nσ < Ψ ( x) < Ψ ˆ ( x) + µ + nσ Ψ (2) ε ε ε ε where n determines the confidence of the above equation. For examples, the equation with n=1 covers 68% data and the one with n=2 do 95.5% data. Based on the current best cost value, Ψbest, and the statistics, µε and σ ε , for the last M consecutive error values, the condition, that needs SPICE simulation for the current candidate point, can be defined as ˆ ( x) + µ − nσ Ψ best > Ψ (3) ε ε ˆ Otherwise, we assume that Ψ is trustworthy. For the case in which σ ε is large for roughly fitted model, cost evaluation is mainly determined by sampling criterion I. However, as the
optimization process progresses and the model becomes accurate, sampling criterion II becomes a major role to select a proper evaluator. Finally, when the cost model is very accurate and also σ ε approaches zero, most of the evaluation is done via the use of the cost model. Therefore, many expensive SPICE simulations can be avoided. C. Adaptive Modeling The key factors of modeling are accuracy and modeling time. In this paper, to increase model accuracy and reduce modeling time, local model that is valid only for the current candidate is made at each iteration. That is, interpolation using neighboring data around the current candidate can be done. Therefore, it requires smaller number of samples and achieve higher accuracy due to the smaller valid region of model when compared to global modeling covering the whole input domain or local modeling for arbitrary input on a limited domain. Finally, modeling process takes very small portion in circuit sizing process. At initial stage, model has low accuracy because of low sampling. However, considering the statistical acceptance of simulated annealing that is designed to accept higher cost to alleviate local minima, low accuracy does not affect the whole process of simulated annealing. As the process iterates, sufficient samples are logged from SPICE simulation and high model accuracy can be achieved. In this paper, Multivariate Adaptive Regression Splines (MARS), proposed by Friedman [5], is used for modeling. IV. NUMERICAL RESULTS
Some experiments are performed using the test functions proposed by Dixon and Szegö. Table 1 shows the results of the proposed method, typical simulated annealing, and differential evolution (DE), where optimization parameters such as initial temperature, cooling schedule, etc. are identical for the proposed method and simulated annealing. The results for DE in Table 1 are reported in [6]. The simulated annealing that we use is based on Cauchy annealing. Sample size for initial cost model is set to 20 × N and 3σ is used for sampling criteria II, where N is the input dimension of a function. The algorithms are stopped when the relative error f − f opt / fopt becomes smaller than 1%, where f is the current cost value and fopt is the global optimum value. Table 1. Average number of function evaluations with relative error
