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IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 58, NO. 5, MAY 2009
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Analysis of a Sigma–Delta Resistance-to-Digital Converter for Differential Resistive Sensors N. Madhu Mohan, Boby George, and V. Jagadeesh Kumar, Member, IEEE
Abstract—A direct resistance-to-digital converter (RDC) that is suitable for differential resistive sensors is proposed and analyzed in this paper. The RDC presented here provides a digital output that is linearly proportional to the parameter being sensed by a differential resistive sensor possessing either linear or inverse characteristics. The RDC employs the sigma–delta analog-todigital conversion (Σ–Δ ADC) principle and, hence, possesses all the advantages and limitations of such an ADC. Analysis shows that the proposed RDC has negligible sensitivity to variations in circuit parameters. Experimental results on a prototype built and tested gave a worst-case error < 0.15%, establishing the efficacy of the proffered RDC. Index Terms—Differential resistive sensor, direct digital converter, resistance-to-digital converter (RDC), signal conditioning, sigma–delta (Σ–Δ) converter.
I. I NTRODUCTION
D
IFFERENTIAL resistive sensors are quite popular for the measurement of physical variables such as displacement and pressure. A typical differential resistive sensor possesses two resistances. The value of one of the resistors of the sensor (for example, R1 ) will increase with the measurand, while the value of the other resistor (R2 ) will decrease. The values of the resistances of a differential resistive sensor possessing a linear characteristic can be expressed as [1] R1 = R0 (1 ± kx),
R2 = R0 (1 ∓ kx)
(1)
where k is the transformation constant of the sensor and R0 is the nominal value of the resistor when x, which is the input parameter being sensed, is zero. On the other hand, the resistance of a differential resistive sensor possessing an inverse characteristic can be expressed as [2] R1 =
R0 , (1 ∓ kx)
R2 =
R0 . (1 ± kx)
(2)
To obtain a measurable output from a differential resistive sensor, a suitable analog signal conditioning circuit such as a Wheatstone bridge is required. Modern instrumentation systems are of the digital kind, as digital systems offer inManuscript received June 21, 2008; revised December 18, 2008. First published February 6, 2009; current version published April 7, 2009. The Associate Editor coordinating the review process for this paper was Dr. Izzet Kale. N. M. Mohan and V. J. Kumar are with the Measurements and Instrumentation Laboratory, Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai 600036, India (e-mail: [email protected]). B. George is with the University of Graz, 8010 Graz, Austria. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIM.2009.2012949
Fig. 1. Proposed Σ–Δ RDC.
creased processing power and excellent user interface compared with their analog counterparts. An analog-to-digital converter (ADC) is required to interface the output from an analog signal conditioner to a digital instrumentation system [3], [4]. It would be advantageous if the signal conditioning circuit directly provides a digital output without the need for an intervening ADC. Such a signal conditioning circuit is called a direct digital converter. Direct capacitance-to-digital converters (CDCs), based on the principles of the relaxation oscillator [5] and the sigma–delta (Σ–Δ) ADC [6]–[8], that are suitable for capacitive type sensors have been reported. Techniques that provide resistance-to-digital conversion using an RC oscillator and timer-counter [9], resistance-to-frequency [10], and resistance-to-time [11] conversions are available for single-element resistive sensors. A method based on capacitor charging that is suitable for both single (half-bridge) and differential (full-bridge) resistive sensors is also reported [12]. Methods that are suitable for differential resistive sensors based on integrating-type ADC have also been reported [13]–[15]. A novel direct resistance-to-digital converter (RDC) that is suitable for differential resistive sensors is proposed [16]. The proposed scheme, based on the principle of the popular Σ–Δ ADC, accepts differential resistive sensors possessing either linear or inverse characteristics and provides a linear digital output that is proportional to the measurand being sensed by the differential resistive sensor. The analysis presented in this paper indicates that the proposed scheme is not affected by the nonideal characteristics of components and that the sensitivity of the output to variations in the nominal values of the components is minimal. Parameters that decide the error in the output and the critical components that dictate the accuracy of the output are clearly identified. II. Σ–Δ RDC Fig. 1 shows the functional block diagram of the Σ–Δ-type RDC that is suitable for a differential resistive sensor. The RDC is made of a Δ-modulator, followed by an oversampler
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and a digital filter. The op-amp OA with capacitor CF in its feedback path and resistors R1 and R2 of a differential resistive sensor, in combination with two single-pole–doublethrow (SPDT) analog switches S1 and S2 serving as input, form an integrator. The free end of R1 is switched to +VR when S1 is in position 2 and connected to ground when S1 is in position 1. When S2 is in position 1, the free end of R2 is connected to −VR , while when S2 is in position 2, it is connected to ground. +VR and −VR are dc reference voltages of equal magnitude but of opposite polarities. The output voi of the integrator is fed to a comparator OC whose output is “low” if voi ≥ 0 and “high” otherwise. The output of OC is given to the input of a D flip-flop whose binary output y controls switches S1 and S2 . Switches S1 and S2 are set at position 1 if y = 1 and set at position 2 whenever y = 0. The D-flip-flop output y, which is updated (for example, at the leading edge) by a high-frequency clock of time period TC , is also fed as input to a digital lowpass-filter (LPF)-based circuit, which extracts and provides as the final output (1 − 2y|avg ), where y|avg is the average value of the LPF input bit stream y. To start with, let voi < 0 and y = 1. Hence, switches S1 and S2 are set at position 1. R1 is connected to ground, and R2 is tied to −VR . voi ramps up with a slope of (VR /R2 CF ) until it becomes positive. Once voi is positive, the comparator output becomes low. The D-flip-flop output gets updated at the very next (leading edge of the) clock, and the output y toggles (y = 0). When y = 0, switches S1 and S2 are set to position 2, grounding resistance R2 and connecting R1 to +VR . The current VR /R1 charges CF . Consequently, voi ramps down with a slope VR /R1 CF until voi turns negative, forcing the output of the comparator to go high. The D-type flip-flop output gets updated on the next clock, making y = 1, bringing the status of the circuit to its assumed initial condition, and hence, the entire cycle repeats continuously. When y = 1, the change in integrator voltage for each clock period is Δvoi(1) = VR TC /R2 CF . Similarly, when y = 0, the change in integrator voltage for each clock period is Δvoi(0) = −VR TC /R1 CF . After a finite number of clock cycles, for instance, N (period T = N TC ), the integrator output is voi(N ) =
VR TC VR TC N(1) − N(0) R2 CF R1 CF
where N(1) and N(0) are the numbers of clock cycles for which the output values of D flip-flop are 1 and 0, respectively, within the period T and N = N(1) + N(0) . If N is sufficiently large, then the value of voi(N ) has to be less than or equal to the maximum possible change in integrator voltage per clock cycle voi(m) , where voi(m) = VR TC /(R1 , R2 )min CF
(3)
and (R1 , R2 )min is the minimum among R1 and R2 . Then N(0) VR TC N(1) 1 VR TC − . (4) ≤ CF R2 R1 CF (R1 , R2 )min On further simplification, we get N(1) R1 − N(0) R2 ≤ (R1 , R2 )max
where (R1 , R2 )max is the maximum of R1 and R2 . Substituting the values of R1 and R2 of a differential resistive sensor possessing linear characteristics, as given by (1) in (5), results in (R0 (1 ± kx)N(1) − R0 (1 ∓ kx)N(0) ) ≤ (R1 , R2 )max , leading to R0 1 N(1) − N(0) ± kxN ≤ (R1 , R2 )max . N N
(6)
For a very large value of N , the value of 1/N (R1 , R2 )max becomes small, and hence
N(0) − N(1) N(1) kx = =1−2 = 1 − 2y avg . N N (7) (N(1) /N ) is the average value y|avg of the bit stream y over the period N TC . Since the digital LPF-based circuit is designed to extract (1 − 2y|avg )—as mentioned earlier—its output is kx. Hence, for differential resistive sensors possessing linear characteristics, as given by (1), the proposed technique provides a linear digital output that is proportional to the quantity being sensed. Very rarely, differential resistive sensors possess inverse characteristics, as given by (2). It turns out that substituting the values of R1 and R2 , as given by (2) in (5), also results in (7). Thus, the proposed method provides a linear digital output that is proportional to the measurand, even if the differential resistive sensor follows an inverse relationship, as given in (2). The results of simulation studies and details of a prototype RDC built and tested using off-the-shelf components are given in the sequel. The errors introduced due to various circuit parameter variations are analyzed next. III. E RROR A NALYSIS AND D ISCUSSION It should be noted here that the proposed RDC is obtained by suitably converting the 1-b quantizer (Δ-modulator) in a conventional Σ–Δ ADC. Hence, the proposed method will necessarily possess noise shaping characteristics, bandwidth limitations, and uncertainties, as detailed in IEEE Std. 1241–2005 [17] and elsewhere [18]–[21]. Over and above the well-known and well-established uncertainties, the RDC will possess additional errors due to the modification itself. The possible errors that would arise due to the modification, such as introduction of switches and two reference voltages instead of one as in a conventional Σ–Δ ADC, are analyzed next. Ideal conditions are assumed while deriving (3), (5), and (6). In a practical case, errors will be introduced in the output due to the following factors: 1) difference in the magnitudes of the positive and negative dc reference voltages; 2) offset voltages of OA and OC; 3) on-resistances of the switches; 4) switch leakage currents; 5) op-amp bias current; and 6) stray capacitances. The following sections discuss in detail the effect of each parameter on the output. A. Effect of Mismatch in DC Reference Voltages
(5)
The magnitudes of dc reference voltages +VR and −VR are assumed to be equal in deriving (5). However, in practice, there
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MOHAN et al.: ANALYSIS OF A SIGMA–DELTA RDC FOR DIFFERENTIAL RESISTIVE SENSORS
will be a small mismatch between them, and hence, in general, | + VR | = | − VR |(1 ± β), where β is the factor indicating the extent of mismatch. In such a condition, (5) gets modified as (N(1) (1 ± β)R1 − N(0) R2 ) ≤ (R1 , R2 )max . Hence N(0) − N(1) ∓ βN(1) ±kx = N ± βN(1) ⎡ ⎤ N(0) − N(1) βN(1) 1
⎦ . =⎣ ∓ N N N 1 ± β (1) N
For (β(N(1) /N )) 1 and neglecting (β(N(1) /N ))2 and higher powers of (β(N(1) /N )), we get N(0) −N(1) βN(1) N(1) ∓ ±kx = 1∓β N N N = (1−2y|avg ) (1∓βy|avg )∓(βy|avg )±(βy|avg )2 . The resulting relative error εVR is shown at the bottom of the page. For full-scale reading, if y|avg → 1, then εVR = =
(1 − 2)(1 ∓ β) ∓ (β) ± (β)2 − (1 − 2) (1 − 2) (−1)(1 ∓ β) ∓ (β) ± (β)2 − (−1) = 2β + β 2 (−1)
resulting in the error due to mismatch in dc reference voltages as % εVR = (2β + β 2 ) 100.
(8)
For the prototype developed, β was found to be 4 × 10−5 , and the error in the output due to mismatch in dc reference voltages works out to be 0.008%. B. Effects of Offset Voltages of Op-Amp OA and Comparator OC If the op-amp OA has an offset voltage ±vos , then the voltages across the sensor resistances R1 and R2 become (+VR ∓ vos ) and (−VR ∓ vos ), respectively. This condition is equivalent to a mismatch of 2vos between the magnitudes of dc reference voltages +VR and −VR . Thus, by taking β = 2vos /VR , the ensuing error in the output can be computed using (8). For the prototype, op-amp OP07, which has a maximum offset voltage of 25 μV, was used, resulting in a worst-case error of 0.004%. The offset voltage of the comparator shifts its reference point by the same amount from zero. As long as the offset voltage of OC remains constant (comparator that has negligible offset drift
εVR =
1619
within one conversion period) during a complete conversion period, it has negligible effect on the final output. C. Effects of On-Resistance of the Switches In the proposed scheme, the on-resistance rON1 of switch S1 is in series with R1 , while the on-resistance rON2 of switch S2 is in series with R2 . It is equivalent to a change in the values of sensor resistances R1 and R2 with new values (R1 + rON1 ) and (R2 + rON2 ), respectively. In this condition, (5) gets modified as (N(1) R1 + N(1) rON1 − N(0) R2 − N(0) rON2 ) ≤ (R1 , R2 )max , and hence, we have rON1 −rON2 1 (1−2y|avg) = ±kx − . R0 +rON1 +rON2 1+ rON1R+r0 ON2 (9) Comparison of (7) and (9) indicates that the switch onresistances introduce a gain error and an offset in the output. If we employ identical switches for S1 and S2 , then rON1 ≈ rON2 , and the offset will be zero. The gain error can be made negligible by ensuring that R0 (rON1 + rON2 ). For the prototype, MAX4680 switches (rON = 1.25 Ω) were used, resulting in a gain error of −0.42% and an offset of 0.05% with R0 = 600 Ω. The gain error and the offset, if present, can be easily reduced by providing suitable compensation. In fact, this is the only significant factor contributing to the errors in the proposed RDC, and therefore, care must be taken to minimize this error. D. Effects of Switch Leakage Currents Leakage currents between nodes 1 and 2 of switches S1 and S2 flow from the dc reference sources to the circuit ground and hence do not charge or discharge CF . When S1 is at position 1, leakage current IL1 exists between nodes 2 and A. In this condition, the resistance between nodes A and 1 is rON1 . As rON R0 , a large portion of the leakage current IL1 flows to circuit ground via node 1, and a negligible amount—IL1 [rON1 /(rON1 + R1 )]—compared with the sensor current of (VR /R1 ), flows through R1 . Similar conditions are applicable for S2 . Thus, in a practical situation, switch leakage currents have negligible effect on the output. For the prototype, the leakage current was 5 nA, resulting in negligible error. E. Effect of Bias Current of the Op-Amp OA Depending on its polarity, the op-amp bias current (IB ) of OA charges the capacitor CF in a given direction throughout a typical conversion time. The bias current manifests as a change in the charging currents as ((VR /R1 ) ± IB ) and ((VR /R2 ) ∓ IB ) through the sensor resistances R1 and R2 , respectively.
(1 − 2y|avg ) (1 ∓ βy|avg ) ∓ (βy|avg ) ± (βy|avg )2 − (1 − 2y|avg ) (1 − 2y|avg )
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Fig. 2. Differential resistive sensor elements with possible stray capacitances. Nodes A and C are connected to S1 and S2 , respectively, while node B is connected to the inverting terminal of the op-amp OA, as shown in Fig. 1.
It can also be represented as an equivalent change in the dc reference voltage +VR . Thus, it is equivalent to a mismatch between reference voltages, and the ensuing worst-case fullscale error due to the bias current of the op-amp OA can be computed using (8) by substituting for β = (IB /VR )(R1 + R2 ) = 2(IB R0 /VR ). The effect can be made insignificant by selecting an op-amp with very low IB —satisfying the condition IB VR /R0 —to realize OA.
Fig. 3.
Simulation results for a sensor with linear characteristics.
Fig. 4.
Simulation results for a sensor possessing inverse characteristics.
F. Effect of Stray Capacitances In practice, it may well be that the sensor unit is far from the signal conditioning unit and that the electrical connections between these units are made using shielded cables. Distributed capacitances will exist between the live conductor of each cable and its grounded shield. This effect can be represented by lumped stray capacitances, as shown in Fig. 2. Stray capacitances CAG , CBG , and CCG exist from nodes A, B, and C, respectively, to ground. CAG charges to +VR when S1 is at position 2. Similarly, CCG charges to −VR when S2 is at position 1. Whenever S1 is switched to position 1 and S2 to position 2, the charge acquired by the corresponding capacitances CAG and CCG discharges to ground through the lowimpedance path offered by the switch on-resistance. As long as the time-constant rON1 CAG R1 CAG and rON1 CCG R2 CCG , the stray capacitances CAG and CCG will have negligible effect on the operation of the circuit. As node B is always at virtual ground, CBG will not charge or discharge during the operation of the circuit. IV. S IMULATION S TUDIES Before prototyping the circuit shown in Fig. 1, it was simulated using OrCAD PSpice (version 9.0). Since a model of the digital filter AD1556 was not available, the low-pass digital function of the AD15556 was realized by a switching and averaging technique. The resistance of the differential resistive sensor was varied in a range of +50% of its nominal value of 600 Ω, in steps of ±5%. To simulate the effect of the switch resistance (rON ), a resistor of 1.25 Ω was included in series with the sensor resistances. The output was sampled after the simulation was allowed to run for 200 ms to ensure that all transients die out. First, the resistances were varied linearly, as given by (1), and the output and error for this case are shown in Fig. 3. A similar simulation was run for a sensor with inverse characteristics of the form given by (2), and the results are shown in Fig. 4. The circuit was again simulated with the switch resistances suitably modified in order to determine the effect of mismatch in rON . It was found that the worst possible
error in the output for a mismatch of 100% was only 0.51%. Similarly, the magnitude of the reference voltages was altered to understand its effect on the output. A 1% mismatch in their magnitudes produced a maximum variation of 4.12% in the output. V. E XPERIMENTAL R ESULTS A prototype Σ–Δ RDC was built and tested in the laboratory. The reference voltage +VR was generated using the reference diode LM385-1.2 [22], which was buffered with a voltage follower (op-amp OP07) [23]. −VR was obtained with the help of a unity gain inverter realized with a second OP07. The magnitude of −VR was trimmed to obtain a match (up to five digits) between +VR and −VR . SPDT switches were realized with IC MAX4680 [24] (possessing low on-resistance rON = 1.25 Ω). A third OP07 served as the op-amp OA. The value of the feedback capacitor was chosen as 0.33 μF to limit the maximum change in the integrator voltage per clock cycle to be less than the slew rate of the OP07. An LM311 IC [25] served as the comparator (OC), and the CD4013 [26] was employed for the D flip-flop. To extract y|avg , the IC AD1556 was employed. The AD1556 [27] implements a finite-impulseresponse linear-phase equiripple LPF and a decimator. The modulator clock frequency was chosen to be 20 kHz. A suitable program was written and burned into a PIC16F877A microcontroller [28] to read the output y|avg from the AD1556, compute,
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MOHAN et al.: ANALYSIS OF A SIGMA–DELTA RDC FOR DIFFERENTIAL RESISTIVE SENSORS
Fig. 5. Output of D flip-flop (y) and integrator voltage voi , along with the clock signal recorded from the prototype.
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and the form of the final digital output is chosen so that the RDC provides a linear digital output that is proportional to the parameter being sensed by sensors possessing either linear or inverse characteristics and is hence applicable to both types of sensors without any change. The resolution required in applications involving differential resistive sensors seldom exceeds 16 b, which is easily achievable (the prototype built and tested had a resolution of 24 b) with the present technique. The conversion speed of few hundred samples per second to few tens of thousand samples per second that is achievable with the Σ–Δ converter topology is more than adequate for applications (distance and pressure sensing) concerning differential resistive sensors. The effects of various circuit parameters on the performance of the RDC are analyzed and found to be negligible or can be made so with proper selection of the circuit components. Simulation studies and experimental results obtained from a prototype built and tested establish the practicality of the proposed RDC. The worst-case error of the prototype was found to be less than ±0.15%. This type of RDC is best suited for micromechanical systems type of applications. R EFERENCES
Fig. 6.
Experimental results of the prototype Σ–Δ RDC.
and then display (1 − 2y|avg ) on a five-digit seven-segment display. A typical conversion time of the prototype Σ–Δ RDC was 40 ms. The prototype developed was tested with resistive sensors possessing linear as well as inverse characteristics. It was found to provide a linear digital output in both cases. Typical waveforms obtained from the prototype are shown in Fig. 5. To test the performance of the prototype RDC, transducer resistances were simulated using two precision decade resistance boxes from Otto Wolff, Germany, having a resolution of 1 Ω and an accuracy of ±0.01%. The nominal value of the resistances was selected as 600 Ω, and R1 and R2 were varied up to 300 Ω in steps of 6 Ω, to simulate a kx variation in the range of ±0.5, with increments of ±0.01. The output characteristic, along with the percentage relative error of the prototype, is shown in Fig. 6. The worst-case error was found to be less than ±0.15%. VI. C ONCLUSION An RDC that provides a direct digital output that is proportional to the parameter being sensed by a differential resistive sensor is presented. The topology of the RDC is obtained by incorporating the differential resistive sensor as an integral part of a first-order 1-b quantizer of a conventional Σ–Δ ADC. Hence, the proposed RDC has all the advantages and limitations of a typical Σ–Δ ADC. The quantizer is controlled suitably,
[1] E. O. Doebelin, Measurement Systems—Application and Design, 5th ed. New York: McGraw-Hill, 2004. [2] “Data sheet, sensor A201,” Flexiforce—The Leader in Standard and Custom OEM Force Sensing Solutions, Tekscan Inc., Boston, MA, Jan. 2007. [Online]. Available: http://www.tekscan.com/flexiforce.html [3] J. K. Gustafsson, “Analog–digital converter for a resistance bridge,” U.S. Patent 3 960 010, Jun. 1, 1976. [4] J. T. Adams, T. M. Tinsley, and P. L. Brown, “Analog-to-digital converter to be used along with a resistive sensor,” U.S. Patent 5 144 309, Sep. 1, 1992. [5] K. Mochizuki and K. Watanabe, “A relaxation-oscillator-based interface for high-accuracy ratiometric signal processing of differential-capacitance transducers,” IEEE Trans. Instrum. Meas., vol. 47, no. 1, pp. 11–14, Feb. 1998. [6] B. Wang, T. Kajita, T. Sun, and G. C. Temes, “High-accuracy circuits for on-chip capacitive ratio testing and sensor readout,” IEEE Trans. Instrum. Meas., vol. 47, no. 1, pp. 16–20, Feb. 1998. [7] R. Schreier and G. C. Temes, Understanding Delta–Sigma Data Converters. Hoboken, NJ: Wiley, 2005. [8] J. Haze, R. Vrba, L. Fujcik, J. Forejtek, P. Zavoral, M. Paulik, and L. Michaeli, “Band pass sigma–delta modulator for capacitive pressure sensor,” in Proc. IEEE IMTC, Warsaw, Poland, May 1–3, 2007, pp. 1–6. [9] T. Nohara, “Resistance-to-digital converter,” U.S. Patent 008 576 7A1, May 8, 2003. [10] K. Mochizuki and K. Watanabe, “A high-resolution, linear resistanceto-frequency converter,” IEEE Trans. Instrum. Meas., vol. 45, no. 3, pp. 761–764, Jun. 1996. [11] S. Kaliyugavaradhan, “A linear resistance-to-time converter with high resolution,” IEEE Trans. Instrum. Meas., vol. 49, no. 1, pp. 151–153, Feb. 2000. [12] J. Jordana and R. Palls-Areny, “A simple, efficient interface circuit for piezoresistive pressure sensors,” Sens. Actuators A, Phys., vol. 127, no. 1, pp. 69–73, Feb. 2006. [13] E. W. Owen, “An integrating analog-to-digital converter for differential transducers,” IEEE Trans. Instrum. Meas., vol. IM-28, no. 3, pp. 216–220, Sep. 1979. [14] V. J. Kumar, N. M. Mohan, and V. G. K. Murti, “Digital converter for push–pull type resistive transducers,” in Proc. IEEE IMTC, Ottawa, ON, Canada, May 17–19, 2005, pp. 422–425. [15] N. M. Mohan, B. George, and V. J. Kumar, “Dual-slope resistance-todigital converter,” in Proc. IEEE IMTC, Warsaw, Poland, May 1–3, 2007, pp. 1–5. [16] N. M. Mohan, B. George, and V. J. Kumar, “A sigma–delta resistance to digital converter suitable for differential resistive sensors,” in Proc. IEEE I2MTC, Victoria, BC, Canada, May 12–15, 2008, pp. 1159–1161. [17] IEEE Standards for Terminology and Test Methods for Analog-to-Digital Converters, 2001. IEEE Std. 1241-2000.
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[18] M. R. Gani, “Robust digital correction of analog errors in cascaded sigma delta converters,” J. Meas., vol. 37, no. 4, pp. 310–319, Jun. 2005. [19] D. W. Braudaway, “Uncertainty specification for data acquisition (DAQ) devices,” IEEE Trans. Instrum. Meas., vol. 55, no. 1, pp. 74–78, Feb. 2006. [20] F. Attivissimo, N. Giaquinto, and M. Savino, “Worst-case uncertainty measurement in ADC-based instruments,” Comput. Stand. Interfaces, vol. 29, no. 1, pp. 5–10, Jan. 2006. [21] A. Strak, “Timing uncertainty in sigma delta analog to digital converters,” Ph.D. dissertation, Royal Inst. Technol., Stockholm, Sweden, 2006. [22] “Data sheet, LM185-1.2/LM285-1.2/LM385-1.2,” Micropower Voltage Reference Diode, Nat. Semiconductor Corp., Santa Clara, CA, Jan. 2008. [Online]. Available: http://www.national.com/ds/LM/LM185-1.2.pdf [23] “Data sheet, OP-07,” Ultra Low Offset Voltage Operational Amplifier, Analog Devices Inc., Norwood, MA, Jan. 2006. [Online]. Available: http://www.analog.com/static/imported-files/data_sheets/OP07.pdf [24] “Data sheet, MAX4680,” 1.25 Ω dual SPST CMOS switches, Maxim Integr. Product Sunnyvale, CA, Jul. 1999. [Online]. Available: http:// datasheets.maxim-ic.com/en/ds/MAX4680-MAX4700.pdf [25] “Data sheet, LM311,” Voltage Comparator, Nat. Semiconductor Corp., Santa Clara, CA, Jan. 2004. [Online]. Available: http://www.national. com/ds/LM/LM111.pdf [26] “Data sheet, CD4013,” Dual D-Flip Flop, Nat. Semiconductor Corp., Santa Clara, CA, Feb. 1988. [Online]. Available: http://www.national. com/ds/CD/CD4013BM.pdf [27] “Data sheet, AD1555/AD1556,” 24-bit Σ–Δ ADC with low noise PGA, Analog Devices Inc., Norwood, MA, May 2002. [Online]. Available: http://www.analog.com/static/imported-files/data_sheets/ AD1555_1556.pdf [28] “Data sheet, PIC16F87XA,” 28/40/44-Pin Enhanced Flash Microcontrollers, Microchip Technol. Inc., Chandler, AZ, Jan. 2003. [Online]. Available: http://ww1.microchip.com/downloads/en/DeviceDoc/ 39582b.pdf
N. Madhu Mohan was born in Coimbatore, India, on March 21, 1970. He received the B.S. degree in electronics and communication engineering from the University of Calicut, Kerala, India, in 1991 and the M.S. degree (by research) from the Indian Institute of Technology Madras, Chennai, India, in 2003, where he is currently working toward the Ph.D. degree in biomedical instrumentation with the Measurements and Instrumentation Laboratory, Department of Electrical Engineering. His interests include measurements, biomedical instrumentation, and virtual instrumentation.
Boby George was born in Kannur, India, on April 30, 1977. He received the B.S. degree in electrical engineering from the Institution of Engineers, Kolkata, India, in 2001 and the M.S. and Ph.D. degrees in electrical engineering from the Indian Institute of Technology Madras, Chennai, India, in 2003 and 2007, respectively. He is currently a Postdoctoral Fellow with the University of Graz, Graz, Austria. His areas of interest include measurements, instrumentation, and virtual instrumentation.
V. Jagadeesh Kumar (M’94) was born in Madras, India, on July 21, 1956. He received the B.E. degree in electronics and telecommunication engineering from the University of Madras, Chennai, India, in 1978 and the M.Tech. and Ph.D. degrees in electrical engineering from the Indian Institute of Technology (IIT) Madras, Chennai, in 1980 and 1986, respectively. He is currently the Head of the Department of Electrical Engineering, IIT Madras, where he is with the Measurements and Instrumentation Laboratory. He was a BOYSCAST Fellow with King’s College, London, U.K., during 1987–1988 and a DAAD Fellow with the Technical University of Braunschweig, Braunschweig, Germany, in 1997. He was a Visiting Scientist with the Technical University of Aachen, Aachen, Germany, in 1999. He taught for a term at the Asian Institute of Technology, Bangkok, Thailand, in the summer of 1999. He has published more than 40 papers in international journals and presented more than 60 papers at various conferences. He is the holder of six patents. His teaching and research interests include measurements, instrumentation, and signal processing.
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Analysis of a Sigma–Delta Resistance-to-Digital Converter for Differential Resistive Sensors N. Madhu Mohan, Boby George, and V. Jagadeesh Kumar, Member, IEEE
Abstract—A direct resistance-to-digital converter (RDC) that is suitable for differential resistive sensors is proposed and analyzed in this paper. The RDC presented here provides a digital output that is linearly proportional to the parameter being sensed by a differential resistive sensor possessing either linear or inverse characteristics. The RDC employs the sigma–delta analog-todigital conversion (Σ–Δ ADC) principle and, hence, possesses all the advantages and limitations of such an ADC. Analysis shows that the proposed RDC has negligible sensitivity to variations in circuit parameters. Experimental results on a prototype built and tested gave a worst-case error < 0.15%, establishing the efficacy of the proffered RDC. Index Terms—Differential resistive sensor, direct digital converter, resistance-to-digital converter (RDC), signal conditioning, sigma–delta (Σ–Δ) converter.
I. I NTRODUCTION
D
IFFERENTIAL resistive sensors are quite popular for the measurement of physical variables such as displacement and pressure. A typical differential resistive sensor possesses two resistances. The value of one of the resistors of the sensor (for example, R1 ) will increase with the measurand, while the value of the other resistor (R2 ) will decrease. The values of the resistances of a differential resistive sensor possessing a linear characteristic can be expressed as [1] R1 = R0 (1 ± kx),
R2 = R0 (1 ∓ kx)
(1)
where k is the transformation constant of the sensor and R0 is the nominal value of the resistor when x, which is the input parameter being sensed, is zero. On the other hand, the resistance of a differential resistive sensor possessing an inverse characteristic can be expressed as [2] R1 =
R0 , (1 ∓ kx)
R2 =
R0 . (1 ± kx)
(2)
To obtain a measurable output from a differential resistive sensor, a suitable analog signal conditioning circuit such as a Wheatstone bridge is required. Modern instrumentation systems are of the digital kind, as digital systems offer inManuscript received June 21, 2008; revised December 18, 2008. First published February 6, 2009; current version published April 7, 2009. The Associate Editor coordinating the review process for this paper was Dr. Izzet Kale. N. M. Mohan and V. J. Kumar are with the Measurements and Instrumentation Laboratory, Department of Electrical Engineering, Indian Institute of Technology Madras, Chennai 600036, India (e-mail: [email protected]). B. George is with the University of Graz, 8010 Graz, Austria. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIM.2009.2012949
Fig. 1. Proposed Σ–Δ RDC.
creased processing power and excellent user interface compared with their analog counterparts. An analog-to-digital converter (ADC) is required to interface the output from an analog signal conditioner to a digital instrumentation system [3], [4]. It would be advantageous if the signal conditioning circuit directly provides a digital output without the need for an intervening ADC. Such a signal conditioning circuit is called a direct digital converter. Direct capacitance-to-digital converters (CDCs), based on the principles of the relaxation oscillator [5] and the sigma–delta (Σ–Δ) ADC [6]–[8], that are suitable for capacitive type sensors have been reported. Techniques that provide resistance-to-digital conversion using an RC oscillator and timer-counter [9], resistance-to-frequency [10], and resistance-to-time [11] conversions are available for single-element resistive sensors. A method based on capacitor charging that is suitable for both single (half-bridge) and differential (full-bridge) resistive sensors is also reported [12]. Methods that are suitable for differential resistive sensors based on integrating-type ADC have also been reported [13]–[15]. A novel direct resistance-to-digital converter (RDC) that is suitable for differential resistive sensors is proposed [16]. The proposed scheme, based on the principle of the popular Σ–Δ ADC, accepts differential resistive sensors possessing either linear or inverse characteristics and provides a linear digital output that is proportional to the measurand being sensed by the differential resistive sensor. The analysis presented in this paper indicates that the proposed scheme is not affected by the nonideal characteristics of components and that the sensitivity of the output to variations in the nominal values of the components is minimal. Parameters that decide the error in the output and the critical components that dictate the accuracy of the output are clearly identified. II. Σ–Δ RDC Fig. 1 shows the functional block diagram of the Σ–Δ-type RDC that is suitable for a differential resistive sensor. The RDC is made of a Δ-modulator, followed by an oversampler
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and a digital filter. The op-amp OA with capacitor CF in its feedback path and resistors R1 and R2 of a differential resistive sensor, in combination with two single-pole–doublethrow (SPDT) analog switches S1 and S2 serving as input, form an integrator. The free end of R1 is switched to +VR when S1 is in position 2 and connected to ground when S1 is in position 1. When S2 is in position 1, the free end of R2 is connected to −VR , while when S2 is in position 2, it is connected to ground. +VR and −VR are dc reference voltages of equal magnitude but of opposite polarities. The output voi of the integrator is fed to a comparator OC whose output is “low” if voi ≥ 0 and “high” otherwise. The output of OC is given to the input of a D flip-flop whose binary output y controls switches S1 and S2 . Switches S1 and S2 are set at position 1 if y = 1 and set at position 2 whenever y = 0. The D-flip-flop output y, which is updated (for example, at the leading edge) by a high-frequency clock of time period TC , is also fed as input to a digital lowpass-filter (LPF)-based circuit, which extracts and provides as the final output (1 − 2y|avg ), where y|avg is the average value of the LPF input bit stream y. To start with, let voi < 0 and y = 1. Hence, switches S1 and S2 are set at position 1. R1 is connected to ground, and R2 is tied to −VR . voi ramps up with a slope of (VR /R2 CF ) until it becomes positive. Once voi is positive, the comparator output becomes low. The D-flip-flop output gets updated at the very next (leading edge of the) clock, and the output y toggles (y = 0). When y = 0, switches S1 and S2 are set to position 2, grounding resistance R2 and connecting R1 to +VR . The current VR /R1 charges CF . Consequently, voi ramps down with a slope VR /R1 CF until voi turns negative, forcing the output of the comparator to go high. The D-type flip-flop output gets updated on the next clock, making y = 1, bringing the status of the circuit to its assumed initial condition, and hence, the entire cycle repeats continuously. When y = 1, the change in integrator voltage for each clock period is Δvoi(1) = VR TC /R2 CF . Similarly, when y = 0, the change in integrator voltage for each clock period is Δvoi(0) = −VR TC /R1 CF . After a finite number of clock cycles, for instance, N (period T = N TC ), the integrator output is voi(N ) =
VR TC VR TC N(1) − N(0) R2 CF R1 CF
where N(1) and N(0) are the numbers of clock cycles for which the output values of D flip-flop are 1 and 0, respectively, within the period T and N = N(1) + N(0) . If N is sufficiently large, then the value of voi(N ) has to be less than or equal to the maximum possible change in integrator voltage per clock cycle voi(m) , where voi(m) = VR TC /(R1 , R2 )min CF
(3)
and (R1 , R2 )min is the minimum among R1 and R2 . Then N(0) VR TC N(1) 1 VR TC − . (4) ≤ CF R2 R1 CF (R1 , R2 )min On further simplification, we get N(1) R1 − N(0) R2 ≤ (R1 , R2 )max
where (R1 , R2 )max is the maximum of R1 and R2 . Substituting the values of R1 and R2 of a differential resistive sensor possessing linear characteristics, as given by (1) in (5), results in (R0 (1 ± kx)N(1) − R0 (1 ∓ kx)N(0) ) ≤ (R1 , R2 )max , leading to R0 1 N(1) − N(0) ± kxN ≤ (R1 , R2 )max . N N
(6)
For a very large value of N , the value of 1/N (R1 , R2 )max becomes small, and hence
N(0) − N(1) N(1) kx = =1−2 = 1 − 2y avg . N N (7) (N(1) /N ) is the average value y|avg of the bit stream y over the period N TC . Since the digital LPF-based circuit is designed to extract (1 − 2y|avg )—as mentioned earlier—its output is kx. Hence, for differential resistive sensors possessing linear characteristics, as given by (1), the proposed technique provides a linear digital output that is proportional to the quantity being sensed. Very rarely, differential resistive sensors possess inverse characteristics, as given by (2). It turns out that substituting the values of R1 and R2 , as given by (2) in (5), also results in (7). Thus, the proposed method provides a linear digital output that is proportional to the measurand, even if the differential resistive sensor follows an inverse relationship, as given in (2). The results of simulation studies and details of a prototype RDC built and tested using off-the-shelf components are given in the sequel. The errors introduced due to various circuit parameter variations are analyzed next. III. E RROR A NALYSIS AND D ISCUSSION It should be noted here that the proposed RDC is obtained by suitably converting the 1-b quantizer (Δ-modulator) in a conventional Σ–Δ ADC. Hence, the proposed method will necessarily possess noise shaping characteristics, bandwidth limitations, and uncertainties, as detailed in IEEE Std. 1241–2005 [17] and elsewhere [18]–[21]. Over and above the well-known and well-established uncertainties, the RDC will possess additional errors due to the modification itself. The possible errors that would arise due to the modification, such as introduction of switches and two reference voltages instead of one as in a conventional Σ–Δ ADC, are analyzed next. Ideal conditions are assumed while deriving (3), (5), and (6). In a practical case, errors will be introduced in the output due to the following factors: 1) difference in the magnitudes of the positive and negative dc reference voltages; 2) offset voltages of OA and OC; 3) on-resistances of the switches; 4) switch leakage currents; 5) op-amp bias current; and 6) stray capacitances. The following sections discuss in detail the effect of each parameter on the output. A. Effect of Mismatch in DC Reference Voltages
(5)
The magnitudes of dc reference voltages +VR and −VR are assumed to be equal in deriving (5). However, in practice, there
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will be a small mismatch between them, and hence, in general, | + VR | = | − VR |(1 ± β), where β is the factor indicating the extent of mismatch. In such a condition, (5) gets modified as (N(1) (1 ± β)R1 − N(0) R2 ) ≤ (R1 , R2 )max . Hence N(0) − N(1) ∓ βN(1) ±kx = N ± βN(1) ⎡ ⎤ N(0) − N(1) βN(1) 1
⎦ . =⎣ ∓ N N N 1 ± β (1) N
For (β(N(1) /N )) 1 and neglecting (β(N(1) /N ))2 and higher powers of (β(N(1) /N )), we get N(0) −N(1) βN(1) N(1) ∓ ±kx = 1∓β N N N = (1−2y|avg ) (1∓βy|avg )∓(βy|avg )±(βy|avg )2 . The resulting relative error εVR is shown at the bottom of the page. For full-scale reading, if y|avg → 1, then εVR = =
(1 − 2)(1 ∓ β) ∓ (β) ± (β)2 − (1 − 2) (1 − 2) (−1)(1 ∓ β) ∓ (β) ± (β)2 − (−1) = 2β + β 2 (−1)
resulting in the error due to mismatch in dc reference voltages as % εVR = (2β + β 2 ) 100.
(8)
For the prototype developed, β was found to be 4 × 10−5 , and the error in the output due to mismatch in dc reference voltages works out to be 0.008%. B. Effects of Offset Voltages of Op-Amp OA and Comparator OC If the op-amp OA has an offset voltage ±vos , then the voltages across the sensor resistances R1 and R2 become (+VR ∓ vos ) and (−VR ∓ vos ), respectively. This condition is equivalent to a mismatch of 2vos between the magnitudes of dc reference voltages +VR and −VR . Thus, by taking β = 2vos /VR , the ensuing error in the output can be computed using (8). For the prototype, op-amp OP07, which has a maximum offset voltage of 25 μV, was used, resulting in a worst-case error of 0.004%. The offset voltage of the comparator shifts its reference point by the same amount from zero. As long as the offset voltage of OC remains constant (comparator that has negligible offset drift
εVR =
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within one conversion period) during a complete conversion period, it has negligible effect on the final output. C. Effects of On-Resistance of the Switches In the proposed scheme, the on-resistance rON1 of switch S1 is in series with R1 , while the on-resistance rON2 of switch S2 is in series with R2 . It is equivalent to a change in the values of sensor resistances R1 and R2 with new values (R1 + rON1 ) and (R2 + rON2 ), respectively. In this condition, (5) gets modified as (N(1) R1 + N(1) rON1 − N(0) R2 − N(0) rON2 ) ≤ (R1 , R2 )max , and hence, we have rON1 −rON2 1 (1−2y|avg) = ±kx − . R0 +rON1 +rON2 1+ rON1R+r0 ON2 (9) Comparison of (7) and (9) indicates that the switch onresistances introduce a gain error and an offset in the output. If we employ identical switches for S1 and S2 , then rON1 ≈ rON2 , and the offset will be zero. The gain error can be made negligible by ensuring that R0 (rON1 + rON2 ). For the prototype, MAX4680 switches (rON = 1.25 Ω) were used, resulting in a gain error of −0.42% and an offset of 0.05% with R0 = 600 Ω. The gain error and the offset, if present, can be easily reduced by providing suitable compensation. In fact, this is the only significant factor contributing to the errors in the proposed RDC, and therefore, care must be taken to minimize this error. D. Effects of Switch Leakage Currents Leakage currents between nodes 1 and 2 of switches S1 and S2 flow from the dc reference sources to the circuit ground and hence do not charge or discharge CF . When S1 is at position 1, leakage current IL1 exists between nodes 2 and A. In this condition, the resistance between nodes A and 1 is rON1 . As rON R0 , a large portion of the leakage current IL1 flows to circuit ground via node 1, and a negligible amount—IL1 [rON1 /(rON1 + R1 )]—compared with the sensor current of (VR /R1 ), flows through R1 . Similar conditions are applicable for S2 . Thus, in a practical situation, switch leakage currents have negligible effect on the output. For the prototype, the leakage current was 5 nA, resulting in negligible error. E. Effect of Bias Current of the Op-Amp OA Depending on its polarity, the op-amp bias current (IB ) of OA charges the capacitor CF in a given direction throughout a typical conversion time. The bias current manifests as a change in the charging currents as ((VR /R1 ) ± IB ) and ((VR /R2 ) ∓ IB ) through the sensor resistances R1 and R2 , respectively.
(1 − 2y|avg ) (1 ∓ βy|avg ) ∓ (βy|avg ) ± (βy|avg )2 − (1 − 2y|avg ) (1 − 2y|avg )
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Fig. 2. Differential resistive sensor elements with possible stray capacitances. Nodes A and C are connected to S1 and S2 , respectively, while node B is connected to the inverting terminal of the op-amp OA, as shown in Fig. 1.
It can also be represented as an equivalent change in the dc reference voltage +VR . Thus, it is equivalent to a mismatch between reference voltages, and the ensuing worst-case fullscale error due to the bias current of the op-amp OA can be computed using (8) by substituting for β = (IB /VR )(R1 + R2 ) = 2(IB R0 /VR ). The effect can be made insignificant by selecting an op-amp with very low IB —satisfying the condition IB VR /R0 —to realize OA.
Fig. 3.
Simulation results for a sensor with linear characteristics.
Fig. 4.
Simulation results for a sensor possessing inverse characteristics.
F. Effect of Stray Capacitances In practice, it may well be that the sensor unit is far from the signal conditioning unit and that the electrical connections between these units are made using shielded cables. Distributed capacitances will exist between the live conductor of each cable and its grounded shield. This effect can be represented by lumped stray capacitances, as shown in Fig. 2. Stray capacitances CAG , CBG , and CCG exist from nodes A, B, and C, respectively, to ground. CAG charges to +VR when S1 is at position 2. Similarly, CCG charges to −VR when S2 is at position 1. Whenever S1 is switched to position 1 and S2 to position 2, the charge acquired by the corresponding capacitances CAG and CCG discharges to ground through the lowimpedance path offered by the switch on-resistance. As long as the time-constant rON1 CAG R1 CAG and rON1 CCG R2 CCG , the stray capacitances CAG and CCG will have negligible effect on the operation of the circuit. As node B is always at virtual ground, CBG will not charge or discharge during the operation of the circuit. IV. S IMULATION S TUDIES Before prototyping the circuit shown in Fig. 1, it was simulated using OrCAD PSpice (version 9.0). Since a model of the digital filter AD1556 was not available, the low-pass digital function of the AD15556 was realized by a switching and averaging technique. The resistance of the differential resistive sensor was varied in a range of +50% of its nominal value of 600 Ω, in steps of ±5%. To simulate the effect of the switch resistance (rON ), a resistor of 1.25 Ω was included in series with the sensor resistances. The output was sampled after the simulation was allowed to run for 200 ms to ensure that all transients die out. First, the resistances were varied linearly, as given by (1), and the output and error for this case are shown in Fig. 3. A similar simulation was run for a sensor with inverse characteristics of the form given by (2), and the results are shown in Fig. 4. The circuit was again simulated with the switch resistances suitably modified in order to determine the effect of mismatch in rON . It was found that the worst possible
error in the output for a mismatch of 100% was only 0.51%. Similarly, the magnitude of the reference voltages was altered to understand its effect on the output. A 1% mismatch in their magnitudes produced a maximum variation of 4.12% in the output. V. E XPERIMENTAL R ESULTS A prototype Σ–Δ RDC was built and tested in the laboratory. The reference voltage +VR was generated using the reference diode LM385-1.2 [22], which was buffered with a voltage follower (op-amp OP07) [23]. −VR was obtained with the help of a unity gain inverter realized with a second OP07. The magnitude of −VR was trimmed to obtain a match (up to five digits) between +VR and −VR . SPDT switches were realized with IC MAX4680 [24] (possessing low on-resistance rON = 1.25 Ω). A third OP07 served as the op-amp OA. The value of the feedback capacitor was chosen as 0.33 μF to limit the maximum change in the integrator voltage per clock cycle to be less than the slew rate of the OP07. An LM311 IC [25] served as the comparator (OC), and the CD4013 [26] was employed for the D flip-flop. To extract y|avg , the IC AD1556 was employed. The AD1556 [27] implements a finite-impulseresponse linear-phase equiripple LPF and a decimator. The modulator clock frequency was chosen to be 20 kHz. A suitable program was written and burned into a PIC16F877A microcontroller [28] to read the output y|avg from the AD1556, compute,
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MOHAN et al.: ANALYSIS OF A SIGMA–DELTA RDC FOR DIFFERENTIAL RESISTIVE SENSORS
Fig. 5. Output of D flip-flop (y) and integrator voltage voi , along with the clock signal recorded from the prototype.
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and the form of the final digital output is chosen so that the RDC provides a linear digital output that is proportional to the parameter being sensed by sensors possessing either linear or inverse characteristics and is hence applicable to both types of sensors without any change. The resolution required in applications involving differential resistive sensors seldom exceeds 16 b, which is easily achievable (the prototype built and tested had a resolution of 24 b) with the present technique. The conversion speed of few hundred samples per second to few tens of thousand samples per second that is achievable with the Σ–Δ converter topology is more than adequate for applications (distance and pressure sensing) concerning differential resistive sensors. The effects of various circuit parameters on the performance of the RDC are analyzed and found to be negligible or can be made so with proper selection of the circuit components. Simulation studies and experimental results obtained from a prototype built and tested establish the practicality of the proposed RDC. The worst-case error of the prototype was found to be less than ±0.15%. This type of RDC is best suited for micromechanical systems type of applications. R EFERENCES
Fig. 6.
Experimental results of the prototype Σ–Δ RDC.
and then display (1 − 2y|avg ) on a five-digit seven-segment display. A typical conversion time of the prototype Σ–Δ RDC was 40 ms. The prototype developed was tested with resistive sensors possessing linear as well as inverse characteristics. It was found to provide a linear digital output in both cases. Typical waveforms obtained from the prototype are shown in Fig. 5. To test the performance of the prototype RDC, transducer resistances were simulated using two precision decade resistance boxes from Otto Wolff, Germany, having a resolution of 1 Ω and an accuracy of ±0.01%. The nominal value of the resistances was selected as 600 Ω, and R1 and R2 were varied up to 300 Ω in steps of 6 Ω, to simulate a kx variation in the range of ±0.5, with increments of ±0.01. The output characteristic, along with the percentage relative error of the prototype, is shown in Fig. 6. The worst-case error was found to be less than ±0.15%. VI. C ONCLUSION An RDC that provides a direct digital output that is proportional to the parameter being sensed by a differential resistive sensor is presented. The topology of the RDC is obtained by incorporating the differential resistive sensor as an integral part of a first-order 1-b quantizer of a conventional Σ–Δ ADC. Hence, the proposed RDC has all the advantages and limitations of a typical Σ–Δ ADC. The quantizer is controlled suitably,
[1] E. O. Doebelin, Measurement Systems—Application and Design, 5th ed. New York: McGraw-Hill, 2004. [2] “Data sheet, sensor A201,” Flexiforce—The Leader in Standard and Custom OEM Force Sensing Solutions, Tekscan Inc., Boston, MA, Jan. 2007. [Online]. Available: http://www.tekscan.com/flexiforce.html [3] J. K. Gustafsson, “Analog–digital converter for a resistance bridge,” U.S. Patent 3 960 010, Jun. 1, 1976. [4] J. T. Adams, T. M. Tinsley, and P. L. Brown, “Analog-to-digital converter to be used along with a resistive sensor,” U.S. Patent 5 144 309, Sep. 1, 1992. [5] K. Mochizuki and K. Watanabe, “A relaxation-oscillator-based interface for high-accuracy ratiometric signal processing of differential-capacitance transducers,” IEEE Trans. Instrum. Meas., vol. 47, no. 1, pp. 11–14, Feb. 1998. [6] B. Wang, T. Kajita, T. Sun, and G. C. Temes, “High-accuracy circuits for on-chip capacitive ratio testing and sensor readout,” IEEE Trans. Instrum. Meas., vol. 47, no. 1, pp. 16–20, Feb. 1998. [7] R. Schreier and G. C. Temes, Understanding Delta–Sigma Data Converters. Hoboken, NJ: Wiley, 2005. [8] J. Haze, R. Vrba, L. Fujcik, J. Forejtek, P. Zavoral, M. Paulik, and L. Michaeli, “Band pass sigma–delta modulator for capacitive pressure sensor,” in Proc. IEEE IMTC, Warsaw, Poland, May 1–3, 2007, pp. 1–6. [9] T. Nohara, “Resistance-to-digital converter,” U.S. Patent 008 576 7A1, May 8, 2003. [10] K. Mochizuki and K. Watanabe, “A high-resolution, linear resistanceto-frequency converter,” IEEE Trans. Instrum. Meas., vol. 45, no. 3, pp. 761–764, Jun. 1996. [11] S. Kaliyugavaradhan, “A linear resistance-to-time converter with high resolution,” IEEE Trans. Instrum. Meas., vol. 49, no. 1, pp. 151–153, Feb. 2000. [12] J. Jordana and R. Palls-Areny, “A simple, efficient interface circuit for piezoresistive pressure sensors,” Sens. Actuators A, Phys., vol. 127, no. 1, pp. 69–73, Feb. 2006. [13] E. W. Owen, “An integrating analog-to-digital converter for differential transducers,” IEEE Trans. Instrum. Meas., vol. IM-28, no. 3, pp. 216–220, Sep. 1979. [14] V. J. Kumar, N. M. Mohan, and V. G. K. Murti, “Digital converter for push–pull type resistive transducers,” in Proc. IEEE IMTC, Ottawa, ON, Canada, May 17–19, 2005, pp. 422–425. [15] N. M. Mohan, B. George, and V. J. Kumar, “Dual-slope resistance-todigital converter,” in Proc. IEEE IMTC, Warsaw, Poland, May 1–3, 2007, pp. 1–5. [16] N. M. Mohan, B. George, and V. J. Kumar, “A sigma–delta resistance to digital converter suitable for differential resistive sensors,” in Proc. IEEE I2MTC, Victoria, BC, Canada, May 12–15, 2008, pp. 1159–1161. [17] IEEE Standards for Terminology and Test Methods for Analog-to-Digital Converters, 2001. IEEE Std. 1241-2000.
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[18] M. R. Gani, “Robust digital correction of analog errors in cascaded sigma delta converters,” J. Meas., vol. 37, no. 4, pp. 310–319, Jun. 2005. [19] D. W. Braudaway, “Uncertainty specification for data acquisition (DAQ) devices,” IEEE Trans. Instrum. Meas., vol. 55, no. 1, pp. 74–78, Feb. 2006. [20] F. Attivissimo, N. Giaquinto, and M. Savino, “Worst-case uncertainty measurement in ADC-based instruments,” Comput. Stand. Interfaces, vol. 29, no. 1, pp. 5–10, Jan. 2006. [21] A. Strak, “Timing uncertainty in sigma delta analog to digital converters,” Ph.D. dissertation, Royal Inst. Technol., Stockholm, Sweden, 2006. [22] “Data sheet, LM185-1.2/LM285-1.2/LM385-1.2,” Micropower Voltage Reference Diode, Nat. Semiconductor Corp., Santa Clara, CA, Jan. 2008. [Online]. Available: http://www.national.com/ds/LM/LM185-1.2.pdf [23] “Data sheet, OP-07,” Ultra Low Offset Voltage Operational Amplifier, Analog Devices Inc., Norwood, MA, Jan. 2006. [Online]. Available: http://www.analog.com/static/imported-files/data_sheets/OP07.pdf [24] “Data sheet, MAX4680,” 1.25 Ω dual SPST CMOS switches, Maxim Integr. Product Sunnyvale, CA, Jul. 1999. [Online]. Available: http:// datasheets.maxim-ic.com/en/ds/MAX4680-MAX4700.pdf [25] “Data sheet, LM311,” Voltage Comparator, Nat. Semiconductor Corp., Santa Clara, CA, Jan. 2004. [Online]. Available: http://www.national. com/ds/LM/LM111.pdf [26] “Data sheet, CD4013,” Dual D-Flip Flop, Nat. Semiconductor Corp., Santa Clara, CA, Feb. 1988. [Online]. Available: http://www.national. com/ds/CD/CD4013BM.pdf [27] “Data sheet, AD1555/AD1556,” 24-bit Σ–Δ ADC with low noise PGA, Analog Devices Inc., Norwood, MA, May 2002. [Online]. Available: http://www.analog.com/static/imported-files/data_sheets/ AD1555_1556.pdf [28] “Data sheet, PIC16F87XA,” 28/40/44-Pin Enhanced Flash Microcontrollers, Microchip Technol. Inc., Chandler, AZ, Jan. 2003. [Online]. Available: http://ww1.microchip.com/downloads/en/DeviceDoc/ 39582b.pdf
N. Madhu Mohan was born in Coimbatore, India, on March 21, 1970. He received the B.S. degree in electronics and communication engineering from the University of Calicut, Kerala, India, in 1991 and the M.S. degree (by research) from the Indian Institute of Technology Madras, Chennai, India, in 2003, where he is currently working toward the Ph.D. degree in biomedical instrumentation with the Measurements and Instrumentation Laboratory, Department of Electrical Engineering. His interests include measurements, biomedical instrumentation, and virtual instrumentation.
Boby George was born in Kannur, India, on April 30, 1977. He received the B.S. degree in electrical engineering from the Institution of Engineers, Kolkata, India, in 2001 and the M.S. and Ph.D. degrees in electrical engineering from the Indian Institute of Technology Madras, Chennai, India, in 2003 and 2007, respectively. He is currently a Postdoctoral Fellow with the University of Graz, Graz, Austria. His areas of interest include measurements, instrumentation, and virtual instrumentation.
V. Jagadeesh Kumar (M’94) was born in Madras, India, on July 21, 1956. He received the B.E. degree in electronics and telecommunication engineering from the University of Madras, Chennai, India, in 1978 and the M.Tech. and Ph.D. degrees in electrical engineering from the Indian Institute of Technology (IIT) Madras, Chennai, in 1980 and 1986, respectively. He is currently the Head of the Department of Electrical Engineering, IIT Madras, where he is with the Measurements and Instrumentation Laboratory. He was a BOYSCAST Fellow with King’s College, London, U.K., during 1987–1988 and a DAAD Fellow with the Technical University of Braunschweig, Braunschweig, Germany, in 1997. He was a Visiting Scientist with the Technical University of Aachen, Aachen, Germany, in 1999. He taught for a term at the Asian Institute of Technology, Bangkok, Thailand, in the summer of 1999. He has published more than 40 papers in international journals and presented more than 60 papers at various conferences. He is the holder of six patents. His teaching and research interests include measurements, instrumentation, and signal processing.
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