Analysis of Performance and Reliability Trade-Off ... - Semantic Scholar
Analysis of Performance and Reliability Trade-Off in Dummy Pattern Design for 32-nm Technology Aditya P. Karmarkar1, Xiaopeng Xu2, Victor Moroz2, Greg Rollins2 and Xiao Lin2 1 2 Synopsys (India) Private Limited, Synopsys, Inc., Hyderabad, Andhra Pradesh, India Mountain View, CA, USA Abstract Deep sub-micron technologies employ dummy metal fills in the interconnect layouts with adequate pre-CMP pattern density distribution to achieve post-CMP planarization. Dummy metal placement has a significant impact on interconnect parasitic parameters and it also alters the mechanical stresses in the interconnect structure. The effects of dummy placement on the parasitic parameters and the mechanical stresses are examined in this study. The impact of the dummy placement is found to be strongly correlated with the dummy fill pattern. Some patterns studied here result in improved interconnect parasitic parameters but lead to a deterioration in the local stress fields that are of reliability concern. Therefore, the dummy placement must be designed such that both performance and reliability are taken into consideration.
1. Introduction The current trends in the microelectronics industry require increased scaling and higher integration densities at each technology node. The performance and density requirements in deep sub-micron technologies call for a greater number of interconnect levels with increased complexity. Thus, interconnect parasitic effects assume a greater significance for technologies that employ complex interconnect layouts [1]. Moreover, advanced deep submicron technologies use multi-level copper (Cu) metallization embedded in low-permittivity (low-k) dielectrics to reduce interconnect parasitic effects and to improve the system performance. Cu/low-k interconnect systems pose significant manufacturability and yield challenges, especially during chemical-mechanical planarization (CMP) operations [2], [3]. Dummy metal fills are used in the interconnect layouts of highly integrated systems to enhance the CMP manufacturability and yield. Dummy metal fills with the pre-CMP pattern density distribution improve post-CMP planarization; thus enhancing the post-CMP topography [2], [3]. However, it is necessary to assess the effects of dummy placement because of its large impact on interconnect parasitic parameters [4], [5]. In addition, the dummy metal placement alters the local distribution of mechanical
stress and affects the back-end of the line (BEOL) reliability and yield [6]. Thus, in order to improve the system performance and yield, it is necessary to examine the impact of dummy metal placement on interconnect parasitic parameters as well as the mechanical stress. This paper examines the effects of dummy metal placement on the coupling capacitance between metal lines. The effects of dummy placement on the local distribution of mechanical stress in the interconnect structure are also studied. Here a number of dummy fill patterns are assessed for their impact on interconnect parasitic parameters as well as the mechanical stresses. This study provides an insight into the design trade-offs necessary to optimize the performance and the yield.
2. Numeric simulations Mechanical stress simulations are performed using an FEM based 3D simulator that can generate structures directly from the mask information in GDSII format and the process steps. The simulator employs advanced algorithms to generate the structures and solve the partial differential equations. The simulator can account for various sources of mechanical stress, for example, thermal mismatch, CMP, grain growth and packaging [7]. For this study, three-dimensional (3D) structures are generated for various layouts using the mask information in GDSII format and the process information. The complete structures are exposed to a thermal ramp to simulate the thermal mismatch stresses. The same 3D geometries are then used to assess the coupling capacitances between the metal lines. The 3D geometries are used in a simulator employing the finite volume method to solve the partial differential equations. The simulator accounts for various material parameters and determines the static capacitances and resistances in the 3D structure [8]. The coupling capacitance between various metal lines is then assessed for various dummy layouts. Figure 1 (A) shows the interconnect layout assessed in this study. Here, the metal line dimensions adhere to the 32 nm design guidelines and the minimum spacing between two metal lines is equal to the line width [9]. Dummy metal placement is carried out in the shaded area shown in Figure 1 (B) to achieve a metal density of ~39%, by area. Three different dummy fill patterns are
examined for their impact on the mechanical stress and interconnect parasitic parameters. Figure 2 (A) shows a dummy pattern with a regular arrangement of eighteen identical dummy blocks. Figure 2 (B) shows a dummy pattern with only two large dummies and Figure 2 (C) shows a dummy pattern with six dummies. The guidelines used to design these dummy fill patterns were described previously by Kahng and others [10]. The dummy patterns are designed such that the areal density of the metal in the desired area in the layout plane, i.e. the shaded area in Figure 1 (B), is the same in all three layouts. Due to the identical height, the total volume of these dummies is also the same in all three layouts. However, the total surface area outside the layout plane is different in all three layouts. Similarly, the distances from these sides surfaces to these of metal lines are also different.
capacitances between the metal lines. The entire structure is subjected to a thermal ramp from 250 C to 25 C to simulate the mechanical stresses in the low-k dielectric. The same structure is then used to determine the coupling capacitances. For the capacitance simulations, the metal lines on the first and the third level are biased at zero volts. On the second metal level, the dummy metal fills on the second are kept at a floating potential, lines 2 and 4 are biased at 1 volt and lines 1 and 3 are biased at zero volts. The material parameters shown in Table 1 are used to perform these simulations. These simulations provide an understanding of the impact of the dummy pattern on the mechanical stress in the dielectrics and the capacitance coupling between metal lines.
Figure 3: (A) 3D Structure; (B) Cross-section Table 1: Material parameters
Figure 1: (A) Interconnect layout; (B) Dummy fill region
Material
E (GPa)
Low-k Copper Silicon Nitride
9.5 111.5 162.0 190.0
0.3 0.343 0.28 0.27
LCTE (ppm/C) 20.0 17.7 3.05 3.2
k 2.3 11.9 7.5
Additionally, the effects of corner rounding on the mechanical stress and the coupling capacitance are also examined. Here, the structures are generated using layouts similar to those shown in Figure 1 and Figure 2, but with rounded corners for the metal lines and dummies. Analysis of the corner rounding effects provides an insight into the impact of process induced structure alteration on the mechanical stress and coupling capacitance. Figure 2: (A) Layout 1 - Regular dummy fill; (B) Layout 2 - Two large dummies; (C) Layout 3 - Six dummies The 3D interconnect structures used in this study are generated from the mask and process information. Figure 3 (A) shows the 3D structure that consists of three metal levels without any vias in between. The first and the third metal levels, as shown in Figure 3 (B), consist of regularly spaced metal lines that follow the 32 nm design guidelines. These metal lines are orthogonal to those on the second level. The metal structure on the second level is used to assess the mechanical stresses the coupling
3. Results and discussion 3.1. Dummy placement effects The mechanical stress in interconnect structures primarily depends on the mismatch between the coefficients of thermal expansion of different materials. The mechanical stress distribution also depends on the interconnect layout. Here, the mechanical stress is assessed after a thermal ramp from 250 C to 25 C. Mechanical stress simulations are performed with
boundary conditions set to restrict displacements at the minima x, y and z axes. Displacements are also restricted at the maxima of x and y axes and allowed at the maxima of z axis. These boundary conditions represent an infinite layout with symmetries in the xy plane. Figure 4 shows the first principal stress in the low-k dielectric for various dummy fill patterns. Using the guidelines described by previous researchers, these dummy fill patterns are designed such that the areal density of the metal is conserved [10]. Here, the mechanical stress is examined along a plane normal to the z-axis and situated at the midpoint of the metal structure on the second level of the 3D structure.
principal stress in the low-k dielectric for a layout with six dummies. It can be observed in Figure 4 (C) that the placement of two large dummies leads to the formation of areas of large stress concentrations, or stress hotspots. These stress hotspots may cause cracks or voids in the low-k dielectric and decrease the low-k reliability. The reliability degradation due to stress hotspots assumes greater significance in case of ultra-low-k dielectrics due to the porosity introduced into the material [11]. Figure 4 (D) shows the 1st principal stress in the low-k dielectric for a layout with six dummies, where the stress distribution does not show formation of any large stress hotspots. Here, the lack of large stress hotspots results in enhanced dielectric reliability and manufacturability. The results discussed so far clearly indicate that although the placement of dummy fills is necessary to improve the manufacturability, dummy fill pattern must be designed carefully to avoid f the formation of stress hotspots and consequent reliability loss.
Figure 5: Coupling capacitance (aF) between line 2 and line 3 for various layouts
Figure 4: First principal stress (MPa) in low-k for - (A) no dummies; (B) regular dummy fill; (C) two large dummies; (D) six dummies Figure 4 (A) shows the 1st principal stress in the low-k dielectric for a layout without any dummy fills. Figure 4 (B) shows the 1st principal stress in the low-k dielectric for a layout with a regular dummy fill pattern. This dummy pattern is designed without following any guidelines. It can be seen from these figures that the placement of a regular dummy pattern leads to a significant increase in the mechanicals stress in the low-k dielectric between metals. Figure 4 (C) shows the 1st principal stress in the low-k dielectric for a layout with two large dummies and Figure 4 (D) shows the 1st
The capacitance coupling between the metal lines is determined from the capacitance simulations. The capacitance simulations are performed using the 3D structure and bias conditions described earlier. Figure 5 shows the coupling capacitance between line 2 and line 3 for various layouts studied here. This figure shows that the placement of a regular dummy pattern between line 2 and line 3 increases the capacitance between the lines by ~78% leading to higher parasitic losses. The capacitance coupling can be reduced by modifying the dummy pattern. It can be observed from Figure 5 that the placement of two large dummies between line 2 and line 3 increases the coupling capacitance by ~75% and the placement of six dummies increases the coupling capacitance by ~47%. These results indicate that dummy metal fills increase the coupling capacitance. However, the increase in the coupling capacitance depends on the
dummy fill pattern and it can be optimized using proper dummy pattern design. The results discussed here show that dummy metal fills lead to higher parasitic losses. Therefore, the dummy fill pattern must be designed such that the parasitic losses are minimized. Improper design of the dummy fill pattern may lead to higher mechanical stresses and create stress hotspots in the interconnect structure. Hence, the dummy fill pattern must be designed to minimize the formation of high-stress regions and stress hotspots. These effects must be understood and balanced in order to determine the design trade-offs necessary to optimize both performance and reliability.
3.2. Corner rounding effects In case of deep sub-micron technologies, optical proximity effects lead to the rounding of sharp features in the interconnect structures. For example, sharp metal corners in a mask may become rounded in the final structure due to optical proximity effects. These effects are studied here by creating rounded metal corners in the mask file used to generate the 3D structure. The impact of corner rounding on the mechanical stress and the parasitic parameters is studied for a layout that contains a regular dummy pattern and a layout that contains six dummies. The layouts and the numeric simulations in this study are similar to those described earlier.
Figure 6: First principal stress (MPa) in layout with - (A) regular dummies; (B) regular dummies and rounded corners; (C) six dummies; (D) six dummies and rounded corners Figure 6 (A) shows the first principal stress in the lowk dielectric for a regular dummy pattern without corner rounding and Figure 6 (B) shows the first principal stress in the low-k dielectric for a regular dummy pattern with corner rounding. Similarly, Figure 6 (C) shows the first principal stress in the low-k dielectric for a pattern consisting of six dummies and without corner rounding and Figure 6 (D) shows the first principal stress in the low-k dielectric for a pattern consisting of six dummies and with corner rounding. It is evident from this figure that the mechanical stress in the low-k dielectric does not show an appreciable change after for structures with rounded corners. These results show that the structural alteration due to optical proximity effects have minimal impact on the dielectric mechanical stress, and hence, its reliability.
without any dummies, for different layouts with and without corner rounding. Figure 8 shows that the effect of the dummy fill pattern on the coupling capacitance does not change with corner rounding. It is evident from these results that the parasitic parameters of a layout can be accurately predicted even without considering the process induced geometry variations, i.e. corner rounding. These results have significant implications for interconnect parasitic analysis, where large and complex layouts can be assessed rather accurately without employing substantial computing resources.
4. Summary Figure 7: Coupling capacitance (aF) between line 2 and line 3 for different layouts with and without corner rounding
This work clearly indicates that although the dummy metal fills improve manufacturability and yield, they lead to a significant increase in the parasitic losses. Therefore, the dummy metal pattern must be designed such that the parasitic losses are minimized. Moreover, dummy fill placement results in higher mechanical stresses and stress hot-spots in the low-k dielectric. These high mechanical stresses and the stress hot-spots may result in dielectric failures and yield loss, especially in ultra low-k dielectrics. Hence, the dummy metal pattern must be designed to avoid the formation of regions of high stress concentration and stress hotspots. It is also observed that process induced structural alteration has a minor impact on the dielectric stress, and it has a small impact on the coupling capacitances. All of these effects must be understood and balanced in order to determine the design trade-offs necessary to optimize performance and reliability.
5. References Figure 8: Effect of corner rounding on various layouts Capacitance simulations are performed on the same structures to assess the impact of corner rounding on the coupling capacitance between line 2 and line 3. The methodology used here is the same as that described previously. Figure 7 shows the change in the coupling capacitance with corner rounding for a layout with regular dummy pattern and for a layout with six dummies. It is observed from Figure 7 that, for a layout with regular dummy pattern the coupling capacitance decreases by ~10.5% due to corner rounding. For a pattern with six dummies, the coupling capacitance decreases by ~5.5% after corner rounding. These results show that corner rounding has a small effect on the parasitic parameters. It is also observed that corner rounding has a bigger impact on layout with a larger number of dummies. Figure 8 shows the effect of corner rounding on all the layouts. Here, the coupling capacitance between line 2 and line 3 is determined for different layouts with and without corner rounding. Figure 8 shows the coupling capacitance, normalized to the capacitance for a layout
[1] W. H. Kao, C.-Y. Lo, M. Basel and R. Singh,
“Parasitic extraction: Current State of the Art and Future Trends,” Proceedings of the IEEE, vol. 89, no. 5, pp 729 – 739, May 2001. [2] D. Sinha, J. Luo, S. Rajagopalan, S. Batterywala, N. V. Shenoy and H. Zhou, “Impact of Modern Process Technologies on the Electrical Parameters of Interconnects,” Proceedings of the 20th International Conference on VLSI Design 2007 (VLSID’07), pp. 875 – 880, Jan. 2007. [3] R. Tian, D. F. Wong and R. Boone, “Model-Based Dummy Feature Placement for Oxide ChemicalMechanical Polishing Manufacturability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 7, pp. 902 – 910, Jul. 2001. [4] N. S. Nagaraj, T. Bonifield, A. Singh, F. Cano, U. Narasimha, M. Kulkarni, P. Balsara and C. Cantrell, “Benchmarks for Interconnect Parasitic Resistance and Capacitance, Proceedings of the 4th International
[5]
[6]
[7] [8] [9] [10]
[11]
Symposium on Quality Electronic Design 2003 (ISQED’03), pp. 163 – 168, Mar. 2003. A. Kurokawa, T. Kanamoto, T. Ibe, A. Kasebe, C. W. Fong, T. Kage, Y. Inoue and H. Masuda, “Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills,” Proceedings of the 6th International Symposium on Quality Electronic Design 2005 (ISQED’05), pp. 586 – 591, Mar. 2005. X. Xu, G. Rollins, X. Lin and D. Pramanik, “Modeling Process Impact on Cu/Low-k Interconnect Performance and Reliability,” Proceedings of the 2006 16th Biennial University/Government/Industry Microelectronics Symposium 2006, pp. 65 – 70, Jun. 2006. Fammos TX User Guide and Fammos TX Reference Manual, Synopsys, Inc., September 2008. Raphael® User Guide and Raphael® Reference Manual, Synopsys, Inc., June 2008. International Technology Roadmap for Semiconductors, 2007, ITRS 2007. A. B. Kahng, K. Samadi and P. Sharma, “Study of Floating Fill Impact on Interconnect Capacitance,” Proceedings of the 7th International Symposium on Quality interconnect Design 2006 (ISQED’06), pp. 691 – 696. Mar. 2006. D. Ryuzaki, H. Sakurai, K. Abe, K. Takeda, and H. Fukuda, "Enhanced Dielectric-Constant Reliability of Low-k Porous Organosilicate Glass (k = 2.3) for 45nm-Generation Cu Interconnects," IEEE International Electron Devices Meeting (IEDM) 2004, IEDM Technical Digest, pp. 949 - 952, Dec. 2004.
1. Introduction The current trends in the microelectronics industry require increased scaling and higher integration densities at each technology node. The performance and density requirements in deep sub-micron technologies call for a greater number of interconnect levels with increased complexity. Thus, interconnect parasitic effects assume a greater significance for technologies that employ complex interconnect layouts [1]. Moreover, advanced deep submicron technologies use multi-level copper (Cu) metallization embedded in low-permittivity (low-k) dielectrics to reduce interconnect parasitic effects and to improve the system performance. Cu/low-k interconnect systems pose significant manufacturability and yield challenges, especially during chemical-mechanical planarization (CMP) operations [2], [3]. Dummy metal fills are used in the interconnect layouts of highly integrated systems to enhance the CMP manufacturability and yield. Dummy metal fills with the pre-CMP pattern density distribution improve post-CMP planarization; thus enhancing the post-CMP topography [2], [3]. However, it is necessary to assess the effects of dummy placement because of its large impact on interconnect parasitic parameters [4], [5]. In addition, the dummy metal placement alters the local distribution of mechanical
stress and affects the back-end of the line (BEOL) reliability and yield [6]. Thus, in order to improve the system performance and yield, it is necessary to examine the impact of dummy metal placement on interconnect parasitic parameters as well as the mechanical stress. This paper examines the effects of dummy metal placement on the coupling capacitance between metal lines. The effects of dummy placement on the local distribution of mechanical stress in the interconnect structure are also studied. Here a number of dummy fill patterns are assessed for their impact on interconnect parasitic parameters as well as the mechanical stresses. This study provides an insight into the design trade-offs necessary to optimize the performance and the yield.
2. Numeric simulations Mechanical stress simulations are performed using an FEM based 3D simulator that can generate structures directly from the mask information in GDSII format and the process steps. The simulator employs advanced algorithms to generate the structures and solve the partial differential equations. The simulator can account for various sources of mechanical stress, for example, thermal mismatch, CMP, grain growth and packaging [7]. For this study, three-dimensional (3D) structures are generated for various layouts using the mask information in GDSII format and the process information. The complete structures are exposed to a thermal ramp to simulate the thermal mismatch stresses. The same 3D geometries are then used to assess the coupling capacitances between the metal lines. The 3D geometries are used in a simulator employing the finite volume method to solve the partial differential equations. The simulator accounts for various material parameters and determines the static capacitances and resistances in the 3D structure [8]. The coupling capacitance between various metal lines is then assessed for various dummy layouts. Figure 1 (A) shows the interconnect layout assessed in this study. Here, the metal line dimensions adhere to the 32 nm design guidelines and the minimum spacing between two metal lines is equal to the line width [9]. Dummy metal placement is carried out in the shaded area shown in Figure 1 (B) to achieve a metal density of ~39%, by area. Three different dummy fill patterns are
examined for their impact on the mechanical stress and interconnect parasitic parameters. Figure 2 (A) shows a dummy pattern with a regular arrangement of eighteen identical dummy blocks. Figure 2 (B) shows a dummy pattern with only two large dummies and Figure 2 (C) shows a dummy pattern with six dummies. The guidelines used to design these dummy fill patterns were described previously by Kahng and others [10]. The dummy patterns are designed such that the areal density of the metal in the desired area in the layout plane, i.e. the shaded area in Figure 1 (B), is the same in all three layouts. Due to the identical height, the total volume of these dummies is also the same in all three layouts. However, the total surface area outside the layout plane is different in all three layouts. Similarly, the distances from these sides surfaces to these of metal lines are also different.
capacitances between the metal lines. The entire structure is subjected to a thermal ramp from 250 C to 25 C to simulate the mechanical stresses in the low-k dielectric. The same structure is then used to determine the coupling capacitances. For the capacitance simulations, the metal lines on the first and the third level are biased at zero volts. On the second metal level, the dummy metal fills on the second are kept at a floating potential, lines 2 and 4 are biased at 1 volt and lines 1 and 3 are biased at zero volts. The material parameters shown in Table 1 are used to perform these simulations. These simulations provide an understanding of the impact of the dummy pattern on the mechanical stress in the dielectrics and the capacitance coupling between metal lines.
Figure 3: (A) 3D Structure; (B) Cross-section Table 1: Material parameters
Figure 1: (A) Interconnect layout; (B) Dummy fill region
Material
E (GPa)
Low-k Copper Silicon Nitride
9.5 111.5 162.0 190.0
0.3 0.343 0.28 0.27
LCTE (ppm/C) 20.0 17.7 3.05 3.2
k 2.3 11.9 7.5
Additionally, the effects of corner rounding on the mechanical stress and the coupling capacitance are also examined. Here, the structures are generated using layouts similar to those shown in Figure 1 and Figure 2, but with rounded corners for the metal lines and dummies. Analysis of the corner rounding effects provides an insight into the impact of process induced structure alteration on the mechanical stress and coupling capacitance. Figure 2: (A) Layout 1 - Regular dummy fill; (B) Layout 2 - Two large dummies; (C) Layout 3 - Six dummies The 3D interconnect structures used in this study are generated from the mask and process information. Figure 3 (A) shows the 3D structure that consists of three metal levels without any vias in between. The first and the third metal levels, as shown in Figure 3 (B), consist of regularly spaced metal lines that follow the 32 nm design guidelines. These metal lines are orthogonal to those on the second level. The metal structure on the second level is used to assess the mechanical stresses the coupling
3. Results and discussion 3.1. Dummy placement effects The mechanical stress in interconnect structures primarily depends on the mismatch between the coefficients of thermal expansion of different materials. The mechanical stress distribution also depends on the interconnect layout. Here, the mechanical stress is assessed after a thermal ramp from 250 C to 25 C. Mechanical stress simulations are performed with
boundary conditions set to restrict displacements at the minima x, y and z axes. Displacements are also restricted at the maxima of x and y axes and allowed at the maxima of z axis. These boundary conditions represent an infinite layout with symmetries in the xy plane. Figure 4 shows the first principal stress in the low-k dielectric for various dummy fill patterns. Using the guidelines described by previous researchers, these dummy fill patterns are designed such that the areal density of the metal is conserved [10]. Here, the mechanical stress is examined along a plane normal to the z-axis and situated at the midpoint of the metal structure on the second level of the 3D structure.
principal stress in the low-k dielectric for a layout with six dummies. It can be observed in Figure 4 (C) that the placement of two large dummies leads to the formation of areas of large stress concentrations, or stress hotspots. These stress hotspots may cause cracks or voids in the low-k dielectric and decrease the low-k reliability. The reliability degradation due to stress hotspots assumes greater significance in case of ultra-low-k dielectrics due to the porosity introduced into the material [11]. Figure 4 (D) shows the 1st principal stress in the low-k dielectric for a layout with six dummies, where the stress distribution does not show formation of any large stress hotspots. Here, the lack of large stress hotspots results in enhanced dielectric reliability and manufacturability. The results discussed so far clearly indicate that although the placement of dummy fills is necessary to improve the manufacturability, dummy fill pattern must be designed carefully to avoid f the formation of stress hotspots and consequent reliability loss.
Figure 5: Coupling capacitance (aF) between line 2 and line 3 for various layouts
Figure 4: First principal stress (MPa) in low-k for - (A) no dummies; (B) regular dummy fill; (C) two large dummies; (D) six dummies Figure 4 (A) shows the 1st principal stress in the low-k dielectric for a layout without any dummy fills. Figure 4 (B) shows the 1st principal stress in the low-k dielectric for a layout with a regular dummy fill pattern. This dummy pattern is designed without following any guidelines. It can be seen from these figures that the placement of a regular dummy pattern leads to a significant increase in the mechanicals stress in the low-k dielectric between metals. Figure 4 (C) shows the 1st principal stress in the low-k dielectric for a layout with two large dummies and Figure 4 (D) shows the 1st
The capacitance coupling between the metal lines is determined from the capacitance simulations. The capacitance simulations are performed using the 3D structure and bias conditions described earlier. Figure 5 shows the coupling capacitance between line 2 and line 3 for various layouts studied here. This figure shows that the placement of a regular dummy pattern between line 2 and line 3 increases the capacitance between the lines by ~78% leading to higher parasitic losses. The capacitance coupling can be reduced by modifying the dummy pattern. It can be observed from Figure 5 that the placement of two large dummies between line 2 and line 3 increases the coupling capacitance by ~75% and the placement of six dummies increases the coupling capacitance by ~47%. These results indicate that dummy metal fills increase the coupling capacitance. However, the increase in the coupling capacitance depends on the
dummy fill pattern and it can be optimized using proper dummy pattern design. The results discussed here show that dummy metal fills lead to higher parasitic losses. Therefore, the dummy fill pattern must be designed such that the parasitic losses are minimized. Improper design of the dummy fill pattern may lead to higher mechanical stresses and create stress hotspots in the interconnect structure. Hence, the dummy fill pattern must be designed to minimize the formation of high-stress regions and stress hotspots. These effects must be understood and balanced in order to determine the design trade-offs necessary to optimize both performance and reliability.
3.2. Corner rounding effects In case of deep sub-micron technologies, optical proximity effects lead to the rounding of sharp features in the interconnect structures. For example, sharp metal corners in a mask may become rounded in the final structure due to optical proximity effects. These effects are studied here by creating rounded metal corners in the mask file used to generate the 3D structure. The impact of corner rounding on the mechanical stress and the parasitic parameters is studied for a layout that contains a regular dummy pattern and a layout that contains six dummies. The layouts and the numeric simulations in this study are similar to those described earlier.
Figure 6: First principal stress (MPa) in layout with - (A) regular dummies; (B) regular dummies and rounded corners; (C) six dummies; (D) six dummies and rounded corners Figure 6 (A) shows the first principal stress in the lowk dielectric for a regular dummy pattern without corner rounding and Figure 6 (B) shows the first principal stress in the low-k dielectric for a regular dummy pattern with corner rounding. Similarly, Figure 6 (C) shows the first principal stress in the low-k dielectric for a pattern consisting of six dummies and without corner rounding and Figure 6 (D) shows the first principal stress in the low-k dielectric for a pattern consisting of six dummies and with corner rounding. It is evident from this figure that the mechanical stress in the low-k dielectric does not show an appreciable change after for structures with rounded corners. These results show that the structural alteration due to optical proximity effects have minimal impact on the dielectric mechanical stress, and hence, its reliability.
without any dummies, for different layouts with and without corner rounding. Figure 8 shows that the effect of the dummy fill pattern on the coupling capacitance does not change with corner rounding. It is evident from these results that the parasitic parameters of a layout can be accurately predicted even without considering the process induced geometry variations, i.e. corner rounding. These results have significant implications for interconnect parasitic analysis, where large and complex layouts can be assessed rather accurately without employing substantial computing resources.
4. Summary Figure 7: Coupling capacitance (aF) between line 2 and line 3 for different layouts with and without corner rounding
This work clearly indicates that although the dummy metal fills improve manufacturability and yield, they lead to a significant increase in the parasitic losses. Therefore, the dummy metal pattern must be designed such that the parasitic losses are minimized. Moreover, dummy fill placement results in higher mechanical stresses and stress hot-spots in the low-k dielectric. These high mechanical stresses and the stress hot-spots may result in dielectric failures and yield loss, especially in ultra low-k dielectrics. Hence, the dummy metal pattern must be designed to avoid the formation of regions of high stress concentration and stress hotspots. It is also observed that process induced structural alteration has a minor impact on the dielectric stress, and it has a small impact on the coupling capacitances. All of these effects must be understood and balanced in order to determine the design trade-offs necessary to optimize performance and reliability.
5. References Figure 8: Effect of corner rounding on various layouts Capacitance simulations are performed on the same structures to assess the impact of corner rounding on the coupling capacitance between line 2 and line 3. The methodology used here is the same as that described previously. Figure 7 shows the change in the coupling capacitance with corner rounding for a layout with regular dummy pattern and for a layout with six dummies. It is observed from Figure 7 that, for a layout with regular dummy pattern the coupling capacitance decreases by ~10.5% due to corner rounding. For a pattern with six dummies, the coupling capacitance decreases by ~5.5% after corner rounding. These results show that corner rounding has a small effect on the parasitic parameters. It is also observed that corner rounding has a bigger impact on layout with a larger number of dummies. Figure 8 shows the effect of corner rounding on all the layouts. Here, the coupling capacitance between line 2 and line 3 is determined for different layouts with and without corner rounding. Figure 8 shows the coupling capacitance, normalized to the capacitance for a layout
[1] W. H. Kao, C.-Y. Lo, M. Basel and R. Singh,
“Parasitic extraction: Current State of the Art and Future Trends,” Proceedings of the IEEE, vol. 89, no. 5, pp 729 – 739, May 2001. [2] D. Sinha, J. Luo, S. Rajagopalan, S. Batterywala, N. V. Shenoy and H. Zhou, “Impact of Modern Process Technologies on the Electrical Parameters of Interconnects,” Proceedings of the 20th International Conference on VLSI Design 2007 (VLSID’07), pp. 875 – 880, Jan. 2007. [3] R. Tian, D. F. Wong and R. Boone, “Model-Based Dummy Feature Placement for Oxide ChemicalMechanical Polishing Manufacturability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 7, pp. 902 – 910, Jul. 2001. [4] N. S. Nagaraj, T. Bonifield, A. Singh, F. Cano, U. Narasimha, M. Kulkarni, P. Balsara and C. Cantrell, “Benchmarks for Interconnect Parasitic Resistance and Capacitance, Proceedings of the 4th International
[5]
[6]
[7] [8] [9] [10]
[11]
Symposium on Quality Electronic Design 2003 (ISQED’03), pp. 163 – 168, Mar. 2003. A. Kurokawa, T. Kanamoto, T. Ibe, A. Kasebe, C. W. Fong, T. Kage, Y. Inoue and H. Masuda, “Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills,” Proceedings of the 6th International Symposium on Quality Electronic Design 2005 (ISQED’05), pp. 586 – 591, Mar. 2005. X. Xu, G. Rollins, X. Lin and D. Pramanik, “Modeling Process Impact on Cu/Low-k Interconnect Performance and Reliability,” Proceedings of the 2006 16th Biennial University/Government/Industry Microelectronics Symposium 2006, pp. 65 – 70, Jun. 2006. Fammos TX User Guide and Fammos TX Reference Manual, Synopsys, Inc., September 2008. Raphael® User Guide and Raphael® Reference Manual, Synopsys, Inc., June 2008. International Technology Roadmap for Semiconductors, 2007, ITRS 2007. A. B. Kahng, K. Samadi and P. Sharma, “Study of Floating Fill Impact on Interconnect Capacitance,” Proceedings of the 7th International Symposium on Quality interconnect Design 2006 (ISQED’06), pp. 691 – 696. Mar. 2006. D. Ryuzaki, H. Sakurai, K. Abe, K. Takeda, and H. Fukuda, "Enhanced Dielectric-Constant Reliability of Low-k Porous Organosilicate Glass (k = 2.3) for 45nm-Generation Cu Interconnects," IEEE International Electron Devices Meeting (IEDM) 2004, IEDM Technical Digest, pp. 949 - 952, Dec. 2004.
