APPLICATION OF GROUP DELAY EQUALISATION IN TESTING ...
APPLICATION OF GROUP DELAY EQUALISATION IN TESTING FULLY-BALANCED OTA-C FILTERS R. Wilcock and B. M. Al-Hashimi Electronic Systems Design, Department of Electronics and Computer Science, University of Southampton, UK. {rw01r, bmah}@ecs.soton.ac.uk. ABSTRACT This paper proposes a new BIST structural testing methodology for fully-balanced OTA-C filters. The methodology is based on using a simple group-delay equaliser to emulate the filter function; any discrepancies resulting from comparing the filter and equaliser outputs indicates a faulty circuit. The test circuitry is designed using detailed analysis of the possible faults and their effects on the filter output. This ensures a high fault coverage and minimisation of test accuracy dependence on manufacturing process variations. Furthermore, the equaliser circuitry requires only a single low-precision capacitor and the test stimulus frequency does not need to be exact. Simulation, has shown that up to 99% fault coverage is possible when the proposed methodology is applied to a 4.5MHz Chebyshev low pass filter. From actual layout, the estimated test circuitry area overhead is 20% which compares well with recently reported results.
1. INTRODUCTION Filters are important signal processing building blocks in mixedsignal integrated circuits (ICs). Operational transconductance amplifier and capacitor (OTA-C) continuous-time filters have been shown experimentally to perform well in low frequency [1] and high frequency [2-3] applications. Unlike switched capacitor (SC) filters, OTA-C circuits do not suffer from switching noise problems and the necessity for pre and post filtering. For these reasons OTA-C filters are becoming the preferred choice for filtering problems in mixed-signal ICs. There is a danger in mixed-signal ICs that digital switching signals will be injected into the analogue circuitry through chip parasitics. To combat this problem, it is usual practice to build differential, rather than single-ended, circuitry. A fully balanced OTA-C filter design [4] goes further, ensuring a completely symmetrical layout such that parasitic injections will couple perfectly equally into both the signal paths, thus appearing as a common mode signal. Integrated filters are subject to manufacturing defects, and various design-for-test (DFT) techniques have been proposed. Built-in-self-test (BIST) circuitry aims to reduce test rig costs by moving stimulus generation and observation onto the IC, eliminating the need for off-chip interfacing and allowing the device to be tested many times during manufacture [5]. With the increase in silicon integration capacity, and the emergence of systems-on-chip (SoC), BIST is likely to provide the best DFT option [6] for testing complex ICs, including mixed-signal chips. Numerous BIST techniques for analogue filters have been reported [7 - 9] but despite all the work carried out, researchers are still looking for more efficient methods. The aim of this
paper is to describe a new BIST structural testing methodology for fully-balanced OTA-C filters. To the best of our knowledge, this paper not only shows for the first time how group-delay equalisation can be used in this context but also reports for the first time a test methodology which has been specifically developed for fully-balanced OTA-C filters, unlike [8]. The methodology is developed based on a thorough analysis of all possible short and open faults which may occur in the filter, resulting in a test accuracy less affected by manufacturing process variations. Furthermore, the proposed test methodology is independent of the filter under test (FUT) design method, unlike previous work [7].
2. PROPOSED METHODOLOGY The block diagram of the proposed BIST method is shown in Fig. 1. In normal filter operation, test mode is not selected so the switches are set to disconnect the testing circuitry. In test mode, the test stimulus signal from the on-chip oscillator is applied to both the filter and equaliser circuit, the latter being designed to match the filter delay at the test frequency. In the case of a faultfree filter, the filter and equaliser output waveforms will have the same amplitude and delay at the test frequency, however, in the case of a faulty filter, the outputs will be different. The analysis block determines and amplifies the difference between the filter output and the equaliser output. Normally, therefore, the analysis block output will be negligible but in the case of a faulty filter, its output will be larger, depending to what extent the fault has affected the filter output. If the analysis block output comes outside of a predefined tolerance window the window detector outputs will change and the output evaluation block gives a signal at the test output pin indicating that the filter is faulty, as will be shown in Section 7.
3. FILTER DESIGN th
A 5 order low pass Chebyshev filter was chosen for the CUT, in order to compare with recent work, specifications for which are: passband of 0 ≤ fc ≤ 4.5MHz; passband ripple of 0.5dB; stopband of 8MHz ≤ fs and stopband attenuation of 45dB. An initial LC ladder prototype was converted to a fully balanced OTA-C filter using well developed techniques [4]. To implement the filter at transistor level, the fully-balanced OTA of Fig. 2 was chosen, mainly because of its high bandwidth, good linearity, and low number of transistors [10]. The completed filter design is shown in the upper half of Fig. 3 using standard symbols to denote the transistor level OTA used. A gain stage was added to compensate for the 6dB insertion loss experienced by all equally terminated LC ladder filters and an additional 2.3dB loss associated with the non-ideal effects of the transistor level OTA.
Fully Balanced Filter
Differential Inputs
Differential Outputs
Test Mode Testing Circuitry
Analysis Window Detector
Fully Balanced Equaliser Network
On-Chip Oscillator
Output Evaluation
Test Output
Fig. 1. Block diagram of the proposed testing method Table 1. Fault list for the OTA of Fig. 2.
M1
M2
M5
M7
M9
M11
M3
M6
M8
M10
M12
No. 1 2 3 4 5
Fault (shorts): Vin+ shorted to Iout+ Vin+ shorted to IoutVin- shorted to Iout+ Vin- shorted to IoutIout+ shorted to Iout-
M4
Fig. 2. Fully balanced OTA for use in filter design [10].
4. TEST SIGNAL CHOICE The presented test method uses a single frequency sinusoidal test stimulus. On-chip OTA-C oscillators are difficult to design for low frequencies [11] but the equaliser network will not accurately match the delay of the filter at frequencies above or near the filter cutoff point, fc. With these considerations in mind, a test stimulus in the filter and equaliser passband of frequency 0.01fc was chosen, which allows the test signal frequency to be fairly inaccurate without altering test efficiency. For the Chebychev filter designed in Section 3, the test frequency is therefore 45kHz. A test signal amplitude of 1V p-p was chosen as this represents typical filter operating conditions.
5. FILTER FAULT MODELS To derive a successful structural testing methodology, it is essential to first understand what possible structural faults could arise in the circuit under test and the affects they would have. Without this analysis, the fault coverage of a proposed test method is purely speculative. A structural fault list, shown in Table 1, has been built representing all the catastrophic short and open faults which could occur in the fully balanced OTA of Fig. 2. Each fault was individually implemented on every filter OTA in turn and a simulation run in each case using the test signal described in Section 4. It was then possible to summarise the main affects faults had on the filter output. It was found that with the specified test signal, all detrimental faults changed the filter output in some way by at least 200mV. Furthermore, the changes were typically in one of three ways: 32% of detrimental faults were found to affect mostly the amplitude of the filter output, 34% introduced a positive offset and 34% introduced a negative offset. These findings have allowed efficient test circuitry to be designed to achieve a high fault coverage.
No. 6 7 8 9 10 11
Fault (opens): Open gate, M1 Open drain, M2 Open source, M4 Open gate, M5 Open source, M6 Open drain, M7
6. TEST CIRCUITRY DESIGN 6.1 Equaliser design It has been found that a 1st-order group delay equaliser is sufficient to test most practical filters using the new method. The chosen equaliser circuit can be seen in the lower half of Fig. 3. Knowledge of the filter DC group delay, τ(s), and use of Equ. 1 allows calculation of the equaliser capacitance, C, given that the OTAs used are identical to those used in the filter. To avoid confusion later, it is worth mentioning now that the phase equaliser designed in this Section introduces an inversion into the signal path. This is exploited in Section 6.2 to allow efficient design of the analysis block.
τ (s) =
− dϕ (ω ) 2C = dω gm
(1)
6.2 Analysis block The analysis block, shown in Fig. 3, compares the differential filter and equaliser output signals, amplifying the difference. The filter and equaliser outputs are connected to two simple transconductance elements (TE’s), which convert the differential voltages into single-ended currents. These currents flow into a common node connected to a grounded resistor. If the filter is fault-free then the filter and equaliser outputs will be identical, although opposite in sign as discussed in Section 6.1. Equal currents will flow into and out of the grounded resistor and a very small analysis block output will result. If the filter is faulty then the filter and analysis block outputs will be different in amplitude or offset and the inbalance in currents from the two TE’s will develop a larger voltage across the grounded resistor, giving an increased analysis block output. Designing the analysis block to have an overall gain of 2 has been found to be sufficient to detect most of the faults outlined in Section 5.
CUT: fully balanced 5th order Chebyshev filter
differential input
filter output
test output
6.54p
6.54p
Fully balanced phase equaliser
Analysis block
Window detector
Output evaluation
Fig. 3. CMOS implementation of the test method.
6.3 Window detection block The window detector block, shown in Fig. 3, detects if the analysis block output waveform is inside or outside a certain window. In theory, when the filter is fault-free, the output of the analysis block is zero since the filter and equaliser outputs are the same. However, in practice there will be a small output from the analysis block even when the filter is fault-free due to manufacturing process variations and ripple in the filter passband. The window is chosen such that these normal, faultfree, analysis block outputs lie within it whilst the larger or more offset outputs associated with a faulty filter come entirely or partially out of it. Extensive SPICE simulations have shown that a window limit of ±100mV allows a very high fault coverage to be achieved in the case of the filter under consideration. Two separate level detectors are used for the high and low levels of the window, each implemented using a single CMOS inverter.
6.4 Output evaluation block The output evaluation block gives a test output of logic 0 in the case of a fault-free filter and logic 1 or an oscillatory signal in the case of a faulty filter. The output evaluation block has been designed using combinational logic and an inverter as shown in Fig. 3. The combinational logic circuit implements a Boolean expression describing the status of the high and low levels of the window detector, whilst the inverter is a single-stage buffer used to provide a well defined and unambiguous test output signal. Note that in the context of a mixed signal IC, it is expected that the on-chip oscillator would come from a master sinusoidal signal generator used for providing various testing stimulus for different parts of the chip. In the context of a stand-alone filter, a dedicated oscillator would have to be designed, many of which have been reported [11]. It is not our intention to discuss oscillator design in this paper.
7. SIMULATION RESULTS AND DISCUSSIONS All the faults discussed in Section 5 were individually inserted into each of the filter OTAs in turn and a SPICE simulation of the entire system run in each case. Due to space limitations, Fig. 4 only shows the results from two of these simulations. Fig. 4a shows the main signals in the case of a fault-free filter. The filter and equaliser outputs are the same (although opposite, see Section 6.1) and the analysis block output is therefore very small, lying entirely within the window limits. This is indicated by the high and low level detector outputs from which the output evaluation block derives the fault-free test output of logic 0. Fig. 4b shows the system signals in the case of a faulty filter, where the fault has affected the amplitude of the filter output. Since the filter and equaliser outputs are no longer the same, the analysis block output has increased and periodically comes out of the window limits, as indicated by the high and low level detector outputs. The output evaluation block derives an oscillating test output, which indicates that the filter is faulty. Note that this was an example of a fault affecting the filter output amplitude, yet a fault may well only introduce an offset in the filter output, as was described in Section 5. In this case the analysis block output may be entirely out of the window limits, giving an entirely high test output, which is also interpreted as faulty. BIST schemes are often characterised using a number of metrics including fault coverage, test circuit area overhead, test circuit design simplicity and performance impact on CUT: Fault coverage: SPICE simulation showed that 98.6% of detrimental faults were successfully detected. Area overhead: To achieve an accurate estimate of the test area overheads a custom layout was created and is shown in Fig. 5 with the CUT and the test circuitry clearly marked. The test circuitry represents 20% of the entire chip, which compares favourably with the numerous BIST techniques that have been proposed [8].
400
800
filter output analysis block output
window
0 -400
Amplitude (mV)
Amplitude (mV)
800
window
0 -400
equaliser
equaliser
-800
-800 4
high level detector output
Amplitude (V)
Amplitude (V)
4 2 0
low level detector output
-2 test output: fault-free
-4
analysis block output
filter output
400
0
10
Time (µs)
20
Fig. 4a. Signals derived from simulation of Fig.3 in the case of a fault free filter. Filter
Test circuitry
Fig. 5. Layout of the described test methodology Test circuit design simplicity: The design of the proposed test method circuitry is simple, as compared with previous reported methods. It is likely that the chosen window size of ±100mV will be sufficient for achieving a high fault coverage using different OTAs and fault models, in which case only the equaliser capacitance must be designed for, using Equ. 1. Performance impact on filter: The proposed test method has little or no effect on the filter during its normal operation as the testing circuitry is entirely disconnected unless in test mode (Fig.1). Also, the output evaluation block of the test circuitry provides an output buffer so that an external connection to the test output pin should have little effect on the filter performance. This paper has shown how group delay equalisation can be employed to produce a feasible BIST structural methodology for fully-balanced OTA-C filters. The methodology has a high fault coverage, test circuitry design simplicity, and has little or no impact on the filter under test performance. Furthermore, the methodology does not require high precision test stimulus and analysis response circuitry, hence minimising test accuracy dependence on manufacturing process variations. The proposed test methodology is independent of the filter under test design methods, unlike other reported test techniques which are limited to testing cascaded based filters only. Using simulation, the proposed test methodology has been extensively validated using a 5th-order Chebyshev low pass filter. Based on actual layout of the self-testable filter, the estimated area overhead introduced by the test circuitry is about 20%.
2 low level detector output
0 -2 -4
high level detector output
test output: faulty
0
10
Time (µs)
20
Fig. 4b. Simulation signals in the case of a faulty filter
9. REFERENCES [1] S. Solis-Bustos, J. Silva-Martinez, F. Maloberti, and E. Sanchez-Sinencio, “A 60-dB dynamic range CMOS 6th-order 2.4Hz lowpass filter for medical applications”, IEEE Trans. on Circuits and Systems-II, Vol.47, No.12, pp.1391-1399, Dec.2000. [2] B.M. Al-Hashimi, F. Dudek, M. Moniri, and J. Living, “Integrated universal biquad based on triple-output OTAs and using digitally programmable zeros”, IEE Proceedings- Circuits, Devices and Systems, Vol.145, No.3, pp.192-196, June 1998 [3] B. Nauta, “ A CMOS transconductance-C filter technique for very high frequencies”, IEEE Journal of Solid-State Circuits, 27(2), pp.142-153, 1992. [4] R. Schaumman, M.S. Ghausi, and K.R., Laker, “Design of analog filters: passive, active RC and switched capacitors”, Prentice-Hall , 1990 [5] B. Vinnakota, “Analog and mixed-signal test”, Prentice Hall PTR, 1998 [6] Y. Zorian, “Testing embedded core-based system chips”, IEEE Computers, 32(6), 52-60, 1999 [7] J.L. Huertas, A. Rueda, and D. Vazquez, “Testable switchedcapacitor filters”, IEEE Journal of Solid-State Circuits, Vol.28, pp.719-724, July 1993 [8] K.J. Lee, W.C., Wang, K.S., Huang, “A current-mode testable design of OTA-C filters”, IEEE Trans. on Circuits and Systems-II, Vol.46, No.4, pp.401-413, April 1999 [9] A. Chatterjee, “Concurrent error detection and fault-tolerance in linear analog circuits using continuous check sums”, IEEE Transactions on VLSI Systems, Vol 1, pp.138-150, June 1993. [10] B. Nauta, and E. Seevink, “ Linear CMOS transconductance element for VHF filters”, Electronics Letters, Vol.25, No.7, pp. 448-450, March 1989. [11] B. Linares-Barranco, A. Rodriguez-Vazques, E. SanchezSinencio, and J.l. Huertas, “ CMOS OTA-C high-frequency sinusoidal oscillators”, IEEE Journal of Solid-State Circuits, Vol.26, No.2, pp. 160-165, Feb 1991.
1. INTRODUCTION Filters are important signal processing building blocks in mixedsignal integrated circuits (ICs). Operational transconductance amplifier and capacitor (OTA-C) continuous-time filters have been shown experimentally to perform well in low frequency [1] and high frequency [2-3] applications. Unlike switched capacitor (SC) filters, OTA-C circuits do not suffer from switching noise problems and the necessity for pre and post filtering. For these reasons OTA-C filters are becoming the preferred choice for filtering problems in mixed-signal ICs. There is a danger in mixed-signal ICs that digital switching signals will be injected into the analogue circuitry through chip parasitics. To combat this problem, it is usual practice to build differential, rather than single-ended, circuitry. A fully balanced OTA-C filter design [4] goes further, ensuring a completely symmetrical layout such that parasitic injections will couple perfectly equally into both the signal paths, thus appearing as a common mode signal. Integrated filters are subject to manufacturing defects, and various design-for-test (DFT) techniques have been proposed. Built-in-self-test (BIST) circuitry aims to reduce test rig costs by moving stimulus generation and observation onto the IC, eliminating the need for off-chip interfacing and allowing the device to be tested many times during manufacture [5]. With the increase in silicon integration capacity, and the emergence of systems-on-chip (SoC), BIST is likely to provide the best DFT option [6] for testing complex ICs, including mixed-signal chips. Numerous BIST techniques for analogue filters have been reported [7 - 9] but despite all the work carried out, researchers are still looking for more efficient methods. The aim of this
paper is to describe a new BIST structural testing methodology for fully-balanced OTA-C filters. To the best of our knowledge, this paper not only shows for the first time how group-delay equalisation can be used in this context but also reports for the first time a test methodology which has been specifically developed for fully-balanced OTA-C filters, unlike [8]. The methodology is developed based on a thorough analysis of all possible short and open faults which may occur in the filter, resulting in a test accuracy less affected by manufacturing process variations. Furthermore, the proposed test methodology is independent of the filter under test (FUT) design method, unlike previous work [7].
2. PROPOSED METHODOLOGY The block diagram of the proposed BIST method is shown in Fig. 1. In normal filter operation, test mode is not selected so the switches are set to disconnect the testing circuitry. In test mode, the test stimulus signal from the on-chip oscillator is applied to both the filter and equaliser circuit, the latter being designed to match the filter delay at the test frequency. In the case of a faultfree filter, the filter and equaliser output waveforms will have the same amplitude and delay at the test frequency, however, in the case of a faulty filter, the outputs will be different. The analysis block determines and amplifies the difference between the filter output and the equaliser output. Normally, therefore, the analysis block output will be negligible but in the case of a faulty filter, its output will be larger, depending to what extent the fault has affected the filter output. If the analysis block output comes outside of a predefined tolerance window the window detector outputs will change and the output evaluation block gives a signal at the test output pin indicating that the filter is faulty, as will be shown in Section 7.
3. FILTER DESIGN th
A 5 order low pass Chebyshev filter was chosen for the CUT, in order to compare with recent work, specifications for which are: passband of 0 ≤ fc ≤ 4.5MHz; passband ripple of 0.5dB; stopband of 8MHz ≤ fs and stopband attenuation of 45dB. An initial LC ladder prototype was converted to a fully balanced OTA-C filter using well developed techniques [4]. To implement the filter at transistor level, the fully-balanced OTA of Fig. 2 was chosen, mainly because of its high bandwidth, good linearity, and low number of transistors [10]. The completed filter design is shown in the upper half of Fig. 3 using standard symbols to denote the transistor level OTA used. A gain stage was added to compensate for the 6dB insertion loss experienced by all equally terminated LC ladder filters and an additional 2.3dB loss associated with the non-ideal effects of the transistor level OTA.
Fully Balanced Filter
Differential Inputs
Differential Outputs
Test Mode Testing Circuitry
Analysis Window Detector
Fully Balanced Equaliser Network
On-Chip Oscillator
Output Evaluation
Test Output
Fig. 1. Block diagram of the proposed testing method Table 1. Fault list for the OTA of Fig. 2.
M1
M2
M5
M7
M9
M11
M3
M6
M8
M10
M12
No. 1 2 3 4 5
Fault (shorts): Vin+ shorted to Iout+ Vin+ shorted to IoutVin- shorted to Iout+ Vin- shorted to IoutIout+ shorted to Iout-
M4
Fig. 2. Fully balanced OTA for use in filter design [10].
4. TEST SIGNAL CHOICE The presented test method uses a single frequency sinusoidal test stimulus. On-chip OTA-C oscillators are difficult to design for low frequencies [11] but the equaliser network will not accurately match the delay of the filter at frequencies above or near the filter cutoff point, fc. With these considerations in mind, a test stimulus in the filter and equaliser passband of frequency 0.01fc was chosen, which allows the test signal frequency to be fairly inaccurate without altering test efficiency. For the Chebychev filter designed in Section 3, the test frequency is therefore 45kHz. A test signal amplitude of 1V p-p was chosen as this represents typical filter operating conditions.
5. FILTER FAULT MODELS To derive a successful structural testing methodology, it is essential to first understand what possible structural faults could arise in the circuit under test and the affects they would have. Without this analysis, the fault coverage of a proposed test method is purely speculative. A structural fault list, shown in Table 1, has been built representing all the catastrophic short and open faults which could occur in the fully balanced OTA of Fig. 2. Each fault was individually implemented on every filter OTA in turn and a simulation run in each case using the test signal described in Section 4. It was then possible to summarise the main affects faults had on the filter output. It was found that with the specified test signal, all detrimental faults changed the filter output in some way by at least 200mV. Furthermore, the changes were typically in one of three ways: 32% of detrimental faults were found to affect mostly the amplitude of the filter output, 34% introduced a positive offset and 34% introduced a negative offset. These findings have allowed efficient test circuitry to be designed to achieve a high fault coverage.
No. 6 7 8 9 10 11
Fault (opens): Open gate, M1 Open drain, M2 Open source, M4 Open gate, M5 Open source, M6 Open drain, M7
6. TEST CIRCUITRY DESIGN 6.1 Equaliser design It has been found that a 1st-order group delay equaliser is sufficient to test most practical filters using the new method. The chosen equaliser circuit can be seen in the lower half of Fig. 3. Knowledge of the filter DC group delay, τ(s), and use of Equ. 1 allows calculation of the equaliser capacitance, C, given that the OTAs used are identical to those used in the filter. To avoid confusion later, it is worth mentioning now that the phase equaliser designed in this Section introduces an inversion into the signal path. This is exploited in Section 6.2 to allow efficient design of the analysis block.
τ (s) =
− dϕ (ω ) 2C = dω gm
(1)
6.2 Analysis block The analysis block, shown in Fig. 3, compares the differential filter and equaliser output signals, amplifying the difference. The filter and equaliser outputs are connected to two simple transconductance elements (TE’s), which convert the differential voltages into single-ended currents. These currents flow into a common node connected to a grounded resistor. If the filter is fault-free then the filter and equaliser outputs will be identical, although opposite in sign as discussed in Section 6.1. Equal currents will flow into and out of the grounded resistor and a very small analysis block output will result. If the filter is faulty then the filter and analysis block outputs will be different in amplitude or offset and the inbalance in currents from the two TE’s will develop a larger voltage across the grounded resistor, giving an increased analysis block output. Designing the analysis block to have an overall gain of 2 has been found to be sufficient to detect most of the faults outlined in Section 5.
CUT: fully balanced 5th order Chebyshev filter
differential input
filter output
test output
6.54p
6.54p
Fully balanced phase equaliser
Analysis block
Window detector
Output evaluation
Fig. 3. CMOS implementation of the test method.
6.3 Window detection block The window detector block, shown in Fig. 3, detects if the analysis block output waveform is inside or outside a certain window. In theory, when the filter is fault-free, the output of the analysis block is zero since the filter and equaliser outputs are the same. However, in practice there will be a small output from the analysis block even when the filter is fault-free due to manufacturing process variations and ripple in the filter passband. The window is chosen such that these normal, faultfree, analysis block outputs lie within it whilst the larger or more offset outputs associated with a faulty filter come entirely or partially out of it. Extensive SPICE simulations have shown that a window limit of ±100mV allows a very high fault coverage to be achieved in the case of the filter under consideration. Two separate level detectors are used for the high and low levels of the window, each implemented using a single CMOS inverter.
6.4 Output evaluation block The output evaluation block gives a test output of logic 0 in the case of a fault-free filter and logic 1 or an oscillatory signal in the case of a faulty filter. The output evaluation block has been designed using combinational logic and an inverter as shown in Fig. 3. The combinational logic circuit implements a Boolean expression describing the status of the high and low levels of the window detector, whilst the inverter is a single-stage buffer used to provide a well defined and unambiguous test output signal. Note that in the context of a mixed signal IC, it is expected that the on-chip oscillator would come from a master sinusoidal signal generator used for providing various testing stimulus for different parts of the chip. In the context of a stand-alone filter, a dedicated oscillator would have to be designed, many of which have been reported [11]. It is not our intention to discuss oscillator design in this paper.
7. SIMULATION RESULTS AND DISCUSSIONS All the faults discussed in Section 5 were individually inserted into each of the filter OTAs in turn and a SPICE simulation of the entire system run in each case. Due to space limitations, Fig. 4 only shows the results from two of these simulations. Fig. 4a shows the main signals in the case of a fault-free filter. The filter and equaliser outputs are the same (although opposite, see Section 6.1) and the analysis block output is therefore very small, lying entirely within the window limits. This is indicated by the high and low level detector outputs from which the output evaluation block derives the fault-free test output of logic 0. Fig. 4b shows the system signals in the case of a faulty filter, where the fault has affected the amplitude of the filter output. Since the filter and equaliser outputs are no longer the same, the analysis block output has increased and periodically comes out of the window limits, as indicated by the high and low level detector outputs. The output evaluation block derives an oscillating test output, which indicates that the filter is faulty. Note that this was an example of a fault affecting the filter output amplitude, yet a fault may well only introduce an offset in the filter output, as was described in Section 5. In this case the analysis block output may be entirely out of the window limits, giving an entirely high test output, which is also interpreted as faulty. BIST schemes are often characterised using a number of metrics including fault coverage, test circuit area overhead, test circuit design simplicity and performance impact on CUT: Fault coverage: SPICE simulation showed that 98.6% of detrimental faults were successfully detected. Area overhead: To achieve an accurate estimate of the test area overheads a custom layout was created and is shown in Fig. 5 with the CUT and the test circuitry clearly marked. The test circuitry represents 20% of the entire chip, which compares favourably with the numerous BIST techniques that have been proposed [8].
400
800
filter output analysis block output
window
0 -400
Amplitude (mV)
Amplitude (mV)
800
window
0 -400
equaliser
equaliser
-800
-800 4
high level detector output
Amplitude (V)
Amplitude (V)
4 2 0
low level detector output
-2 test output: fault-free
-4
analysis block output
filter output
400
0
10
Time (µs)
20
Fig. 4a. Signals derived from simulation of Fig.3 in the case of a fault free filter. Filter
Test circuitry
Fig. 5. Layout of the described test methodology Test circuit design simplicity: The design of the proposed test method circuitry is simple, as compared with previous reported methods. It is likely that the chosen window size of ±100mV will be sufficient for achieving a high fault coverage using different OTAs and fault models, in which case only the equaliser capacitance must be designed for, using Equ. 1. Performance impact on filter: The proposed test method has little or no effect on the filter during its normal operation as the testing circuitry is entirely disconnected unless in test mode (Fig.1). Also, the output evaluation block of the test circuitry provides an output buffer so that an external connection to the test output pin should have little effect on the filter performance. This paper has shown how group delay equalisation can be employed to produce a feasible BIST structural methodology for fully-balanced OTA-C filters. The methodology has a high fault coverage, test circuitry design simplicity, and has little or no impact on the filter under test performance. Furthermore, the methodology does not require high precision test stimulus and analysis response circuitry, hence minimising test accuracy dependence on manufacturing process variations. The proposed test methodology is independent of the filter under test design methods, unlike other reported test techniques which are limited to testing cascaded based filters only. Using simulation, the proposed test methodology has been extensively validated using a 5th-order Chebyshev low pass filter. Based on actual layout of the self-testable filter, the estimated area overhead introduced by the test circuitry is about 20%.
2 low level detector output
0 -2 -4
high level detector output
test output: faulty
0
10
Time (µs)
20
Fig. 4b. Simulation signals in the case of a faulty filter
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