Carbon Nanotube-based Programmable Devices ... - Semantic Scholar
Carbon Nanotube-based Programmable Devices for Adaptive Architectures G. Agnus, A. Filoramo, J-P. Bourgoin V. Derycke
W. Zhao
Laboratoire d’Electronique Moléculaire CEA, IRAMIS, SPEC (CNRS URA 2464) 91191 Gif sur Yvette, France [email protected]
Embedded Computing Laboratory CEA, LIST 91191 Gif sur Yvette, France [email protected]
Abstract— We show that optically-gated carbon nanotube field effect transistors can be used as 2-terminal like devices with light sensitivity and memory capabilities. In particular, their channel resistivity can be adjusted precisely, within a large range and memorized. These devices can thus be used as synapses in neural network type of circuits. We demonstrate experimentally these properties, build a device model and propose a circuit architecture, which allows very efficient parallel learning.
I.
INTRODUCTION
Carbon nanotubes (CNTs) are known to have exceptional electronic properties. Still, the future integration of CNT transistors into conventional integrated circuits remains unlikely. Indeed, the potential improvement in performances, while significant, may not be sufficient to compensate for the large efforts necessary to solve the issues of precise placement of individual CNTs and device performance variability. However, CNTs benefit from decisive advantages that open new perspectives in unconventional type of circuits: (i) they have exceptional transport properties (mobility >104 cm2/V.s, ballistic transport over hundreds of nm) that allow high frequency operation [1,2], (ii) these properties are preserved when CNTs are integrated in various environments (CNTs can be assembled above-IC at the back-end process [3]), and (iii) CNT transistors can be functionalized to become highly sensitive light-, chemical- or bio-sensors [4-6]. However, it is expected that the circuit architectures developed for the CMOS technology will not be ideally suited to such nanoobjects. Notably, these architectures can barely cope with any significant variability among as-built devices, which is an inherent particularity of nano-devices. Conversely, adaptive circuits, such as neural networks, could take advantage of the rich functionality of nano-size building blocks while managing variability by means of a learning step. Our work shows that optically-gated carbon nanotube FETs (so called OG-CNTFETs) have all the required characteristics of nanoscale artificial synapses. They can be operated as 2terminal devices with memory capability (retention time >40h at present), large dynamics and remarkable tolerance to variability. Moreover, the capability to program independently multiple devices is also established and a way to implement
circuits is proposed. The topology is of crossbar type with additional shared gate electrodes. Based on our simulations, we show how this implementation allows efficient parallel learning. II.
An OG-CNTFET is a p-type carbon nanotube field-effect transistor in back-gate geometry coated with a thin film of photoconductive polymer (Fig. 1a) [6,7]. We demonstrated that the FET channel can be indifferently composed of a single semiconducting single-wall CNT (SWNT), multiple parallel semiconducting SWNTs or an array of SWNTs potentially composed of both metallic and semiconducting SWNTs (adjusted to provide a good off-state). At constant source-drain bias VDS and positive gate bias VGS, such FET is in its off-state but can be turned-on using light (Fig. 1b). Upon illumination electron-hole pairs are generated in the polymer, a fraction of which gets dissociated. While photo-induced holes are depleted from the device, electrons get trapped in the gate dielectric, at the polymer-SiO2 interface [8]. The trapped electrons apply a negative potential to the channel, which becomes more conductive. After light has been switched-off, a significant part of these electrons remain trapped giving rise to a memory state. Using either negative electrical pulses on the gate electrode [7,8] or positive electrical pulses on the source
This work is partially sponsored by the E.U through the Nabab project (FP7-216777), by the French ANR through the Panini project (ANR-07ARFU-008) and by the Région Ile de France for the Nanofabrication facility at CEA-SPEC.
978-1-4244-5309-2/10/$26.00 ©2010 IEEE
OPTICALLY-GATED NANOTUBE FETS
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Figure 1. (a) Schematic representation of an OG-CNTFET (CNT diameter: ~1.2 nm, channel length: 100 to 500 nm). Light generates electron-hole pairs, part of which gets separated. At VDS=-0.4V and VGS>0, holes get depleted from the polymer film while electrons get trapped at the SiO2/polymer interface. (b) Transfer characteristics before and during illumination. The trapped electrons set the FET in its on-state, regardless of VGS.
electrode [9], these electrons can be de-trapped in a controlled manner. By adjusting the number of trapped charges, the resistivity of the device channel can be precisely programmed and stored. In section IV we show that in the proposed architecture light is applied only once at the beginning of the learning procedure so that the learning or programming speed is set by the efficiency of the charge detrapping mechanism. Our initial OG-CNTFETs had gate oxide thickness of 10 to 20 nm. In such configuration programming electrical pulses of 10-100 ms were necessary. Recently, we developed a new process in which silicon wires serve as local gate electrodes (Fig. 2a) and the oxide thickness can be scaled down to 2.3 nm. With such thin oxide, high electric fields can be generated through the gate oxide at moderate bias (2-5 V) so that efficient electron detrapping is achieved. Fig. 2b demonstrates the programming efficiency of three 1µs-pulses applied on the local gate. In the best devices, the channel conductivity decreases by one order of magnitude within 600 ns.
=0 to 6 and R=5MΩ). In linear scale the I(V) curves are linear. We then show how this can be extended to small prototype circuits composed of a series of OG-CNTFETs as presented in Fig. 3b. The four devices are first globally illuminated to be set into their low resistivity state. Due to differences in the arrangement of CNTs within the networks, the four devices have dispersed initial resistivity values R1 to R4 (Fig. 3d). Using electrical pulses applied to the source electrodes the four devices can be precisely adjusted to the same resistivity value R0. We also verified the absence of crosstalk (i.e. unwanted change in resistivity of a device during the programming of its neighbors). This experiment shows that the variability among as built OG-CNTFETs can be efficiently compensated at the programming stage.
Figure 2. (a) OG-CNTFET in a double back-gate configuration (the polymer film is not shown for clarity). A silicon wire covered with 2.3 nm of SiO2 serves as efficient local gate. (b) Current through the nanotube as a function of time. A light pulse sets the device in the onstate. Electrical pulses of 1µs at VGS=-5 V program the CNT resistivity.
III.
Figure 3. (a) prinicple of a simple perceptron. (b) AFM image (16x31 µm2) of a 4 input - 1 output circuit based on carbon nanotube network transistors. The resistivity of each of the four devices stores the synaptic weigths Wi. (c) I(V) curves (log scale) of one of the four devices when programmed at 7 diffrent values of resistivity from R=5 MΩ to 64R. (d) Initial resistivity of the four devices (R1 to R4) after illumination. The variability comes from different topologies of CNTs within the networks. (d) After programming, the four devices can be set to arbitrary values.
MULTIPLE DEVICES OPERATION
We showed that both negative VGS [7] or positive VDS [9] pulses can be used to precisely adjust the OG-CNTFET conductivity. We propose to use the latter while keeping the gate potential constant at all time. By doing so, OG-CNTFETs are considered as 2-terminal devices [9]. Such approach allows implementing series of devices sharing the same gate electrode while addressing each of them independently using their input electrodes. Our first goal is to build a simple perceptron in which each OG-CNTFET plays the role of a synapse and its resistivity codes for the synaptic weight. In a perceptron (Fig. 3a), input signals (Xi) are multiplied by the synaptic weights (Wi) and then added at the neuron level. The sum is then compared to a reference (using for example a threshold function) and eventually, an output signal is emitted. Fig. 3b displays an AFM image of four CNT devices used as resistors. They all share the same global back-gate electrode and a common drain electrode. In this example, CNT networks were used in place of individual CNTs for simplicity but the same conclusions can be extended to smaller devices. Fig. 3c illustrates the range of programmability of one such CNT network device. In this example a particular device (one of the four from Fig. 3b) is successively programmed to 7 different values of resistivity using a combination of light and electrical pulses (these values were chosen to be 2n R with n
IV.
PROPOSED ARCHITECTURE
In section III, we used a global back-gate electrode common to the full wafer. Using OG-CNTFETs as strictly 2terminal devices is interesting in terms of circuit density but may be limited in terms of functionality. Hereafter, we evidence experimentally an additional property that governs the programmability of OG-CNTFETs and then use it to derive an original and efficient circuit architecture: The programming of OG-CNTFETs relies on electric-field assisted detrapping of electrons from the gate dielectric. This detrapping thus occurs only for negative VGS or positive VDS. As a consequence, if a strong positive bias is applied on the gate, it shields (or protect) the device from being programmed by positive VDS pulses. This ‘gate protection effect’ is experimentally demonstrated in Fig. 4a. An OG-CNTFET is first set to its conductive state using a single light pulse. Then a train of positive pulses is applied on the source electrode (blue) for two different configurations of gate bias. When
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VGS=0 (black), programming occurs. Conversely, when a constant and positive VGS bias (red) is applied during the programming sequence, this electric-field prevents electron detrapping and the final current is unaffected. This property provides an efficient way to address individually each nanodevice within an array. Instead of a single global gate electrode, we propose to implement one gate electrode per row of devices in crossbar geometry. An example of such topology comprising 4 neurons and 16 synapses is represented in Fig. 4b. Devices sharing the same gate (red) and source (black) electrodes along a row correspond to synapses connected to the same neuron. The pre-synapse drain terminals (blue) of each device within the same column are connected together and carry the input signals (Xn). Each neuron computes a different function (Yn) and can generate feedback signals toward its shared gate electrode (VGn). The neurons are simple CMOS-based comparators. The values to learn for each configuration of the inputs are presented on the corresponding Irefn terminals.
keep modifying synaptic weights in other rows until each output has reached its targeted value. This implies a dramatic increase in the learning speed as the total learning duration for the whole neural network circuits corresponds to the learning duration of one single function: the one requiring the largest number of programming pulses. One of the most important constraint of this architecture is the unidirectional learning mechanism associated with the optical global reset. In future work, a fully electrical version will be studied with, as only requirement, the combination of two electrical programming stimuli (one global and one shared by lines). Considering the combination of both top- and backgates, this solution can be realistically envisioned. For its physical implementation, the proposed architecture requires long and aligned CNTs precisely assembled with respect to pre-patterned silicon gates. This can be achieved on the basis of the recent progress in the CVD growth and transfer of dense arrays of perfectly aligned SWNTs [10]. V.
DEVICE MODEL AND SIMULATION
In order to design and simulate OG-CNTFET based circuits and architectures, we developed a behavioral spice model. It provides an interface between the physical phenomena taking place in the nano-device and an electrical test-bench compatible with large scale circuit simulations. The model integrates the principal properties described above and experimental parameters to improve the simulation accuracy. The first step for the behavioral modeling is to obtain a simple and efficient equivalent circuit of an OG-CNTFET (Fig. 5a). Three resistances are implemented: R0 is the minimum resistance Ron with a fixed value measured directly from nanodevices after illumination; RA varies dynamically with the drain voltage pulses and RB depends only on the drain voltage value. The equations for calculating RA and RB are obtained from the fitting of experimental measurements and are detailed in Ref. [11]. As shown in Fig. 4a, a positive gate bias prevents the electrical characteristic (RDS) of the device from being modified by the drain voltage. It also sets the sum (RA+RB) to Roff, which is a fixed value also directly measured.
Figure 4. (a) Output current of an OG-CNTFET as a function of time during a series of input bias pulses (blue) for two configurations of gate bias. At VGS=0 (black) programming takes place. At VGS=+6V, the device is protected from being programmed. (b) Proposed crossbar architecture with one shared gate electrode per neuron (red). The exemple comprises 4 neurons and 16 synapses.
Thanks to the gate protection effect, the proposed architecture allows massively parallel function learning (i.e. parallel synaptic weights adjustment). Light is first applied globally to set all the OG-CNTFETs in their low resistance state. Then, input pulses are sent to all the input electrodes simultaneously, which initiates the modification of all the synaptic weights. The total current originating from devices within a given row is compared to the respective reference target. Once this target value is reached, this neuron modifies the gate bias of the corresponding row so as to protect the full row from further change in device resistivity. Input signals
Figure 5. (a) Equivalent circuit from “on” to “off” state, R0 is the low resistance Ron, RA varies dynamically with the drain voltage pulses (n and t are respectively the number and duration of voltage pulse) and RB depends on the drain bias. The high gate voltage sets the sum of RA and RB to Roff, (b) Symbol of OG-CNTFET in Cadence Virtuoso, (c) By sharing the same optical gate, output and gate terminals, a row of OGCNTFETs as in Fig. 4b can be built.
The second step is to build the equivalent circuits and an electrical symbol (Fig. 5b) in the CAD platform such as Virtuoso. Verilog-A has been chosen as the program language as it provides easy parameter definition, good interface with Spice tools and abundant analog function libraries. The third step corresponds to the hierarchical design involved with the
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proposed architectures. Fig. 5c shows the electrical symbol corresponding to one row of four OG-CNTFETs, which share the same optical gate, electrical gate and output terminal. Using this model and a CMOS design kit, we can simulate and extrapolate the performances of realistic hybrid circuits and architectures comprising large numbers of nano-devices. Fig. 6 shows an example of simulation of parallel function learning for a crossbar architecture comprising four neurons and 64 synapses. Only the data for two of the four neurons are shown for clarity. As mentioned in section IV, there are three operating phases: (i) the initializing phase which resets optically all the synapses to the minimal weight. Three light pulses are used in the simulation to realize this task. (ii) the learning phase during which the weight of all the synapses are updated in parallel to reach the reference currents (in the simulated example: Iref0=30nA, Iref1=20nA) at different neurons. Once the summated current in one row reaches the corresponding reference current, the neuron activates the gate protection mechanism (Fig. 6d-e). (iii) the computing phase during which the circuit processes input signals within the learnt configuration by deactivating the gate protection feedback.
the programming so that a trade-off between time and precision is necessary. Alternately, increasing the number of synapses also improves significantly the precision. In our simulations, the accuracy becomes >98% when the number of synapses per neuron is changed from 16 to 100 and the reference currents are maintained similar. This precision improvement is also associated with an increase of the number of pulses required to reach the same Iref since the starting currents originating from 100 synapses in place of 16 are higher. Increasing the number of synapses could increase the circuit size, but as they would be built at the nano-scale while the neuron would be CMOS-based, this type of architecture would intrinsically be in a configuration of large synapses/neurons ratio compatible with high precision. With large numbers of synapses, a parallel learning procedure such as the one proposed here is a mandatory requirement. VI.
CONCLUSION
Based on experimental realizations, we showed that a new kind of nano-object based device gathers all the necessary requirements of artificial synapses. We demonstrated on a small type prototype how individual programming of multiple devices can be achieved and then proposed an original and efficient circuit architecture. Based on simulations, we showed that such architecture allows parallel learning within arrays of synapses. Combining a high level of functionality within a single nano-device together with well established CMOS-based functions at the neuron level, very attractive neuromorphic circuits can be envisioned. ACKNOWLEDGMENT We thank C. Gamrat (CEA List) for decisive inputs, D. Vuillaume and S. Lenfant (IEMN Lille) for scientific discussions and crucial help with wafer design and fabrication, B. Linares-Barranco (IMSE Sevilla) and J-O. Klein (IEF Orsay) for fruitful discussions.
Figure 6. Electrical simulation of an OG-CNTFET based neuromorphic circuit comprising 2 neurons and 16 synapses per neuron. The reference currents for these neurons 0 and 1 are respectively 30nA and 20nA (a) Voltage pulses applied at the inputs (Xn), (b, c) Current Is0 and Is1 at the post-synapse terminals, (d, e) Voltage VG0 and VG1 at the gate terminals.
It is important to note that in the proposed model, the parameters were adjusted to correspond to experimental data acquired on non scaled-down devices such as those used in Fig. 3. As shown in Section II, next generations of such circuits could be programmed with sub-µs pulses and the program voltage could be also reduced to standard CMOS logic drive voltage (e.g. 2 V). We should also note that the final currents at the end of the learning phase are close to the reference currents but with a moderate accuracy (~94%). A better accuracy can be obtained through the use of shorter programming pulses corresponding to smaller modifications of the resistivity at each step. This strategy is ultimately limited by the minimal pulse time that can be handled by the CMOS part and by the efficiency of the detrapping mechanism. Of course, it also increases the total duration of
REFERENCES [1] [2]
C. Rutherglen, D. Jain, P. Burke, Nature Nanotechnol. 4, 811 (2009). L. Nougaret, H. Happy, G. Dambrine, V. Derycke, J. -P. Bourgoin, A. A. Green and M. C. Hersam, Appl. Phys. Lett. 94 (2009) 243505. [3] D. Akinwande, S. Yasuda, B. Paul, S. Fujita, G. Close, HSP. Wong, IEEE Trans. on Nanotechnol. 7, 636 (2008). [4] P. Avouris, M. Freitag, V. Perebeinos, Nature Photonics 2, 341 (2008). [5] B.L. Allen, P.D. Kichambare, A. Star, Adv. Mater. 19, 1439 (2007). [6] A. Star, L. Yu, K. Bradley, G. Gruner, Nano Lett. 4, 1587 (2004). [7] J. Borghetti, V. Derycke, S. Lenfant, P. Chenevier, A. Filoramo, M. Goffman, D. Vuillaume, J.-P. Bourgoin, Adv. Mater. 18, 2535 (2006). [8] C. Anghel, V. Derycke, A. Filoramo, S. Lenfant, B. Giffard, D. Vuillaume, J.-P. Bourgoin, Nano Lett. 8, 3619 (2008). [9] G. Agnus, W. Zhao, V. Derycke, A. Filoramo, Y. Lhuillier, S. Lenfant, D. Vuillaume, C. Gamrat, J-P. Bourgoin, Adv. Mater. 22, 702 (2010). [10] S.J. Kang, C. Kocabas, T. Ozel, M. Shim, N. Pimparkar, M.A. Alam, S.V. Rotkin, J.A. Rogers, Nature Nanotechnol. 2, 230 (2007). [11] W. Zhao, G. Agnus, V. Derycke, A. Filoramo, C. Gamrat, J-P. Bourgoin, Proc of IEEE Int. Conf. on Nanotechnol. (IEEE-Nano), Genoa, Italy, pp.873-876 (2009).
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W. Zhao
Laboratoire d’Electronique Moléculaire CEA, IRAMIS, SPEC (CNRS URA 2464) 91191 Gif sur Yvette, France [email protected]
Embedded Computing Laboratory CEA, LIST 91191 Gif sur Yvette, France [email protected]
Abstract— We show that optically-gated carbon nanotube field effect transistors can be used as 2-terminal like devices with light sensitivity and memory capabilities. In particular, their channel resistivity can be adjusted precisely, within a large range and memorized. These devices can thus be used as synapses in neural network type of circuits. We demonstrate experimentally these properties, build a device model and propose a circuit architecture, which allows very efficient parallel learning.
I.
INTRODUCTION
Carbon nanotubes (CNTs) are known to have exceptional electronic properties. Still, the future integration of CNT transistors into conventional integrated circuits remains unlikely. Indeed, the potential improvement in performances, while significant, may not be sufficient to compensate for the large efforts necessary to solve the issues of precise placement of individual CNTs and device performance variability. However, CNTs benefit from decisive advantages that open new perspectives in unconventional type of circuits: (i) they have exceptional transport properties (mobility >104 cm2/V.s, ballistic transport over hundreds of nm) that allow high frequency operation [1,2], (ii) these properties are preserved when CNTs are integrated in various environments (CNTs can be assembled above-IC at the back-end process [3]), and (iii) CNT transistors can be functionalized to become highly sensitive light-, chemical- or bio-sensors [4-6]. However, it is expected that the circuit architectures developed for the CMOS technology will not be ideally suited to such nanoobjects. Notably, these architectures can barely cope with any significant variability among as-built devices, which is an inherent particularity of nano-devices. Conversely, adaptive circuits, such as neural networks, could take advantage of the rich functionality of nano-size building blocks while managing variability by means of a learning step. Our work shows that optically-gated carbon nanotube FETs (so called OG-CNTFETs) have all the required characteristics of nanoscale artificial synapses. They can be operated as 2terminal devices with memory capability (retention time >40h at present), large dynamics and remarkable tolerance to variability. Moreover, the capability to program independently multiple devices is also established and a way to implement
circuits is proposed. The topology is of crossbar type with additional shared gate electrodes. Based on our simulations, we show how this implementation allows efficient parallel learning. II.
An OG-CNTFET is a p-type carbon nanotube field-effect transistor in back-gate geometry coated with a thin film of photoconductive polymer (Fig. 1a) [6,7]. We demonstrated that the FET channel can be indifferently composed of a single semiconducting single-wall CNT (SWNT), multiple parallel semiconducting SWNTs or an array of SWNTs potentially composed of both metallic and semiconducting SWNTs (adjusted to provide a good off-state). At constant source-drain bias VDS and positive gate bias VGS, such FET is in its off-state but can be turned-on using light (Fig. 1b). Upon illumination electron-hole pairs are generated in the polymer, a fraction of which gets dissociated. While photo-induced holes are depleted from the device, electrons get trapped in the gate dielectric, at the polymer-SiO2 interface [8]. The trapped electrons apply a negative potential to the channel, which becomes more conductive. After light has been switched-off, a significant part of these electrons remain trapped giving rise to a memory state. Using either negative electrical pulses on the gate electrode [7,8] or positive electrical pulses on the source
This work is partially sponsored by the E.U through the Nabab project (FP7-216777), by the French ANR through the Panini project (ANR-07ARFU-008) and by the Région Ile de France for the Nanofabrication facility at CEA-SPEC.
978-1-4244-5309-2/10/$26.00 ©2010 IEEE
OPTICALLY-GATED NANOTUBE FETS
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Figure 1. (a) Schematic representation of an OG-CNTFET (CNT diameter: ~1.2 nm, channel length: 100 to 500 nm). Light generates electron-hole pairs, part of which gets separated. At VDS=-0.4V and VGS>0, holes get depleted from the polymer film while electrons get trapped at the SiO2/polymer interface. (b) Transfer characteristics before and during illumination. The trapped electrons set the FET in its on-state, regardless of VGS.
electrode [9], these electrons can be de-trapped in a controlled manner. By adjusting the number of trapped charges, the resistivity of the device channel can be precisely programmed and stored. In section IV we show that in the proposed architecture light is applied only once at the beginning of the learning procedure so that the learning or programming speed is set by the efficiency of the charge detrapping mechanism. Our initial OG-CNTFETs had gate oxide thickness of 10 to 20 nm. In such configuration programming electrical pulses of 10-100 ms were necessary. Recently, we developed a new process in which silicon wires serve as local gate electrodes (Fig. 2a) and the oxide thickness can be scaled down to 2.3 nm. With such thin oxide, high electric fields can be generated through the gate oxide at moderate bias (2-5 V) so that efficient electron detrapping is achieved. Fig. 2b demonstrates the programming efficiency of three 1µs-pulses applied on the local gate. In the best devices, the channel conductivity decreases by one order of magnitude within 600 ns.
=0 to 6 and R=5MΩ). In linear scale the I(V) curves are linear. We then show how this can be extended to small prototype circuits composed of a series of OG-CNTFETs as presented in Fig. 3b. The four devices are first globally illuminated to be set into their low resistivity state. Due to differences in the arrangement of CNTs within the networks, the four devices have dispersed initial resistivity values R1 to R4 (Fig. 3d). Using electrical pulses applied to the source electrodes the four devices can be precisely adjusted to the same resistivity value R0. We also verified the absence of crosstalk (i.e. unwanted change in resistivity of a device during the programming of its neighbors). This experiment shows that the variability among as built OG-CNTFETs can be efficiently compensated at the programming stage.
Figure 2. (a) OG-CNTFET in a double back-gate configuration (the polymer film is not shown for clarity). A silicon wire covered with 2.3 nm of SiO2 serves as efficient local gate. (b) Current through the nanotube as a function of time. A light pulse sets the device in the onstate. Electrical pulses of 1µs at VGS=-5 V program the CNT resistivity.
III.
Figure 3. (a) prinicple of a simple perceptron. (b) AFM image (16x31 µm2) of a 4 input - 1 output circuit based on carbon nanotube network transistors. The resistivity of each of the four devices stores the synaptic weigths Wi. (c) I(V) curves (log scale) of one of the four devices when programmed at 7 diffrent values of resistivity from R=5 MΩ to 64R. (d) Initial resistivity of the four devices (R1 to R4) after illumination. The variability comes from different topologies of CNTs within the networks. (d) After programming, the four devices can be set to arbitrary values.
MULTIPLE DEVICES OPERATION
We showed that both negative VGS [7] or positive VDS [9] pulses can be used to precisely adjust the OG-CNTFET conductivity. We propose to use the latter while keeping the gate potential constant at all time. By doing so, OG-CNTFETs are considered as 2-terminal devices [9]. Such approach allows implementing series of devices sharing the same gate electrode while addressing each of them independently using their input electrodes. Our first goal is to build a simple perceptron in which each OG-CNTFET plays the role of a synapse and its resistivity codes for the synaptic weight. In a perceptron (Fig. 3a), input signals (Xi) are multiplied by the synaptic weights (Wi) and then added at the neuron level. The sum is then compared to a reference (using for example a threshold function) and eventually, an output signal is emitted. Fig. 3b displays an AFM image of four CNT devices used as resistors. They all share the same global back-gate electrode and a common drain electrode. In this example, CNT networks were used in place of individual CNTs for simplicity but the same conclusions can be extended to smaller devices. Fig. 3c illustrates the range of programmability of one such CNT network device. In this example a particular device (one of the four from Fig. 3b) is successively programmed to 7 different values of resistivity using a combination of light and electrical pulses (these values were chosen to be 2n R with n
IV.
PROPOSED ARCHITECTURE
In section III, we used a global back-gate electrode common to the full wafer. Using OG-CNTFETs as strictly 2terminal devices is interesting in terms of circuit density but may be limited in terms of functionality. Hereafter, we evidence experimentally an additional property that governs the programmability of OG-CNTFETs and then use it to derive an original and efficient circuit architecture: The programming of OG-CNTFETs relies on electric-field assisted detrapping of electrons from the gate dielectric. This detrapping thus occurs only for negative VGS or positive VDS. As a consequence, if a strong positive bias is applied on the gate, it shields (or protect) the device from being programmed by positive VDS pulses. This ‘gate protection effect’ is experimentally demonstrated in Fig. 4a. An OG-CNTFET is first set to its conductive state using a single light pulse. Then a train of positive pulses is applied on the source electrode (blue) for two different configurations of gate bias. When
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VGS=0 (black), programming occurs. Conversely, when a constant and positive VGS bias (red) is applied during the programming sequence, this electric-field prevents electron detrapping and the final current is unaffected. This property provides an efficient way to address individually each nanodevice within an array. Instead of a single global gate electrode, we propose to implement one gate electrode per row of devices in crossbar geometry. An example of such topology comprising 4 neurons and 16 synapses is represented in Fig. 4b. Devices sharing the same gate (red) and source (black) electrodes along a row correspond to synapses connected to the same neuron. The pre-synapse drain terminals (blue) of each device within the same column are connected together and carry the input signals (Xn). Each neuron computes a different function (Yn) and can generate feedback signals toward its shared gate electrode (VGn). The neurons are simple CMOS-based comparators. The values to learn for each configuration of the inputs are presented on the corresponding Irefn terminals.
keep modifying synaptic weights in other rows until each output has reached its targeted value. This implies a dramatic increase in the learning speed as the total learning duration for the whole neural network circuits corresponds to the learning duration of one single function: the one requiring the largest number of programming pulses. One of the most important constraint of this architecture is the unidirectional learning mechanism associated with the optical global reset. In future work, a fully electrical version will be studied with, as only requirement, the combination of two electrical programming stimuli (one global and one shared by lines). Considering the combination of both top- and backgates, this solution can be realistically envisioned. For its physical implementation, the proposed architecture requires long and aligned CNTs precisely assembled with respect to pre-patterned silicon gates. This can be achieved on the basis of the recent progress in the CVD growth and transfer of dense arrays of perfectly aligned SWNTs [10]. V.
DEVICE MODEL AND SIMULATION
In order to design and simulate OG-CNTFET based circuits and architectures, we developed a behavioral spice model. It provides an interface between the physical phenomena taking place in the nano-device and an electrical test-bench compatible with large scale circuit simulations. The model integrates the principal properties described above and experimental parameters to improve the simulation accuracy. The first step for the behavioral modeling is to obtain a simple and efficient equivalent circuit of an OG-CNTFET (Fig. 5a). Three resistances are implemented: R0 is the minimum resistance Ron with a fixed value measured directly from nanodevices after illumination; RA varies dynamically with the drain voltage pulses and RB depends only on the drain voltage value. The equations for calculating RA and RB are obtained from the fitting of experimental measurements and are detailed in Ref. [11]. As shown in Fig. 4a, a positive gate bias prevents the electrical characteristic (RDS) of the device from being modified by the drain voltage. It also sets the sum (RA+RB) to Roff, which is a fixed value also directly measured.
Figure 4. (a) Output current of an OG-CNTFET as a function of time during a series of input bias pulses (blue) for two configurations of gate bias. At VGS=0 (black) programming takes place. At VGS=+6V, the device is protected from being programmed. (b) Proposed crossbar architecture with one shared gate electrode per neuron (red). The exemple comprises 4 neurons and 16 synapses.
Thanks to the gate protection effect, the proposed architecture allows massively parallel function learning (i.e. parallel synaptic weights adjustment). Light is first applied globally to set all the OG-CNTFETs in their low resistance state. Then, input pulses are sent to all the input electrodes simultaneously, which initiates the modification of all the synaptic weights. The total current originating from devices within a given row is compared to the respective reference target. Once this target value is reached, this neuron modifies the gate bias of the corresponding row so as to protect the full row from further change in device resistivity. Input signals
Figure 5. (a) Equivalent circuit from “on” to “off” state, R0 is the low resistance Ron, RA varies dynamically with the drain voltage pulses (n and t are respectively the number and duration of voltage pulse) and RB depends on the drain bias. The high gate voltage sets the sum of RA and RB to Roff, (b) Symbol of OG-CNTFET in Cadence Virtuoso, (c) By sharing the same optical gate, output and gate terminals, a row of OGCNTFETs as in Fig. 4b can be built.
The second step is to build the equivalent circuits and an electrical symbol (Fig. 5b) in the CAD platform such as Virtuoso. Verilog-A has been chosen as the program language as it provides easy parameter definition, good interface with Spice tools and abundant analog function libraries. The third step corresponds to the hierarchical design involved with the
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proposed architectures. Fig. 5c shows the electrical symbol corresponding to one row of four OG-CNTFETs, which share the same optical gate, electrical gate and output terminal. Using this model and a CMOS design kit, we can simulate and extrapolate the performances of realistic hybrid circuits and architectures comprising large numbers of nano-devices. Fig. 6 shows an example of simulation of parallel function learning for a crossbar architecture comprising four neurons and 64 synapses. Only the data for two of the four neurons are shown for clarity. As mentioned in section IV, there are three operating phases: (i) the initializing phase which resets optically all the synapses to the minimal weight. Three light pulses are used in the simulation to realize this task. (ii) the learning phase during which the weight of all the synapses are updated in parallel to reach the reference currents (in the simulated example: Iref0=30nA, Iref1=20nA) at different neurons. Once the summated current in one row reaches the corresponding reference current, the neuron activates the gate protection mechanism (Fig. 6d-e). (iii) the computing phase during which the circuit processes input signals within the learnt configuration by deactivating the gate protection feedback.
the programming so that a trade-off between time and precision is necessary. Alternately, increasing the number of synapses also improves significantly the precision. In our simulations, the accuracy becomes >98% when the number of synapses per neuron is changed from 16 to 100 and the reference currents are maintained similar. This precision improvement is also associated with an increase of the number of pulses required to reach the same Iref since the starting currents originating from 100 synapses in place of 16 are higher. Increasing the number of synapses could increase the circuit size, but as they would be built at the nano-scale while the neuron would be CMOS-based, this type of architecture would intrinsically be in a configuration of large synapses/neurons ratio compatible with high precision. With large numbers of synapses, a parallel learning procedure such as the one proposed here is a mandatory requirement. VI.
CONCLUSION
Based on experimental realizations, we showed that a new kind of nano-object based device gathers all the necessary requirements of artificial synapses. We demonstrated on a small type prototype how individual programming of multiple devices can be achieved and then proposed an original and efficient circuit architecture. Based on simulations, we showed that such architecture allows parallel learning within arrays of synapses. Combining a high level of functionality within a single nano-device together with well established CMOS-based functions at the neuron level, very attractive neuromorphic circuits can be envisioned. ACKNOWLEDGMENT We thank C. Gamrat (CEA List) for decisive inputs, D. Vuillaume and S. Lenfant (IEMN Lille) for scientific discussions and crucial help with wafer design and fabrication, B. Linares-Barranco (IMSE Sevilla) and J-O. Klein (IEF Orsay) for fruitful discussions.
Figure 6. Electrical simulation of an OG-CNTFET based neuromorphic circuit comprising 2 neurons and 16 synapses per neuron. The reference currents for these neurons 0 and 1 are respectively 30nA and 20nA (a) Voltage pulses applied at the inputs (Xn), (b, c) Current Is0 and Is1 at the post-synapse terminals, (d, e) Voltage VG0 and VG1 at the gate terminals.
It is important to note that in the proposed model, the parameters were adjusted to correspond to experimental data acquired on non scaled-down devices such as those used in Fig. 3. As shown in Section II, next generations of such circuits could be programmed with sub-µs pulses and the program voltage could be also reduced to standard CMOS logic drive voltage (e.g. 2 V). We should also note that the final currents at the end of the learning phase are close to the reference currents but with a moderate accuracy (~94%). A better accuracy can be obtained through the use of shorter programming pulses corresponding to smaller modifications of the resistivity at each step. This strategy is ultimately limited by the minimal pulse time that can be handled by the CMOS part and by the efficiency of the detrapping mechanism. Of course, it also increases the total duration of
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