Chameleon - Semantic Scholar
Chameleon: A High Performance Flash/
FRAM Hybrid Solid State Disk Architecture Jin Hyuk Yoon, Eyee Hyun Nam, Yoon Jae Seong,
Hongseok Kim, Bryan S. Kim, Sang Lyul Min, and Yookun Cho IEEE Computer Architecture Letters, Vol. 7, No. 1 Aug. 5, 2008
Speaker: Sehwan Lee
Introduction Chameleon
SSD(NAND flash memories) + Ferroelectric RAM
FRAM
Non-volatile Fast random reads In-place-updates
!"
#$$$%&'()*
Chameleon Hybrid SSD Architecture II. CHAMELEON HYBRID SSD ARCHITECTURE
Chameleon SSD Architecture Overview
A. Chameleon SSD Architecture Overview
Fig. 1. Chameleon SSD architecture.
Fig. 1 shows the overall architecture of the Chameleon SSD.
blo me GB ass boo 16 Mo cap
T buf blo [5] B
!"
#$$$%&'()*
Chameleon Hybrid SSD Architecture II. CHAMELEON HYBRID SSD ARCHITECTURE
Chameleon SSD Architecture Overview
A. Chameleon SSD Architecture Overview
FPGA
Fig. 1. Chameleon SSD architecture.
Fig. 1 shows the overall architecture of the Chameleon SSD.
blo me GB ass boo 16 Mo cap
T buf blo [5] B
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Data blocks
Write buffers Block-level write buffers To optimize the performance of sequential writes from the host
Page-level write buffers To optimize the performance of small random writes from the host
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon NAND Flash array
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon NAND Flash array
Data Blocks
•About 16 GB
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon NAND Flash array
Page-level Write Buffers •Size: 32MB
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon NAND Flash array
Block-level Write buffers •Size: 8MB
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon NAND Flash array
FRAM
• Size: 2MB •To obsorbe small random writes (meta data)
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Data blocks
Block Mapping Table The size of logical block = the degree of interleaving * The size of physical block FTL metadata are stored/maintained in... FRAM The spare area of each page scalability problem large boot time
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Write buffers: Block-level write buffers
Next write pointer
The logical block number associated with each write-level buffer
Three cases of write requests The next host write request == The next write pointer The next host write request > The next write pointer The next host write request < The next write pointer
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Write buffers: Block-level write buffers
Next write pointer
The logical block number associated with each write-level buffer
Three cases of write requests The next host write request == The next write pointer The next host write request > The next write pointer The next host write request < The next write pointer
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Write buffers: Block-level write buffers
Next write pointer
The logical block number associated with each write-level buffer
Three cases of write requests The next host write request == The next write pointer
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Write buffers: Block-level write buffers
Next write pointer
The logical block number associated with each write-level buffer
Three cases of write requests The next host write request == The next write pointer The next host write request > The next write pointer
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Write buffers: Block-level write buffers
Next write pointer
The logical block number associated with each write-level buffer
Three cases of write requests The next host write request == The next write pointer The next host write request > The next write pointer The next host write request < The next write pointer
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Write buffers: Page-level write buffers Handling methods All the write buffer blocks form a log as in a log-structured file system Data from the host write request is simply appended at the end of the log
How to replenish free pages? The number of valid pages in the log < threshold Choosing the smallest number of valid pages and erasing a block The number of valid pages in the log > threshold Choosing the largest number of valid pages and merging blocks
Chameleon Hybrid SSD Architecture Processing of Host Requets and Miscellaneous Issues Host write request processing Criterion If the request start at a local block boundary and the number of requested pages is above a given threshold
Host read request processing Bad block handling Wear-leveling Implicitily and explicitly
ssues ks and evious d in a ch the f write request on the block a given buffer; r. This most correct, of write
a read logical buffer.
GB. The degrees of both bus-level and chip-level interleavings are four and thus 16 chips operate in parallel. The sizes of block-level and page-level write buffers used in the experiment (2 MB) are 8 MB and 32 MB, respectively. The prototype uses the parallel ATA (PATA, also called IDE/EIDE) interface whose maximum transfer bandwidth is 66 MB/s in the current Inplementation Platform implementation. (Max. transfer bandwidth: 66MB/s)
Prototype Implementation and Performance Evaluation
(1GB*4 module *4slots) (20 MHz)
KB) (2 MB) Fig. 2. Chameleon (64 SSD prototype.
B. Performance Evaluation Method We used the PCMark04 benchmark program [3] for our
Prototype Implementation and Performance Evaluation Performance Evaluation Method PCMark04 Benchmark program Window XP Startup Application Loading General HDD Usage File Copying
Prototype Implementation and Performance Evaluation !"
#$$$%&'()*+$,%-
C. Evaluation Results Evaluation Results
TABLE I PERFORMANCE EFFECT OF FRAM Chameleon Chameleon w/o FRAM with FRAM PCMark04 HDD Score 10585 12841 Windows XP Startup 21.2 MB/s 25.0 MB/s Application Loading 18.3 MB/s 22.9 MB/s General HDD Usage 14.7 MB/s 18.0 MB/s File Copying 30.4 MB/s 33.9 MB/s
% gain 21.3 % 17.9 % 25.1 % 22.4 % 11.5 %
To evaluate how much performance gain is made due to the use of FRAM in the Chameleon SSD, we implemented an alternative FTL that does not make any use of FRAM and emulates the reads/writes from/to FRAM by read/modify/write operations using SRAM and page-level write buffers in flash memory.
In File C can be e addition performa
In thi Flash/FR cures th random w evaluatio Chamele Chamele also show in FRAM buffering
FRAM is 21.3 % according to the PCMark04 score calculated from a weighted sum of the four component benchmark programs based on a typical usage pattern [3]. All the component benchmarks except File Copying show similar performance improvements. In File Copying, sequential writes dominate and since this access pattern generates only a small number of updates to the FTL metadata, the performance Evaluation Results improvement is limited.
Prototype Implementation and Performance Evaluation 50.0 45.0 40.0 35.0
31.9 28.9
MB/s
30.0
24.4 25.0
25.0
22.3 22.9
20.0
16.8
18.0
15.0 10.0
33.9
7.5 8.3
5.0
5.3 5.6
14.5
4.4 5.1
0.0 Windows XP Startup
Application Loading
block-level write buffer (X), page-level write buffer (X) block-level write buffer (X), page-level write buffer (O)
General Usage
File Copying
block-level write buffer (O), page-level write buffer (X) block-level write buffer (O), page-level write buffer (O)
Fig. 3. Effect of block-level and page-level write buffering.
Fig. 3 shows PCMark04 results for different combinations of block-level and page-level write buffering in the Chameleon
improve Experien [3] Futurema http://ww [4] E. Gal memorie 2005. [5] A. Kawa system,” 155-164. [6] J. Kim, J flash tra Consume [7] S.-W. Le “A log b translatio Jul. 2007 [8] Ramtron http://ww [9] M. Rose log-struc 1, pp. 26 [10] Samsung http://ww [11] A. Sheik ferroelec May 200 [12] C.-H. W flash tran Internati
Conclusions Chameleon
FRAM+SSD (NAND Flash array) Although the size of FRAM is not enought for maintaining bulk data, the use of write buffering at the page-level is important Practical implementation of Chameleon
FRAM Hybrid Solid State Disk Architecture Jin Hyuk Yoon, Eyee Hyun Nam, Yoon Jae Seong,
Hongseok Kim, Bryan S. Kim, Sang Lyul Min, and Yookun Cho IEEE Computer Architecture Letters, Vol. 7, No. 1 Aug. 5, 2008
Speaker: Sehwan Lee
Introduction Chameleon
SSD(NAND flash memories) + Ferroelectric RAM
FRAM
Non-volatile Fast random reads In-place-updates
!"
#$$$%&'()*
Chameleon Hybrid SSD Architecture II. CHAMELEON HYBRID SSD ARCHITECTURE
Chameleon SSD Architecture Overview
A. Chameleon SSD Architecture Overview
Fig. 1. Chameleon SSD architecture.
Fig. 1 shows the overall architecture of the Chameleon SSD.
blo me GB ass boo 16 Mo cap
T buf blo [5] B
!"
#$$$%&'()*
Chameleon Hybrid SSD Architecture II. CHAMELEON HYBRID SSD ARCHITECTURE
Chameleon SSD Architecture Overview
A. Chameleon SSD Architecture Overview
FPGA
Fig. 1. Chameleon SSD architecture.
Fig. 1 shows the overall architecture of the Chameleon SSD.
blo me GB ass boo 16 Mo cap
T buf blo [5] B
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Data blocks
Write buffers Block-level write buffers To optimize the performance of sequential writes from the host
Page-level write buffers To optimize the performance of small random writes from the host
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon NAND Flash array
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon NAND Flash array
Data Blocks
•About 16 GB
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon NAND Flash array
Page-level Write Buffers •Size: 32MB
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon NAND Flash array
Block-level Write buffers •Size: 8MB
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon NAND Flash array
FRAM
• Size: 2MB •To obsorbe small random writes (meta data)
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Data blocks
Block Mapping Table The size of logical block = the degree of interleaving * The size of physical block FTL metadata are stored/maintained in... FRAM The spare area of each page scalability problem large boot time
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Write buffers: Block-level write buffers
Next write pointer
The logical block number associated with each write-level buffer
Three cases of write requests The next host write request == The next write pointer The next host write request > The next write pointer The next host write request < The next write pointer
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Write buffers: Block-level write buffers
Next write pointer
The logical block number associated with each write-level buffer
Three cases of write requests The next host write request == The next write pointer The next host write request > The next write pointer The next host write request < The next write pointer
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Write buffers: Block-level write buffers
Next write pointer
The logical block number associated with each write-level buffer
Three cases of write requests The next host write request == The next write pointer
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Write buffers: Block-level write buffers
Next write pointer
The logical block number associated with each write-level buffer
Three cases of write requests The next host write request == The next write pointer The next host write request > The next write pointer
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Write buffers: Block-level write buffers
Next write pointer
The logical block number associated with each write-level buffer
Three cases of write requests The next host write request == The next write pointer The next host write request > The next write pointer The next host write request < The next write pointer
Chameleon Hybrid SSD Architecture Two Types of Non-volatile Data in Chameleon Write buffers: Page-level write buffers Handling methods All the write buffer blocks form a log as in a log-structured file system Data from the host write request is simply appended at the end of the log
How to replenish free pages? The number of valid pages in the log < threshold Choosing the smallest number of valid pages and erasing a block The number of valid pages in the log > threshold Choosing the largest number of valid pages and merging blocks
Chameleon Hybrid SSD Architecture Processing of Host Requets and Miscellaneous Issues Host write request processing Criterion If the request start at a local block boundary and the number of requested pages is above a given threshold
Host read request processing Bad block handling Wear-leveling Implicitily and explicitly
ssues ks and evious d in a ch the f write request on the block a given buffer; r. This most correct, of write
a read logical buffer.
GB. The degrees of both bus-level and chip-level interleavings are four and thus 16 chips operate in parallel. The sizes of block-level and page-level write buffers used in the experiment (2 MB) are 8 MB and 32 MB, respectively. The prototype uses the parallel ATA (PATA, also called IDE/EIDE) interface whose maximum transfer bandwidth is 66 MB/s in the current Inplementation Platform implementation. (Max. transfer bandwidth: 66MB/s)
Prototype Implementation and Performance Evaluation
(1GB*4 module *4slots) (20 MHz)
KB) (2 MB) Fig. 2. Chameleon (64 SSD prototype.
B. Performance Evaluation Method We used the PCMark04 benchmark program [3] for our
Prototype Implementation and Performance Evaluation Performance Evaluation Method PCMark04 Benchmark program Window XP Startup Application Loading General HDD Usage File Copying
Prototype Implementation and Performance Evaluation !"
#$$$%&'()*+$,%-
C. Evaluation Results Evaluation Results
TABLE I PERFORMANCE EFFECT OF FRAM Chameleon Chameleon w/o FRAM with FRAM PCMark04 HDD Score 10585 12841 Windows XP Startup 21.2 MB/s 25.0 MB/s Application Loading 18.3 MB/s 22.9 MB/s General HDD Usage 14.7 MB/s 18.0 MB/s File Copying 30.4 MB/s 33.9 MB/s
% gain 21.3 % 17.9 % 25.1 % 22.4 % 11.5 %
To evaluate how much performance gain is made due to the use of FRAM in the Chameleon SSD, we implemented an alternative FTL that does not make any use of FRAM and emulates the reads/writes from/to FRAM by read/modify/write operations using SRAM and page-level write buffers in flash memory.
In File C can be e addition performa
In thi Flash/FR cures th random w evaluatio Chamele Chamele also show in FRAM buffering
FRAM is 21.3 % according to the PCMark04 score calculated from a weighted sum of the four component benchmark programs based on a typical usage pattern [3]. All the component benchmarks except File Copying show similar performance improvements. In File Copying, sequential writes dominate and since this access pattern generates only a small number of updates to the FTL metadata, the performance Evaluation Results improvement is limited.
Prototype Implementation and Performance Evaluation 50.0 45.0 40.0 35.0
31.9 28.9
MB/s
30.0
24.4 25.0
25.0
22.3 22.9
20.0
16.8
18.0
15.0 10.0
33.9
7.5 8.3
5.0
5.3 5.6
14.5
4.4 5.1
0.0 Windows XP Startup
Application Loading
block-level write buffer (X), page-level write buffer (X) block-level write buffer (X), page-level write buffer (O)
General Usage
File Copying
block-level write buffer (O), page-level write buffer (X) block-level write buffer (O), page-level write buffer (O)
Fig. 3. Effect of block-level and page-level write buffering.
Fig. 3 shows PCMark04 results for different combinations of block-level and page-level write buffering in the Chameleon
improve Experien [3] Futurema http://ww [4] E. Gal memorie 2005. [5] A. Kawa system,” 155-164. [6] J. Kim, J flash tra Consume [7] S.-W. Le “A log b translatio Jul. 2007 [8] Ramtron http://ww [9] M. Rose log-struc 1, pp. 26 [10] Samsung http://ww [11] A. Sheik ferroelec May 200 [12] C.-H. W flash tran Internati
Conclusions Chameleon
FRAM+SSD (NAND Flash array) Although the size of FRAM is not enought for maintaining bulk data, the use of write buffering at the page-level is important Practical implementation of Chameleon
