Seminars by Exhibitors December 3rd, 2008
ASSEMBLY STRATEGIES FOR 3D-IC INTEGRATION WAFER-TO-WAFER VERSUS CHIP-TO-WAFER Gilbert Lecarpentier Product Manager
[email protected] Abstract: With the advent of 3D Integration concepts as a potential enabler for the continuation of Moore’s law, the aligned wafer bonding requirements have shifted significantly. Chip-to-Wafer bonding and wafer reconstruction represent alternative or complementary solutions to improve yield and chip size flexibility; pros and cons of the two methods are reviewed.
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Exhibitor Seminars - December 3rd, 2008
SET AT A GLANCE Founded in 1975 SUSS MicroTec Device Division from 1993 to 2007 07/2007: SET (MBO) 01/2008: Subsidiary of Replisaurus Located in the French Alps (Grenoble: 90’ – Geneva: 30’) 58 employees
Assembly - Class 10,000 (546 m²)
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Test Area - Class 1,000 (149 m²)
Exhibitor Seminars - December 3rd, 2008
Acceptance - Class 100 (30 m²)
SET / REPLISAURUS CONTRIBUTION TO 3D-IC
S E T R T I
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Exhibitor Seminars - December 3rd, 2008
SET / REPLISAURUS CONTRIBUTION TO 3D-IC
S E T
R T I
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Exhibitor Seminars - December 3rd, 2008
AGENDA
1st transistor, 1947
Introduction Wafer Stacking Vs Chip-to-Wafer Bonding Wafer to Wafer Bonding Wafer Bonding Techniques Align and Bond Process Chip to Wafer / Chip to Chip Bonding Die Bonding Techniques Assembly scenarios Examples Summary
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Exhibitor Seminars - December 3rd, 2008
INTRODUCTION 3D Assembly by Chip or Wafer Stacking enables the development of Very High Density, Multifunction Devices and satisfies the demand for Higher Packaging Miniaturization 3D-Assemby Technologies Chip-to-Chip Chip-to-Wafer Wafer-to-Wafer (Wafer Stacking) 3D - WB 2D
Source
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Exhibitor Seminars - December 3rd, 2008
3D - TSV
WAFER TO WAFER Vs. CHIP-TO-WAFER Wafer Stacking technique
Chip-to-Wafer technique
Wafer Bonder
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Exhibitor Seminars - December 3rd, 2008
Device Bonder
W2W Vs. C2W
APPLICATIONS
Source
Source: Terrazon Semiconductors
Wafer To Wafer Memory: DRAM, PCRAM, FERAM, MRAM FPGA Sensors Processors 1,000 to 1,000,000 connections per square millimeters Chip-to-Wafer Memory to Logic Mixed Materials (GaAs, InP) Known good die yield ++ 1,000 to 1,000,000 connections per square millimeters
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Exhibitor Seminars - December 3rd, 2008
CHIP TO WAFER Vs. WAFER STACKING WAFER STACKING ☺ High Throughput Wafer Level Component size must be identical Yield ? CHIP-TO-WAFER Low Throughput Single Chip Placement ☺ High Yield Known Good Die ☺ Flexibility Component size Different Technologies
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Exhibitor Seminars - December 3rd, 2008
WAFER STACKING Vs. CHIP-TO-WAFER Wafer Stacking technique
Chip-to-Wafer technique
Wafer Bonder
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Exhibitor Seminars - December 3rd, 2008
Device Bonder
WAFER BONDING TECHNIQUES
WBT Without intermediate layer
Si direct bonding
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Anodic bonding
WBT With intermediate layer
Solder bonding
Eutectic TC metal bonding bonding
Exhibitor Seminars - December 3rd, 2008
Glass frit bonding
Adhesive bonding
WAFER BONDER - ALIGN & BOND PROCESS Alignment performed outside of the bonding chamber The Wafer stack is transferred to the bonding chamber using a transport fixture The fixture achieves two functions it transfers the aligned wafers Maintains a gap (if needed) between wafers for purging before bonding MEMS applications often require wafer bonding to be carried out in controlled environmental conditions Low pressure / vacuum or inert gases to be encapsulated in between die on the wafers
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Exhibitor Seminars - December 3rd, 2008
WAFER BONDER - ALIGN & BOND PROCESS Bond Load wafers into Bond Aligner Full auto Bond cluster
Wafer clamp into fixture after alignment Semi-auto
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Exhibitor Seminars - December 3rd, 2008
WAFER BONDER: TYPICAL BONDING SEQUENCE
Load fixture with aligned wafers into the bond chamber
Bond wafers by applying force, heat, electrical current and/or pressurized confinement
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Exhibitor Seminars - December 3rd, 2008
WAFER STACKING Vs. CHIP-TO-WAFER Wafer Stacking technique
Chip-to-Wafer technique
Wafer Bonder
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Exhibitor Seminars - December 3rd, 2008
Device Bonder
CHIP BONDING PROCESSES (FC)
Thermo compression Temperature, Force Gap control Bumps Au, In, …
Bumps Au, Ni/Au with Adhesive
NCA
ACA
Temperature Gap control
Temperature Fluxing
Low Force
PbSn, SnAg, 80AuSn, In Bumps
PbSn, SnAg, In Bumps (+ flux)
No intermediate layer
ICA
Device Bonder
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Direct
Reflow
Exhibitor Seminars - December 3rd, 2008
Pick and Place
CHIP TO WAFER – FACE UP CHIP PLACEMENT Chip are placed one after each other They can be aligned individually with respect to wafer/substrate pattern Alternatively, they can be aligned prior to pick up and placed using a step and repeat approach if the wafer/substrate is blank The accuracy is then the accuracy of the Wafer/Substrate X/Y stage The operation can be repeated to place another chip on top of the first one >> 3D-Stacking
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Exhibitor Seminars - December 3rd, 2008
CHIP TO WAFER – FACE UP CHIP PLACEMENT & BONDING Chip are placed one after each other They can be aligned individually with respect to wafer/substrate pattern Alternatively, they can be aligned prior to pick up and placed using a step and repeat approach if the wafer/substrate is blank The accuracy is then the accuracy of the Wafer/Substrate X/Y stage The operation can be repeated to place another chip on top of the first one >> 3D-Stacking Chip-to-Substrate and/or Chip-to-Chip connections are then made with wire bonding 18
Exhibitor Seminars - December 3rd, 2008
CHIP TO WAFER – FLIP CHIP PLACEMENT (AND BONDING) The Placement Sequence is similar to the Sequence used for Face UP Placement The Connections are visible on the Wafer and can be used to perform Chip-to-Wafer Alignment Electrical connections is performed simultaneously to chip bonding The operation can be repeated several times to place another chip on top of the first one Electrical connections is performed simultaneously to chip bonding It is possible to mix Face Up & Flip Chip
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Exhibitor Seminars - December 3rd, 2008
CHIP-TO-WAFER -- FACE UP Vs FLIP CHIP FACE UP ☺ Rework ability, Testability Wire Bond
Serial process
Wire Bond
Long connection
FLIP CHIP Rework (only possible for Reflow) ☺ Global bonding ☺ Bumps = Short connection
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Exhibitor Seminars - December 3rd, 2008
CHIP-TO-WAFER AND WAFER-TO-WAFER COMPLEMENTARY TECHNIQUES
To enable Wafer-to-Wafer bonding with Chips of different size, it is possible to rebuild a Wafer by placing Chips accurately on a given mesh with a accurate device bonder The gap between chips is then filled with appropriated resin If Flip Chip Technique is used, it guarantees that the top surface of all chips is on a plan and enables thinning of the reconstructed wafer
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Exhibitor Seminars - December 3rd, 2008
CHIP-TO-WAFER AND WAFER-TO-WAFER COMPLEMENTARY TECHNIQUES
At this stage, it is possible to process the components at wafer level using standard photolithography process Photo-resist coating, baking Masking, Development, etching etc.
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Exhibitor Seminars - December 3rd, 2008
EXAMPLE OF APPLICATIONS
Courtesy: IMEC
MEMS RF Device assembled to a logic system with Package on Package Approach Memory stack: 2D Flip Chip Bonding on Silicon Substrates stacked together Memory stack using Trough Silicon Vias
Source: Samsung
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Exhibitor Seminars - December 3rd, 2008
EXAMPLE OF APPLICATION
Chip-to-Wafer Process Chips Placement (Flip Chip) Wafer Level Processing Potting Pad’s Redistribution Thinning and Dicing Chip-to-Chip Process Stacking 3D interconnect
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Exhibitor Seminars - December 3rd, 2008
EXAMPLE OF APPLICATION ENCAPSULATION ON WAFER Encapsulation Wafer to Wafer W2W
Wafer with « Caps or Window »
Wafer with « Chips to Encapsulate »
Encapsulation Chip to Wafer C2W
Wafer with « Caps or Functionalized Window »
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Wafer with « Chips to Encapsulate »
Exhibitor Seminars - December 3rd, 2008
Placement and Sealing On the entire matrix
SEALING AND FINAL ALIGNMENT BY COLLECTIVE REFLOW Cadence +
PICK/PLACE High Speed Placement of Functionalized Caps Alignment requirement Application dependent 5 ~ 10 µm
Pick & Place =Alignment and Deposition Controlled Atmosphere
BONDING Self Alignment Fast Temperature Ramp Hermetic Encapsulation under Controlled Atmosphere 26
Exhibitor Seminars - December 3rd, 2008
Bonding = T >Tf
SIMULTANEOUS HERMETIC SEALING AND CONNECTION -- PROCESS FLOW Cap is tacked to the substrate Higher Connection Bumps maintain a Gap ensuring Gas Flow and Pumping between Inner Solder Cap Ring and MEMS Wafer Wetting Pads Geometry Controls Cap Collapsing during Reflow
Controlled atmosphere or vacuum
Sealing Ring contacts the Wetting Ring on the opposite wafer, capturing the required atmosphere inside the MEMS cavity. Oxide reduction Vacuum Gettering
Controlled Collapse Hermetic Sealing Solder ring interconnection
Cap
MEMS wafer
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MEMS
Exhibitor Seminars - December 3rd, 2008
COLLECTIVE REFLOW IN THE EMBEDDED CHAMBER FOR VACUUM OR GAS CONFINEMENT Having the Chamber included inside the Placement Tool eliminates the risk of Chips shifting during wafer transport
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Exhibitor Seminars - December 3rd, 2008
DEMONSTRATOR -- SEALING RESULTS FLIP-CAP
Indium Ring Indium bump
Gold plated UBM lands
Cap chip Bottom chip
SEALED COMPONENT
1 2 3 4
Before soldering Bump height Ring height 39,7 18,1 32,4 15,6 52 44,6
22,2 19,3
After soldering (separate) Bump height Ring height 10,9 11,5 10 10,7 10,5 10
Bump only
Ring only
14,4 13,3 FINAL = Bumps + Ring
Measured ring and bump height for 4 different bump & ring designs 1,2,3,4 using a « sixteen bumps / one ring design »
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Exhibitor Seminars - December 3rd, 2008
SUMMARY (1/2) Various pieces of equipment are available to suit different degrees of automation or flexibility Device Bonder can be used in combination with Wafer Bonder to increase throughput: In Thermo-compression mode; Chips are Tacked and Final Bond occurs in the Wafer Bonder When Using Reflow Bonding, a Chamber can be used to Reflow under Vacuum or Gas environment
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Exhibitor Seminars - December 3rd, 2008
SUMMARY (2/2) 3D Assembly
+ Multifunction devices + Packaging density increases
Wafer-to-Wafer
+ Higher Throughput (globalization) - Overlay control (slightly better with In Situ Aligner bonder) - Component sizes - Yield
Chip-to-Wafer
+ Yield (Known Good Die – KGD) + Flexibility - Lower Throughput (serialization)
Higher throughput can be achieved by 2-Step approach, placement then collective bonding ● Thermo Compression, using a wafer Bonder ● Collective Reflow Chamber as illustrated in the previous example
W2W, C2W and C2C are complementary techniques
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Exhibitor Seminars - December 3rd, 2008
Thank you for your attention >> Questions?
Seminars by Exhibitors December 3rd, 2008
ASSEMBLY STRATEGIES FOR 3D-IC INTEGRATION WAFER-TO-WAFER VERSUS CHIP-TO-WAFER Gilbert Lecarpentier Product Manager
[email protected] Abstract: With the advent of 3D Integration concepts as a potential enabler for the continuation of Moore’s law, the aligned wafer bonding requirements have shifted significantly. Chip-to-Wafer bonding and wafer reconstruction represent alternative or complementary solutions to improve yield and chip size flexibility; pros and cons of the two methods are reviewed.
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Exhibitor Seminars - December 3rd, 2008