Compact Model for Vertical Silicon Nanowire Based Device ...
Compact Model for Vertical Silicon Nanowire Based Device Simulation and Circuit Design M. Sharma, S. Maheshwaram, Om. Prakash, A. Bulusu, A.K. Saxena and S.K. Manhas* Microelectronics & VLSI, E&CE Dept., Indian Institute of Technology Roorkee, Uttarakhand-247667, India. *Phone: +91-1332-285147 E-mail: [email protected] existing I-V and C-V model framework [1]. The main equations used are listed as (1)-(4) in Table 1. At extremely scaled device dimensions, the drain side potential starts to affect channel potential in form of VT roll-off, DIBL, subthreshold slope degradation known as SCE. These SCEs are modeled as in [2] by using αSCE ≠1 in (2). The quantum mechanical effects are modeled using [2], mobility degradation and velocity saturation are modeled as in [4].
Abstract— Verilog-A based unified compact model of silicon vertical nanowire FET is developed for circuit simulation, which includes: short channel, velocity saturation, mobility degradation, quantum mechanical effects and device parasitic. We include scalable TCAD calibrated parasitic resistance and capacitance models, which also consider device asymmetry due to vertical nanowire structure. The model shows excellent match with calibrated TCAD at device as well as circuit level for both long and short channel devices. Further, the model results underline the importance of parasitics on nanowire based circuit performance.
Parasitic at extremely scaled dimension play a crucial role in determining the characteristics of device. By virtue of its structure as shown in Fig.1 the VNW is an asymmetric device, which lead to different parasitic for top and bottom electrode. These parasitic are highlighted in Fig. 1 and Fig. 2 and main equation are listed in Table 2. The calibrated parasitic models proposed by us are presented in detail in [5], which are integrated into the core model.
Keywords- Parasitics, Verilog-A model, vertical nanowire FET.
I.
INTRODUCTION
The multigate devices such as FinFETs and nanowire-FET are projected to be replacement for planar CMOS due to immunity against short channel effects (SCE) for 22nm and below technology nodes. In addition to very low SCE, the vertical nanowire (VNW) shown in Fig. 1 occupies least silicon area, high on to off current ratio. The silicon nanowire is best suited for high speed and low power applications. In nanoscale regime, however, the device parasitic degrades the circuit performance and is a critical issue in device and circuit performance. In order to analyze the performance of circuits based on VNW, a unified compact model of VNW is required, which can capture both parasitic and nanoscale physical effects. The compact models for lateral NW FETs have been reported [1]-[4], however most of these models are limited in their application as they do not consider device structural parasitics. In particular no compact model for VNW MOSFET considering realistic parasitic models and device asymmetry has been reported. In absence of these parasitics, any compact model will not accurately predict device and circuit performance.
III.
The developed complete model is able to accurately reproduce the reported long channel I-V (error < 4%) and C-V (error < 6%) characteristics [1]-[2], and also as shown in Fig. 3 and Fig. 4 they match well with calibrated TCAD results for 250nm channel length respectively. Further, the model predicted I-V characteristic with 15nm channel length shows excellent match with calibrated TCAD as shown in Fig. 5 validating the short channel models. Fig 6 highlights the asymmetric nature of the VNW device and the model matching with TCAD reflects the accuracy of parasitic models [5]. The observed asymmetry in Fig. 6 is due to larger bottom than the top electrode, resulting in lower bottom electrode resistance. For circuit analysis using compact model of VNW device, we obtain drive matched NMOS-PMOS devices as shown in Fig. 5 by increasing PMOS diameter. An inverter is implemented, whose voltage transfer characteristic and transient analysis exhibit a good match with the calibrated TCAD as shown in Fig. 7. The effect of parasitic (by varying extension length) on performance of device and two stage CMOS inverter with source Top and source Bottom [5] configurations is shown in Fig. 8 along with TCAD predicted results. The good match between compact model and TCAD highlights the accuracy of parasitic integrated compact model and its importance in understanding circuit performance. Further design of the VNW CMOS digital and analog circuits including cell library using the compact model will be presented in future study.
Accurate and fast Verilog-A compact models for transistors are one of the main pillars in circuit design and optimization using simulators. In this paper, we develop such a complete model of VNW, which include device parasitic, device asymmetry and nanoscale physical effects. Our model accurately predicts device and circuit performance, which are well matched to TCAD simulations. II.
DEVICE AND CIRCUIT RESULTS
CORE AND PARASITIC MODEL
This complete model for VNW (shown in Fig. 1), in which we incorporate our TCAD calibrated parasitic models [5] in the
This work was partially supported in part by Dept. of Science and Technology India, Project Grant No.SR/NM/NS- 149/2010 and SMDP- II, Ministry of Technology, Government of India under Project No. MIT-218ECD.
-1-
ISOCC 2015
IV.
CMOS standard cell library characterization and SRAM design, as well as analog circuit design.
CONCLUSION
In summary, a Verilog-A based unified compact model for VNW CMOS is developed including device parasitics and physical effects for circuit simulation. The model predicted characteristics match well with corresponding calibrated TCAD for long, short channel devices, including device asymmetry. The compact model can accurately reproduce
REFERENCES [1] [2] [3] [4] [5]
circuit simulation results using TCAD mixed mode simulations. The developed model can be used for VNW T
B I s o l a t i o n
SiO2
G
RT ppT
Gate Metal
CGT
DNW
gexT
Tox
T1
T2
CGB
CGC
C GTif CGBif
Metal
CGTO P2 P1 P3
C GBO
ppB
Metal / Electrical top contact
Silicon
gexB
T3
Bo Yu, et al., IEEE Trans. Elect. Devi., 54(2007) 492. J.Yang, et al., IEEE Trans. Elect. Devi., 55(2008) 2998. B. Iniguez, et al., IEEE Trans. Elect. Devi., 52(2005) 1868. BSIMCMG108.0.0, [online] www-device.eecs.berkeley.edu. S. Maheshwaram, et al.,IEEE Trans. Elect .Devi., 60(2013) 2943.
RB
Silicon
L3
STI
Substrate
Silicon
Figure 1. VNWFET 2-D view with parasitic capacitances and resistances identified [5].
Figure 2. VNWFET 3-D isometric view with individual resistance components.
Figure 4. (a) PMOS C-Vgs (at Vds=-1.0V) and (b) PMOS C-Vds (at Vgs=-1.0V). The channel length is 250nm.
Figure 6. Model consideration of source drain asymmetry and results matched to TCAD.
Figure 3. Compact model comparison with TCAD results for 250nm channel NMOS (a) Id-Vgs on log scale and (b) Id-Vds characteristics.
Figure 5. (a) Id-Vgs and (b) Id-Vds characteristic of model compared with TCAD. LG=15nm for NMOS (R=5nm) and PMOS (R=7nm).
Figure 7. (a) Inverter VTC matched with TCAD. (b) Inverter transient matched with TCAD.
TABLE I. MODELLING EQUATIONS USED IN CORE MODEL.
8πε
2
si ⎛ KT ⎞ ⎡ f α − f α ⎤ ( d ) ( s )⎦ ⎜ ⎟ L ⎝ q ⎠ ⎣ where, αd and αs are the solution of (2) at drain and source side
I ds = μ
(1)
⎛ 2 2εsi KT ⎞ 1 1− α q(Vg −Δφnew ) qV ln(1− α) − lnα + s = − − ln⎜ ⎟⎟ (2) 2 ⎜ 2 2KTαSCE 2KT αSCEα ⎝ R q ni ⎠
Figure 8. Model calculated (a) ION (b) delay compared to TCAD with change in extension length for source Top and source TABLE II. TOTAL PARASITIC RESISTANCE AND CAPACITANCE MODELS.
where, αSCE =1 for long channel and αSCE ≠ 1 for short channel ⎡ (1 − α d
C gd = 8πε si L
C gs
)
⎤ + W sd + W ds ⎥ ⎣ αd ⎦ α d ( f (α s ) − f (α d ) )
(1 − α d ) ⎢
⎡ (1 − α s ) ⎤ + W sd + W d s ⎥ (1 − α s ) ⎢ α s ⎣ ⎦ = 8πε si L α s ( f (α d ) − f (α s ) )
(3)
CGT = CGTov + CGTif + CgexT + CGTof
(5)
CGB = CGBif + CGBov + C ppB + C gexB + CGBof
(6)
RT = (4)
R tmsc 1 R tmsc 2 + R + R sp 2 ( Rtmsc1 + Rtmsc 2 ) ext
R b = R b m sc + R sh + R1 + R sp 2
-2-
(7) (8)
ISOCC 2015
Abstract— Verilog-A based unified compact model of silicon vertical nanowire FET is developed for circuit simulation, which includes: short channel, velocity saturation, mobility degradation, quantum mechanical effects and device parasitic. We include scalable TCAD calibrated parasitic resistance and capacitance models, which also consider device asymmetry due to vertical nanowire structure. The model shows excellent match with calibrated TCAD at device as well as circuit level for both long and short channel devices. Further, the model results underline the importance of parasitics on nanowire based circuit performance.
Parasitic at extremely scaled dimension play a crucial role in determining the characteristics of device. By virtue of its structure as shown in Fig.1 the VNW is an asymmetric device, which lead to different parasitic for top and bottom electrode. These parasitic are highlighted in Fig. 1 and Fig. 2 and main equation are listed in Table 2. The calibrated parasitic models proposed by us are presented in detail in [5], which are integrated into the core model.
Keywords- Parasitics, Verilog-A model, vertical nanowire FET.
I.
INTRODUCTION
The multigate devices such as FinFETs and nanowire-FET are projected to be replacement for planar CMOS due to immunity against short channel effects (SCE) for 22nm and below technology nodes. In addition to very low SCE, the vertical nanowire (VNW) shown in Fig. 1 occupies least silicon area, high on to off current ratio. The silicon nanowire is best suited for high speed and low power applications. In nanoscale regime, however, the device parasitic degrades the circuit performance and is a critical issue in device and circuit performance. In order to analyze the performance of circuits based on VNW, a unified compact model of VNW is required, which can capture both parasitic and nanoscale physical effects. The compact models for lateral NW FETs have been reported [1]-[4], however most of these models are limited in their application as they do not consider device structural parasitics. In particular no compact model for VNW MOSFET considering realistic parasitic models and device asymmetry has been reported. In absence of these parasitics, any compact model will not accurately predict device and circuit performance.
III.
The developed complete model is able to accurately reproduce the reported long channel I-V (error < 4%) and C-V (error < 6%) characteristics [1]-[2], and also as shown in Fig. 3 and Fig. 4 they match well with calibrated TCAD results for 250nm channel length respectively. Further, the model predicted I-V characteristic with 15nm channel length shows excellent match with calibrated TCAD as shown in Fig. 5 validating the short channel models. Fig 6 highlights the asymmetric nature of the VNW device and the model matching with TCAD reflects the accuracy of parasitic models [5]. The observed asymmetry in Fig. 6 is due to larger bottom than the top electrode, resulting in lower bottom electrode resistance. For circuit analysis using compact model of VNW device, we obtain drive matched NMOS-PMOS devices as shown in Fig. 5 by increasing PMOS diameter. An inverter is implemented, whose voltage transfer characteristic and transient analysis exhibit a good match with the calibrated TCAD as shown in Fig. 7. The effect of parasitic (by varying extension length) on performance of device and two stage CMOS inverter with source Top and source Bottom [5] configurations is shown in Fig. 8 along with TCAD predicted results. The good match between compact model and TCAD highlights the accuracy of parasitic integrated compact model and its importance in understanding circuit performance. Further design of the VNW CMOS digital and analog circuits including cell library using the compact model will be presented in future study.
Accurate and fast Verilog-A compact models for transistors are one of the main pillars in circuit design and optimization using simulators. In this paper, we develop such a complete model of VNW, which include device parasitic, device asymmetry and nanoscale physical effects. Our model accurately predicts device and circuit performance, which are well matched to TCAD simulations. II.
DEVICE AND CIRCUIT RESULTS
CORE AND PARASITIC MODEL
This complete model for VNW (shown in Fig. 1), in which we incorporate our TCAD calibrated parasitic models [5] in the
This work was partially supported in part by Dept. of Science and Technology India, Project Grant No.SR/NM/NS- 149/2010 and SMDP- II, Ministry of Technology, Government of India under Project No. MIT-218ECD.
-1-
ISOCC 2015
IV.
CMOS standard cell library characterization and SRAM design, as well as analog circuit design.
CONCLUSION
In summary, a Verilog-A based unified compact model for VNW CMOS is developed including device parasitics and physical effects for circuit simulation. The model predicted characteristics match well with corresponding calibrated TCAD for long, short channel devices, including device asymmetry. The compact model can accurately reproduce
REFERENCES [1] [2] [3] [4] [5]
circuit simulation results using TCAD mixed mode simulations. The developed model can be used for VNW T
B I s o l a t i o n
SiO2
G
RT ppT
Gate Metal
CGT
DNW
gexT
Tox
T1
T2
CGB
CGC
C GTif CGBif
Metal
CGTO P2 P1 P3
C GBO
ppB
Metal / Electrical top contact
Silicon
gexB
T3
Bo Yu, et al., IEEE Trans. Elect. Devi., 54(2007) 492. J.Yang, et al., IEEE Trans. Elect. Devi., 55(2008) 2998. B. Iniguez, et al., IEEE Trans. Elect. Devi., 52(2005) 1868. BSIMCMG108.0.0, [online] www-device.eecs.berkeley.edu. S. Maheshwaram, et al.,IEEE Trans. Elect .Devi., 60(2013) 2943.
RB
Silicon
L3
STI
Substrate
Silicon
Figure 1. VNWFET 2-D view with parasitic capacitances and resistances identified [5].
Figure 2. VNWFET 3-D isometric view with individual resistance components.
Figure 4. (a) PMOS C-Vgs (at Vds=-1.0V) and (b) PMOS C-Vds (at Vgs=-1.0V). The channel length is 250nm.
Figure 6. Model consideration of source drain asymmetry and results matched to TCAD.
Figure 3. Compact model comparison with TCAD results for 250nm channel NMOS (a) Id-Vgs on log scale and (b) Id-Vds characteristics.
Figure 5. (a) Id-Vgs and (b) Id-Vds characteristic of model compared with TCAD. LG=15nm for NMOS (R=5nm) and PMOS (R=7nm).
Figure 7. (a) Inverter VTC matched with TCAD. (b) Inverter transient matched with TCAD.
TABLE I. MODELLING EQUATIONS USED IN CORE MODEL.
8πε
2
si ⎛ KT ⎞ ⎡ f α − f α ⎤ ( d ) ( s )⎦ ⎜ ⎟ L ⎝ q ⎠ ⎣ where, αd and αs are the solution of (2) at drain and source side
I ds = μ
(1)
⎛ 2 2εsi KT ⎞ 1 1− α q(Vg −Δφnew ) qV ln(1− α) − lnα + s = − − ln⎜ ⎟⎟ (2) 2 ⎜ 2 2KTαSCE 2KT αSCEα ⎝ R q ni ⎠
Figure 8. Model calculated (a) ION (b) delay compared to TCAD with change in extension length for source Top and source TABLE II. TOTAL PARASITIC RESISTANCE AND CAPACITANCE MODELS.
where, αSCE =1 for long channel and αSCE ≠ 1 for short channel ⎡ (1 − α d
C gd = 8πε si L
C gs
)
⎤ + W sd + W ds ⎥ ⎣ αd ⎦ α d ( f (α s ) − f (α d ) )
(1 − α d ) ⎢
⎡ (1 − α s ) ⎤ + W sd + W d s ⎥ (1 − α s ) ⎢ α s ⎣ ⎦ = 8πε si L α s ( f (α d ) − f (α s ) )
(3)
CGT = CGTov + CGTif + CgexT + CGTof
(5)
CGB = CGBif + CGBov + C ppB + C gexB + CGBof
(6)
RT = (4)
R tmsc 1 R tmsc 2 + R + R sp 2 ( Rtmsc1 + Rtmsc 2 ) ext
R b = R b m sc + R sh + R1 + R sp 2
-2-
(7) (8)
ISOCC 2015
