Correlations between BTI-Induced Degradations ... - Semantic Scholar
IEICE TRANS. FUNDAMENTALS, VOL.E97–A, NO.12 DECEMBER 2014
2367
PAPER
Special Section on VLSI Design and CAD Algorithms
Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs Michitarou YABUUCHI†a) , Student Member, Ryo KISHIDA† , Nonmember, and Kazutoshi KOBAYASHI† , Member
SUMMARY We analyze the correlation between BTI (Bias Temperature Instability) -induced degradations and process variations. Those reliability issues are correlated. BTI is one of the most significant agingdegradations on LSIs. Threshold voltages of MOSFETs increase with time when biases stress their gates. It shows a strong effect of BTI on highly scaled LSIs in the same way as the process variations. The accurate prediction of the combinational effects is indispensable. We should analyze both aging-degradations and process variations of MOSFETs to explain the correlation. We measure frequencies of ROs (Ring Oscillators) of 65-nm process test circuits on two types of LSIs, ASICs and FPGAs. There are 98 and 837 ROs on our ASICs and FPGAs respectively. The frequencies of ROs follow gaussian distributions. We describe the highest frequency group as the “fast” conditon, the average group as the “typical” conditon and the lowest group as the “slow” conditon. We measure the aging-degradations of the ROs of the three conditions on the accelerated test. The degradations can be approximated by logarithmic function of stress time. The degradation at the “fast” condition has a higher impact on the frequency than the “slow” one. The correlation coefficient is 0.338. In this case, we can define a smaller design margin for BTI-induced degradations than that without considering the correlation because the degradation at the “slow” conditon is smaller than the average and the fast. key words: BTI, process variation, reliability
1.
Introduction
Reliability issues, such as BTI (Bias Temperature Instability) and process variations are exposed at the highly scaling process [1]. BTI is one of the most significant agingdegradations on LSIs. It was first reported in 1967 [2]. Threshold voltages of transistors are shifted by BTI for the long-term period of use. It is called NBTI (Negative BTI) that appears in PMOS transistors. Because threshold voltages of PMOS transistors increase with time when thier gates are stressed by negative bias. It is also called PBTI (Positive BTI) that appears in NMOS transistors. NBTI is known as one of dominant factors that determines life time of circuits after 65-nm process technology. PBTI emerges as a problem after 40-nm high-k metal gate process technology. They result in circuit delays and unstable performances because their effects are not negligible and avoidable. BTI is a kind of random discrete-charge-induced variations [3]. It is time-dependent phenomenon. Behavior of a single charge in the channel is becoming a significant probManuscript received March 13, 2014. Manuscript revised June 30, 2014. † The authors are with the Graduate School of Science and Technology, Kyoto Institute of Technology, Kyoto-shi, 606-8585 Japan. a) E-mail: [email protected] DOI: 10.1587/transfun.E97.A.2367
lem on heavily scaled LSIs. Characteristics of the MOSFETs are fluctuated by the charge behavior. It is called the RTN (Random Telegraph Noise). The origin of BTI is the defects trapping and detrapping carriers in gate oxide. BTI is basically the same degradation as the RTN. But it has the effect for the longer-term than RTN. BTI and process variations are becoming important reliability problems on highly scaled LSIs. Traditionally, the main source of the variation is the RDF (Random Dopant Fluctuation). It is locationdependent phenomenon. Now the main sources of the variation are random discrete-charge and RDF. The accurate prediction of the combinational effects is necessary. In this paper, we propose the correlation between BTIinduced degradations and process variations. We measure the frequencies of ROs (ring oscillators) on ASICs and FPGAs to analyze the reliability issues. We expect the frequencies are varied by the process variations according to locations on the test chips. They should follow the gaussian distribution. We focus on the groups of the highest, average and lowest frequencies. We measure the aging-degradations of the three groups on the accelerated test. We assume that the degradation at the highest frequency group is larger than one at the slowest frequency group. Because there are more carriers in the highest group transistors than the slowest one. BTI is assumed to have a large impact on the highest frequency group transistors. We examine the correlation among BTI-induced degradations and process variations. Related works are as follows. BTI-induced degradations on ASICs are discussed in [4]–[7]. BTI-induced degradations on FPGAs are discussed in [8]–[11]. Conventionally, the correlation among BTI-induced degradations and process variations are not discussed. It is important to disclose the relation between those two reliability issues. The remainder of this paper is organized as follows. Section 2 introduces our measurement methods for ASICs and FPGAs. Section 3 shows the results of the process variations and aging-degradations measurement. Section 4 discusses our results with the simulations and the analyses. Section 5 summarizes this paper. 2.
Measurement Method
In this section, we introduce the measurement setup for ROs on ASICs and FPGAs. We measure the ROs to analyze BTIinduced degradations and process variations.
c 2014 The Institute of Electronics, Information and Communication Engineers Copyright
IEICE TRANS. FUNDAMENTALS, VOL.E97–A, NO.12 DECEMBER 2014
2368
Fig. 1
Measurement equipment.
Fig. 3 Measurement circuit consists of a RO and a 16-bit counter on the FPGA.
We synthesize the configurations of the test circuit. To analyze the process variations, the configurations should cover whole logic array blocks of the FPGA. We can put the circuit in any location on the FPGA by using a corresponding configuration. Fig. 2
Structure of the Cyclone IV FPGA.
2.1 Measurement Setup The measurement setup is as follows. We use the engineering LSI tester to measure the circuits. A 65-nm process test chip contains 1764 ROs. Those ROs are divided into 18 types. These 98 ROs have different structures such as stages and wiring capacitance/resistance. We measure them at the accelerated conditon at which the power supply voltage is 2.0 V. Nominal power supply voltage is 1.2 V. A 65-nm process cyclone IV FPGA contains 1347 ROs. We measure 837 ROs of them. The details of the configurations are shown in the latter part. FPGA is mounted on DE0 NANO FPGA board which has 72 GPIO pins, a USB mini-AB port, two DC 5 V pins, and etc. The FPGA board and the DUT board on the tester are connected by the DSUB 50pin cable. The measurement equipment is shown in Fig. 1. Power supply voltage is 1.2 V, which is limited by the specification of the FPGA board. The temperature conditions are 80◦ C. Numbers of oscillation are detected by on-chip counters. It is important to minimize the control signal delays when we measure BTI. Because the degradation amount is changing in very short time. To achieve accurate measurement results, we use the LSI tester. 2.2 Configuration of ROs on FPGAs We design the ROs and the on-chip counters on the FPGAs. The structure of the Cyclone IV FPGA is shown in Fig. 2. They consist of logic array blocks which can configurate any logic circuits. Each logic array block has 16 logic elements which are the basic units of the FPGA. Figure 3 shows the measurement circuit on the FPGA. It contains a ring oscillator (RO), a four-stage divider (DIVx4) and a 16-bit counter (DIVx16).
3.
Measurement Results
In this section, we show the results of the process variations and the BTI-Induced degradations measurements. 3.1 Results of Process Variations We measure frequencies of all ring oscillators to analyze the process variations. Figure 4 shows the distributions of frequencies of 98 ROs of the same type of the structure on the ASIC. The frequencies do not follow the gaussian distribution. The reason is that the samples are 98. We describe 10 samples (10%) of the highest frequency group as the “fast” conditon, 10 samples (10%) of the average group as the “typical” conditon and 10 samples (10%) of the lowest group as the “slow” conditon. Figure 5 shows the distributions of frequencies of the ROs on the FPGA. The frequencies follow the gaussian distribution. We measure 1347 ROs which have the configurations of each location. But the automatic optimization of the design tool rewrites some configurations. Figure 5 includes only the frequencies of the original configuration ROs. We describe the 10 of the highest frequency group as the “fast” conditon, the 10 of the average group as the “typical” conditon and the 10 of the lowest group as the “slow” conditon. Note that the descriptions of the variation conditions are different from that of ASICs. BTI should be affected by the process variations. The origin of BTI is carrier-capturing and emitting activities of the defects in the gate oxide [6]. The amount of carriers is fluctuated by the process variations. Since there are more carriers in the fast conditon transistor than the slow one, BTI should has a large impact on the fast condition transistors. 3.2 Results of BTI-Induced Degradations BTI-induced degradations can be detected by measuring the
YABUUCHI et al.: CORRELATIONS BETWEEN BTI-INDUCED DEGRADATIONS AND PROCESS VARIATIONS ON ASICS AND FPGAS
2369
Fig. 4 80◦ C.
Frequency distribution of 98 ROs on the ASIC, Vdd = 2.0 V, T =
Fig. 7 Frequency degradations of fast, typical and slow conditions on the FPGA, Vdd = 1.2V, T = 80◦ C.
on the FPGA are shown in Fig. 7. Note that the x axis is a log-scale. The frequencies are the frequency of single RO of three conditions. The degradations also follow logarithmic function f (t) = −a × log(t) + b. 4.
Discussion
In this section, we discuss the simulation results of the degradations and the correlation between process variations and BTI-induced degradations. Fig. 5
Frequency distribution of ROs on FPGAs, Vdd = 1.2V, T = 80◦ C.
Fig. 6 Frequency degradations of fast, typical and slow conditions on the ASIC, Vdd = 2.0V, T = 80◦ C.
frequencies of the ROs through the degradation time. When the oscillations stop, the ROs degrade over time. We measure the frequencies of the ROs of the fast, typical and slow conditions, periodically. The ROs repeat the degradation intervals and oscillations/measurements. The total degradation time is 3600 s. The degradations of frequencies of the three conditions on the ASIC are shown in Fig. 6. Note that the x axis is a log-scale. The frequencies are averages of each variation conditon. The degradations follow logarithmic function f (t) = −a × log(t) + b. The variable a is the degradation factor. The degradation trend is increased with a. The variable b is the frequency factor. The degradations of frequencies of the three conditions
4.1 Simulation of BTI-Induced Degradations We simulate the degradations of the ROs to confirm the measurement results. The schematics of internal circuits of FPGAs are not disclosed. We analyze following two circuits instead. One of the simulation circuit is shown in Fig. 8. It is a 17-stage RO with NAND enable. The initial frequency is 1.232 GHz. The other circuit is shown in Fig. 9. It is an oscillation circuit which consists of 4-stage CMOS multiplexers. It represents a logic element chain of the FPGA. The oscillation path is A and the enable is B. The initial frequency is 3.736 GHz. The simulation setup is as follows. The transistor model is 65-nm process standard size and the temperture is 80◦ C. Threshold voltage Vth shifts from BTI-induced degradations are calculated by the trapping-detrapping model [12]. A MOSFET has N defects and each of them can be characterized by capture and emission time constants τc and τe . If a defect captures carriers, Vth of the device increases. The capture probability PC is a function of τc and τe [12]. The degradation ΔVth at degradation time t can be calculated by Eq. (1). ΔVth (t) =
N
k j (t) · μ j
(1)
j=1
When the jth defect captures carriers, k j = 1, while carriers are emitted, k j = 0. It is determined by PC . The μ is Vth shift from a single defect. Each τc , τe or μ is a statistical parameter. We use ΔVth of the average of 100 time calculations as shown in Fig. 10.
IEICE TRANS. FUNDAMENTALS, VOL.E97–A, NO.12 DECEMBER 2014
2370
Fig. 8
Simulation circuit, 17-stage ring oscillator.
Fig. 12 Fig. 9
Simulation circuit, 4-stage MUX chain.
Fig. 13 Fig. 10 model.
Simulation result of 4-stage MUX chain.
Variable a of same type ROs on the ASIC.
Threshold voltage shifts calculated by the trapping-detrapping
Fig. 14 FPGA. Fig. 11
Frequency degradation of the average of the fast conditon on the
Simulation result of 17-stage ring oscillator.
The results are shown in Figs. 11 and 12. Note that the x axis is a log-scale. The degradations follow a logarithmic function in the same way with measurement results. 4.2 Correlation among Process Variations and BTIInduced Degradations We examine a correlation between BTI-induced degradations and process variations. To compare the trends of the degradations, we focus on the variable a of the degradation function f (t) = −a × log(t) + b. If a is larger, it means the degradation has a larger impact on BTI-induced degradations.
Figure 13 shows a of the 98 ROs of the same type on the ASIC. The x axis is initial frequencies of the ROs. We calculate the correlation coefficient c of the frequencies f and a. n i=0 ( fi − favg )(ai − aavg ) = 0.338 (2) c= n n 2 2 i=0 ( fi − favg ) i=0 (ai − aavg ) Variables favg and aavg are averages of f and a respectively. It shows an increasing trend with the frequency. Figures 14–16 show the degradations of the frequencies of the fast, typical and slow condition on the FPGA respectively. They are the averages of the variation conditions. The variable a and b are shown in Table 1. It shows that a of the fast condition is the largest of all conditons.
YABUUCHI et al.: CORRELATIONS BETWEEN BTI-INDUCED DEGRADATIONS AND PROCESS VARIATIONS ON ASICS AND FPGAS
2371
dations follow logarithmic functions. The correlation coefficient of the degradation factors and the initial frequencies is 0.338 on the ASIC. The degradation factor at the “fast” condition is the largest of all conditions on the FPGA. They suggest that the BTI-induced degradation at the “fast” condition has a significant effect. In this case, we can reduce the design margin for BTI-induced degradations because the degradation at the “slow” conditon is smaller than we currently expect. Our future work is to evaluate the reliability issues on 28-nm process test chips and FPGAs. Fig. 15 Frequency degradation of the average of the typical conditon on the FPGA.
Acknowledgment This work is supported by VLSI Design and Education Center(VDEC), the University of Tokyo in collaboration with Synopsys, Inc., Cadence Design Systems, Inc. and Mentor Graphics, Inc. This work was done in “Ultra-Low Voltage Device Project” of LEAP funded and supported by METI and NEDO. References
Fig. 16 Frequency degradation of the average of the slow conditon on the FPGA. Table 1 a b
Variable a and b of three conditons on the FPGA. fast typical slow 16.31 × 10−5 9.873 × 10−5 5.267 × 10−5 1.258 1.211 1.175
Table 2 Frequency degradation predictions of both proposed and conventional models [GHz]. proposed conventional
fast 1.255 1.256
typical 1.209 1.209
slow 1.174 1.173
The BTI-induced degradation at the fast condition has a significant effect. In this case, we can reduce the design margin for BTI-induced degradations because the degradation at the “slow” conditon is smaller than the average. The degradation predictions of both the proposed and the conventional models are shown in Table 2. It shows the degradation on the “slow” condition is small when we use the proposed model. 5.
Conclusion
In this paper, we analyze the correlation between BTIinduced degradations and process variations. We analyze those reliability issues on the ASICs and the FPGAs to measure the frequencies of the ROs. The frequencies of the FPGAs follow the gaussian destribution. The frequencies of those LSIs decrease with time because of BTI. The degra-
[1] W. Wang, S. Yang, S. Bhardwaj, S. Vrudhula, F. Liu, and Y. Cao, “The impact of NBTI effect on combinational circuit: Modeling, simulation, and analysis,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.18, no.2, pp.173–183, Feb. 2010. [2] B.E. Deal, M. Sklar, A.S. Grove, and E.H. Snow, “Characteristics of the surface-state charge (Q) of thermally oxidized silicon,” J. Electrochemical Society, vol.114, p.266, 1967. [3] T. Grasser, “Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities,” Microelectronics Reliability, vol.52, no.1, pp.39–70, 2012. [4] W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu, and Y. Cao, “The impact of NBTI on the performance of combinational and sequential circuits,” Proc. 44th Annual Design Automation Conference, pp.364–369, 2007. [5] S. Pae, M. Agostinelli, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Kavalieros, K. Kuhn, M. Kuhn, J. Maiz, M. Metz, K. Mistry, C. Prasad, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, J. Thomas, C. Wiegand, and J. Wiedemer, “BTI reliability of 45 nm high-k + metal-gate process technology,” IEEE International Reliability Physics Symposium, 2008. IRPS 2008., pp.352–357, May 2008. [6] B. Kaczer, T. Grasser, J. Martin-Martinez, E. Simoen, M. Aoulaiche, P. Roussel, and G. Groeseneken, “NBTI from the perspective of defect states with widely distributed time scales,” IEEE International Reliability Physics Symposium, 2009, pp.55–60, 2009. [7] M. Yabuuchi and K. Kazutoshi, “Circuit characteristic analysis considering nbti and PBTI-induced delay degradation,” 2012 International Meeting for Future of Electron Devices, Kansai (IMFEDK2011), pp.72–73, 2012. [8] M. Yabuuchi and K. Kobayashi, “Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations,” 2010 International Conference on FieldProgrammable Technology (FPT), pp.417–420, 2010. [9] K. Ramakrishnan, S. Suresh, N. Vijaykrishnan, and M. Irwin, “Impact of NBTI on FPGAs,” 20th International Conference on VLSI Design, pp.717–722, 2007. [10] E. Stott and P.Y.K. Cheung, “Improving FPGA reliability with wearlevelling,” 2011 International Conference on Field Programmable Logic and Applications (FPL), pp.323–328, 2011. [11] A. Amouri and M. Tahoori, “High-level aging estimation for FPGA-
IEICE TRANS. FUNDAMENTALS, VOL.E97–A, NO.12 DECEMBER 2014
2372
mapped designs,” 2012 22nd International Conference on Field Programmable Logic and Applications (FPL), pp.284–291, 2012. [12] B. Kaczer, S. Mahato, V. Valduga de Almeida Camargo, M. Toledano-Luque, P.J. Roussel, T. Grasser, F. Catthoor, P. Dobrovolny, P. Zuber, G. Wirth, and G. Groeseneken, “Atomistic approach to variability of bias-temperature instability in circuit simulation,” IEEE International Reliability Physics Symposium, 2011, pp.XT.3.1–XT.3.5, 2011.
Michitarou Yabuuchi was born in Shiga, Japan in 1987. He received the B.E. and M.E. degrees in Electronics and System Engineering from Kyoto Institute of Technology, Kyoto, Japan, in 2010, 2012, respectively. He is presently a doctral course student at Kyoto Institute of Technology. His interests are in reconfigurable circuit, reliability issues, design automation and test structure. He recieved a young researcher’s award of IEICE in 2011. He is a member of IEICE and IEEE.
Ryo Kishida was born in Kyoto, Japan in 1990. He received the B.E. degrees in Electronics and System Engineering from Kyoto Institute of Technology, Kyoto, Japan, in 2013. He is presently a master course student at Kyoto Institute of Technology. His interests are in reconfigurable circuit, reliability issues, design automation and test structure.
Kazutoshi Kobayashi was born in Kyoto, Japan in 1968. He received the B.E., M.E. and Dr. Eng. degrees in Electronic Engineering from Kyoto University, Kyoto, Japan, in 1991, 1993, 1999, respectively. His interests are in reconfigurable architectures utilizing device variations, architectures and implementations of parallel computers, and reliability issues of current and future VLSIs. He was an Assistant Professor (1993–2001) and an Associate Professor (2001– 2002, 2004–2009) in Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University. From 2002 to 2004, he was an Associate Professor of VLSI Design and Education Center (VDEC) at the University of Tokyo. Since 2009, he is a Professor in Kyoto Institute of Technology. He received a best paper award of IEICE in 2009. He is a member of IEEE, IEICE and IPSJ.
2367
PAPER
Special Section on VLSI Design and CAD Algorithms
Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs Michitarou YABUUCHI†a) , Student Member, Ryo KISHIDA† , Nonmember, and Kazutoshi KOBAYASHI† , Member
SUMMARY We analyze the correlation between BTI (Bias Temperature Instability) -induced degradations and process variations. Those reliability issues are correlated. BTI is one of the most significant agingdegradations on LSIs. Threshold voltages of MOSFETs increase with time when biases stress their gates. It shows a strong effect of BTI on highly scaled LSIs in the same way as the process variations. The accurate prediction of the combinational effects is indispensable. We should analyze both aging-degradations and process variations of MOSFETs to explain the correlation. We measure frequencies of ROs (Ring Oscillators) of 65-nm process test circuits on two types of LSIs, ASICs and FPGAs. There are 98 and 837 ROs on our ASICs and FPGAs respectively. The frequencies of ROs follow gaussian distributions. We describe the highest frequency group as the “fast” conditon, the average group as the “typical” conditon and the lowest group as the “slow” conditon. We measure the aging-degradations of the ROs of the three conditions on the accelerated test. The degradations can be approximated by logarithmic function of stress time. The degradation at the “fast” condition has a higher impact on the frequency than the “slow” one. The correlation coefficient is 0.338. In this case, we can define a smaller design margin for BTI-induced degradations than that without considering the correlation because the degradation at the “slow” conditon is smaller than the average and the fast. key words: BTI, process variation, reliability
1.
Introduction
Reliability issues, such as BTI (Bias Temperature Instability) and process variations are exposed at the highly scaling process [1]. BTI is one of the most significant agingdegradations on LSIs. It was first reported in 1967 [2]. Threshold voltages of transistors are shifted by BTI for the long-term period of use. It is called NBTI (Negative BTI) that appears in PMOS transistors. Because threshold voltages of PMOS transistors increase with time when thier gates are stressed by negative bias. It is also called PBTI (Positive BTI) that appears in NMOS transistors. NBTI is known as one of dominant factors that determines life time of circuits after 65-nm process technology. PBTI emerges as a problem after 40-nm high-k metal gate process technology. They result in circuit delays and unstable performances because their effects are not negligible and avoidable. BTI is a kind of random discrete-charge-induced variations [3]. It is time-dependent phenomenon. Behavior of a single charge in the channel is becoming a significant probManuscript received March 13, 2014. Manuscript revised June 30, 2014. † The authors are with the Graduate School of Science and Technology, Kyoto Institute of Technology, Kyoto-shi, 606-8585 Japan. a) E-mail: [email protected] DOI: 10.1587/transfun.E97.A.2367
lem on heavily scaled LSIs. Characteristics of the MOSFETs are fluctuated by the charge behavior. It is called the RTN (Random Telegraph Noise). The origin of BTI is the defects trapping and detrapping carriers in gate oxide. BTI is basically the same degradation as the RTN. But it has the effect for the longer-term than RTN. BTI and process variations are becoming important reliability problems on highly scaled LSIs. Traditionally, the main source of the variation is the RDF (Random Dopant Fluctuation). It is locationdependent phenomenon. Now the main sources of the variation are random discrete-charge and RDF. The accurate prediction of the combinational effects is necessary. In this paper, we propose the correlation between BTIinduced degradations and process variations. We measure the frequencies of ROs (ring oscillators) on ASICs and FPGAs to analyze the reliability issues. We expect the frequencies are varied by the process variations according to locations on the test chips. They should follow the gaussian distribution. We focus on the groups of the highest, average and lowest frequencies. We measure the aging-degradations of the three groups on the accelerated test. We assume that the degradation at the highest frequency group is larger than one at the slowest frequency group. Because there are more carriers in the highest group transistors than the slowest one. BTI is assumed to have a large impact on the highest frequency group transistors. We examine the correlation among BTI-induced degradations and process variations. Related works are as follows. BTI-induced degradations on ASICs are discussed in [4]–[7]. BTI-induced degradations on FPGAs are discussed in [8]–[11]. Conventionally, the correlation among BTI-induced degradations and process variations are not discussed. It is important to disclose the relation between those two reliability issues. The remainder of this paper is organized as follows. Section 2 introduces our measurement methods for ASICs and FPGAs. Section 3 shows the results of the process variations and aging-degradations measurement. Section 4 discusses our results with the simulations and the analyses. Section 5 summarizes this paper. 2.
Measurement Method
In this section, we introduce the measurement setup for ROs on ASICs and FPGAs. We measure the ROs to analyze BTIinduced degradations and process variations.
c 2014 The Institute of Electronics, Information and Communication Engineers Copyright
IEICE TRANS. FUNDAMENTALS, VOL.E97–A, NO.12 DECEMBER 2014
2368
Fig. 1
Measurement equipment.
Fig. 3 Measurement circuit consists of a RO and a 16-bit counter on the FPGA.
We synthesize the configurations of the test circuit. To analyze the process variations, the configurations should cover whole logic array blocks of the FPGA. We can put the circuit in any location on the FPGA by using a corresponding configuration. Fig. 2
Structure of the Cyclone IV FPGA.
2.1 Measurement Setup The measurement setup is as follows. We use the engineering LSI tester to measure the circuits. A 65-nm process test chip contains 1764 ROs. Those ROs are divided into 18 types. These 98 ROs have different structures such as stages and wiring capacitance/resistance. We measure them at the accelerated conditon at which the power supply voltage is 2.0 V. Nominal power supply voltage is 1.2 V. A 65-nm process cyclone IV FPGA contains 1347 ROs. We measure 837 ROs of them. The details of the configurations are shown in the latter part. FPGA is mounted on DE0 NANO FPGA board which has 72 GPIO pins, a USB mini-AB port, two DC 5 V pins, and etc. The FPGA board and the DUT board on the tester are connected by the DSUB 50pin cable. The measurement equipment is shown in Fig. 1. Power supply voltage is 1.2 V, which is limited by the specification of the FPGA board. The temperature conditions are 80◦ C. Numbers of oscillation are detected by on-chip counters. It is important to minimize the control signal delays when we measure BTI. Because the degradation amount is changing in very short time. To achieve accurate measurement results, we use the LSI tester. 2.2 Configuration of ROs on FPGAs We design the ROs and the on-chip counters on the FPGAs. The structure of the Cyclone IV FPGA is shown in Fig. 2. They consist of logic array blocks which can configurate any logic circuits. Each logic array block has 16 logic elements which are the basic units of the FPGA. Figure 3 shows the measurement circuit on the FPGA. It contains a ring oscillator (RO), a four-stage divider (DIVx4) and a 16-bit counter (DIVx16).
3.
Measurement Results
In this section, we show the results of the process variations and the BTI-Induced degradations measurements. 3.1 Results of Process Variations We measure frequencies of all ring oscillators to analyze the process variations. Figure 4 shows the distributions of frequencies of 98 ROs of the same type of the structure on the ASIC. The frequencies do not follow the gaussian distribution. The reason is that the samples are 98. We describe 10 samples (10%) of the highest frequency group as the “fast” conditon, 10 samples (10%) of the average group as the “typical” conditon and 10 samples (10%) of the lowest group as the “slow” conditon. Figure 5 shows the distributions of frequencies of the ROs on the FPGA. The frequencies follow the gaussian distribution. We measure 1347 ROs which have the configurations of each location. But the automatic optimization of the design tool rewrites some configurations. Figure 5 includes only the frequencies of the original configuration ROs. We describe the 10 of the highest frequency group as the “fast” conditon, the 10 of the average group as the “typical” conditon and the 10 of the lowest group as the “slow” conditon. Note that the descriptions of the variation conditions are different from that of ASICs. BTI should be affected by the process variations. The origin of BTI is carrier-capturing and emitting activities of the defects in the gate oxide [6]. The amount of carriers is fluctuated by the process variations. Since there are more carriers in the fast conditon transistor than the slow one, BTI should has a large impact on the fast condition transistors. 3.2 Results of BTI-Induced Degradations BTI-induced degradations can be detected by measuring the
YABUUCHI et al.: CORRELATIONS BETWEEN BTI-INDUCED DEGRADATIONS AND PROCESS VARIATIONS ON ASICS AND FPGAS
2369
Fig. 4 80◦ C.
Frequency distribution of 98 ROs on the ASIC, Vdd = 2.0 V, T =
Fig. 7 Frequency degradations of fast, typical and slow conditions on the FPGA, Vdd = 1.2V, T = 80◦ C.
on the FPGA are shown in Fig. 7. Note that the x axis is a log-scale. The frequencies are the frequency of single RO of three conditions. The degradations also follow logarithmic function f (t) = −a × log(t) + b. 4.
Discussion
In this section, we discuss the simulation results of the degradations and the correlation between process variations and BTI-induced degradations. Fig. 5
Frequency distribution of ROs on FPGAs, Vdd = 1.2V, T = 80◦ C.
Fig. 6 Frequency degradations of fast, typical and slow conditions on the ASIC, Vdd = 2.0V, T = 80◦ C.
frequencies of the ROs through the degradation time. When the oscillations stop, the ROs degrade over time. We measure the frequencies of the ROs of the fast, typical and slow conditions, periodically. The ROs repeat the degradation intervals and oscillations/measurements. The total degradation time is 3600 s. The degradations of frequencies of the three conditions on the ASIC are shown in Fig. 6. Note that the x axis is a log-scale. The frequencies are averages of each variation conditon. The degradations follow logarithmic function f (t) = −a × log(t) + b. The variable a is the degradation factor. The degradation trend is increased with a. The variable b is the frequency factor. The degradations of frequencies of the three conditions
4.1 Simulation of BTI-Induced Degradations We simulate the degradations of the ROs to confirm the measurement results. The schematics of internal circuits of FPGAs are not disclosed. We analyze following two circuits instead. One of the simulation circuit is shown in Fig. 8. It is a 17-stage RO with NAND enable. The initial frequency is 1.232 GHz. The other circuit is shown in Fig. 9. It is an oscillation circuit which consists of 4-stage CMOS multiplexers. It represents a logic element chain of the FPGA. The oscillation path is A and the enable is B. The initial frequency is 3.736 GHz. The simulation setup is as follows. The transistor model is 65-nm process standard size and the temperture is 80◦ C. Threshold voltage Vth shifts from BTI-induced degradations are calculated by the trapping-detrapping model [12]. A MOSFET has N defects and each of them can be characterized by capture and emission time constants τc and τe . If a defect captures carriers, Vth of the device increases. The capture probability PC is a function of τc and τe [12]. The degradation ΔVth at degradation time t can be calculated by Eq. (1). ΔVth (t) =
N
k j (t) · μ j
(1)
j=1
When the jth defect captures carriers, k j = 1, while carriers are emitted, k j = 0. It is determined by PC . The μ is Vth shift from a single defect. Each τc , τe or μ is a statistical parameter. We use ΔVth of the average of 100 time calculations as shown in Fig. 10.
IEICE TRANS. FUNDAMENTALS, VOL.E97–A, NO.12 DECEMBER 2014
2370
Fig. 8
Simulation circuit, 17-stage ring oscillator.
Fig. 12 Fig. 9
Simulation circuit, 4-stage MUX chain.
Fig. 13 Fig. 10 model.
Simulation result of 4-stage MUX chain.
Variable a of same type ROs on the ASIC.
Threshold voltage shifts calculated by the trapping-detrapping
Fig. 14 FPGA. Fig. 11
Frequency degradation of the average of the fast conditon on the
Simulation result of 17-stage ring oscillator.
The results are shown in Figs. 11 and 12. Note that the x axis is a log-scale. The degradations follow a logarithmic function in the same way with measurement results. 4.2 Correlation among Process Variations and BTIInduced Degradations We examine a correlation between BTI-induced degradations and process variations. To compare the trends of the degradations, we focus on the variable a of the degradation function f (t) = −a × log(t) + b. If a is larger, it means the degradation has a larger impact on BTI-induced degradations.
Figure 13 shows a of the 98 ROs of the same type on the ASIC. The x axis is initial frequencies of the ROs. We calculate the correlation coefficient c of the frequencies f and a. n i=0 ( fi − favg )(ai − aavg ) = 0.338 (2) c= n n 2 2 i=0 ( fi − favg ) i=0 (ai − aavg ) Variables favg and aavg are averages of f and a respectively. It shows an increasing trend with the frequency. Figures 14–16 show the degradations of the frequencies of the fast, typical and slow condition on the FPGA respectively. They are the averages of the variation conditions. The variable a and b are shown in Table 1. It shows that a of the fast condition is the largest of all conditons.
YABUUCHI et al.: CORRELATIONS BETWEEN BTI-INDUCED DEGRADATIONS AND PROCESS VARIATIONS ON ASICS AND FPGAS
2371
dations follow logarithmic functions. The correlation coefficient of the degradation factors and the initial frequencies is 0.338 on the ASIC. The degradation factor at the “fast” condition is the largest of all conditions on the FPGA. They suggest that the BTI-induced degradation at the “fast” condition has a significant effect. In this case, we can reduce the design margin for BTI-induced degradations because the degradation at the “slow” conditon is smaller than we currently expect. Our future work is to evaluate the reliability issues on 28-nm process test chips and FPGAs. Fig. 15 Frequency degradation of the average of the typical conditon on the FPGA.
Acknowledgment This work is supported by VLSI Design and Education Center(VDEC), the University of Tokyo in collaboration with Synopsys, Inc., Cadence Design Systems, Inc. and Mentor Graphics, Inc. This work was done in “Ultra-Low Voltage Device Project” of LEAP funded and supported by METI and NEDO. References
Fig. 16 Frequency degradation of the average of the slow conditon on the FPGA. Table 1 a b
Variable a and b of three conditons on the FPGA. fast typical slow 16.31 × 10−5 9.873 × 10−5 5.267 × 10−5 1.258 1.211 1.175
Table 2 Frequency degradation predictions of both proposed and conventional models [GHz]. proposed conventional
fast 1.255 1.256
typical 1.209 1.209
slow 1.174 1.173
The BTI-induced degradation at the fast condition has a significant effect. In this case, we can reduce the design margin for BTI-induced degradations because the degradation at the “slow” conditon is smaller than the average. The degradation predictions of both the proposed and the conventional models are shown in Table 2. It shows the degradation on the “slow” condition is small when we use the proposed model. 5.
Conclusion
In this paper, we analyze the correlation between BTIinduced degradations and process variations. We analyze those reliability issues on the ASICs and the FPGAs to measure the frequencies of the ROs. The frequencies of the FPGAs follow the gaussian destribution. The frequencies of those LSIs decrease with time because of BTI. The degra-
[1] W. Wang, S. Yang, S. Bhardwaj, S. Vrudhula, F. Liu, and Y. Cao, “The impact of NBTI effect on combinational circuit: Modeling, simulation, and analysis,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.18, no.2, pp.173–183, Feb. 2010. [2] B.E. Deal, M. Sklar, A.S. Grove, and E.H. Snow, “Characteristics of the surface-state charge (Q) of thermally oxidized silicon,” J. Electrochemical Society, vol.114, p.266, 1967. [3] T. Grasser, “Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities,” Microelectronics Reliability, vol.52, no.1, pp.39–70, 2012. [4] W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, S. Vrudhula, F. Liu, and Y. Cao, “The impact of NBTI on the performance of combinational and sequential circuits,” Proc. 44th Annual Design Automation Conference, pp.364–369, 2007. [5] S. Pae, M. Agostinelli, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Kavalieros, K. Kuhn, M. Kuhn, J. Maiz, M. Metz, K. Mistry, C. Prasad, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, J. Thomas, C. Wiegand, and J. Wiedemer, “BTI reliability of 45 nm high-k + metal-gate process technology,” IEEE International Reliability Physics Symposium, 2008. IRPS 2008., pp.352–357, May 2008. [6] B. Kaczer, T. Grasser, J. Martin-Martinez, E. Simoen, M. Aoulaiche, P. Roussel, and G. Groeseneken, “NBTI from the perspective of defect states with widely distributed time scales,” IEEE International Reliability Physics Symposium, 2009, pp.55–60, 2009. [7] M. Yabuuchi and K. Kazutoshi, “Circuit characteristic analysis considering nbti and PBTI-induced delay degradation,” 2012 International Meeting for Future of Electron Devices, Kansai (IMFEDK2011), pp.72–73, 2012. [8] M. Yabuuchi and K. Kobayashi, “Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations,” 2010 International Conference on FieldProgrammable Technology (FPT), pp.417–420, 2010. [9] K. Ramakrishnan, S. Suresh, N. Vijaykrishnan, and M. Irwin, “Impact of NBTI on FPGAs,” 20th International Conference on VLSI Design, pp.717–722, 2007. [10] E. Stott and P.Y.K. Cheung, “Improving FPGA reliability with wearlevelling,” 2011 International Conference on Field Programmable Logic and Applications (FPL), pp.323–328, 2011. [11] A. Amouri and M. Tahoori, “High-level aging estimation for FPGA-
IEICE TRANS. FUNDAMENTALS, VOL.E97–A, NO.12 DECEMBER 2014
2372
mapped designs,” 2012 22nd International Conference on Field Programmable Logic and Applications (FPL), pp.284–291, 2012. [12] B. Kaczer, S. Mahato, V. Valduga de Almeida Camargo, M. Toledano-Luque, P.J. Roussel, T. Grasser, F. Catthoor, P. Dobrovolny, P. Zuber, G. Wirth, and G. Groeseneken, “Atomistic approach to variability of bias-temperature instability in circuit simulation,” IEEE International Reliability Physics Symposium, 2011, pp.XT.3.1–XT.3.5, 2011.
Michitarou Yabuuchi was born in Shiga, Japan in 1987. He received the B.E. and M.E. degrees in Electronics and System Engineering from Kyoto Institute of Technology, Kyoto, Japan, in 2010, 2012, respectively. He is presently a doctral course student at Kyoto Institute of Technology. His interests are in reconfigurable circuit, reliability issues, design automation and test structure. He recieved a young researcher’s award of IEICE in 2011. He is a member of IEICE and IEEE.
Ryo Kishida was born in Kyoto, Japan in 1990. He received the B.E. degrees in Electronics and System Engineering from Kyoto Institute of Technology, Kyoto, Japan, in 2013. He is presently a master course student at Kyoto Institute of Technology. His interests are in reconfigurable circuit, reliability issues, design automation and test structure.
Kazutoshi Kobayashi was born in Kyoto, Japan in 1968. He received the B.E., M.E. and Dr. Eng. degrees in Electronic Engineering from Kyoto University, Kyoto, Japan, in 1991, 1993, 1999, respectively. His interests are in reconfigurable architectures utilizing device variations, architectures and implementations of parallel computers, and reliability issues of current and future VLSIs. He was an Assistant Professor (1993–2001) and an Associate Professor (2001– 2002, 2004–2009) in Department of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University. From 2002 to 2004, he was an Associate Professor of VLSI Design and Education Center (VDEC) at the University of Tokyo. Since 2009, he is a Professor in Kyoto Institute of Technology. He received a best paper award of IEICE in 2009. He is a member of IEEE, IEICE and IPSJ.
