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Decoupling Capacitor Design Strategy for Minimizing Supply Noise of Ultra Low Voltage Circuits Mingoo Seok Department of Electrical Engineering, Columbia University [email protected] ous current, reducing fluctuations of supply voltage. Since a large amount of decap, e.g. 10× the switching capacitance, is typically needed [1], the gate capacitors of MOSFETs are often used to maximize capacitance density and thus reduce area overhead. However, the gate capacitance of MOSFETs reduces as we scale down supply voltage near or below Vth since the inversion layers of MOSFETs are not completely formed at these voltage regimes [2]. Figure 1 shows that the capacitance of decaps, which are provided in a 65nm standard-cell library, reduces by up to 2.5× at lower supply voltages, which can incur a significant amount of area overhead.
ABSTRACT Supply noise is a critical problem for the robust operation of integrated circuits at ultra low voltage regimes. Although decoupling capacitance is a traditional solution, the reduction of gate capacitance at subthreshold voltage can cause area overhead. In this paper, we propose a decoupling capacitor design strategy to reduce area overhead. The strategy consists of two parts: 1) enhancing gate capacitance through circuit optimizations and 2) using remote decoupling capacitors. Remote decoupling capacitors, which can be placed far from the block to compensate, can minimize the area overhead of the capacitance-enhancing optimizations. They also exploit less utilizable silicon area. The proposed strategy improves the capacitance density by 6.1× without extra process steps, compared to the conventional approach. The gained robustness may be traded off for higher energy efficiency.
Norm. capacitance
4.5
Categories and Subject Descriptors B.7 [Integrated Circuits]: General General Terms: Design Keywords: ultra-low power, subthreshold operation, ultra low voltage operation, supply noise, decoupling capacitor
1. Introduction Recently ultra low voltage (ULV) operation, where the supply voltage of metal oxide semiconductor field effect transistors (MOSFET) is scaled down to near or below transistor threshold voltage (Vth), has gained a significant amount of attention due to the large (10-20×) energy savings [10][11]. ULV operation can benefit a variety of energy-constrained systems for increasing battery lifetime and reducing the volume of power sources. The applications range from implantable medical devices, to infrastructure and environment monitoring systems, to active radio frequency identification (RFID) tags. However, integrated circuits (IC) operating at ULV regimes become more sensitive to various sources of noise. Especially, noise on the supply voltage should be minimized since it can cause robustness and performance degradations, which can affect the minimum functional supply voltage (Vmin) for both logic and memory circuits. For mitigating supply noise, traditionally, decoupling capa-
4.0
tox1 tox2 tox3 tox13 orders of magnitude at the same amount of Cdecap. This also implies that smaller amount of decaps have a higher resilience against Rdist. As shown in Figure 8, with 10kȍ resistance, the design with 25pF has only 2× capacitance density. We also apply length optimization (denoted as length in Figure 10), NFETonly design (NFET in Figure 10), and consequent area savings (spacing1, spacing2 in Figure 10), which collectively provide an additional 1.85× improvement in capacitance density. All the techniques that can be used in standard cell layouts yield a 3.7× improvement, compared to the baseline design.
AE =
h⋅w (odct + 2 ⋅ (t 2od + sde) + w) ⋅ ( p 2 p + 2 ⋅ poe + h) where Lcrit > odct + 2 ⋅ (t 2od + sde) + w
[EQ3]
Figure 11. An example decap design without adhering to standard cell layout With the freedom in layout, accumulation-mode capacitors with n+ poly on n-well structure can be used for decap design. Due to the n-well and guard ring for mitigating substrate noise, it can have a lower area efficiency of ~87%. However, the effective capacitance density is slightly better than inversionmode capacitors due to higher capacitance per oxide area. In addition, the accumulation-mode capacitors maintain almost the same capacitance density (~6% degradation) at ~200mV while inversion-mode decaps exhibit 42% lower density compared to Vdd=0.35V. This makes accumulation-mode decaps
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an attractive option for designing remote decaps at ULV regimes. Additionally, multi-layer metal-oxide-metal capacitor can be stacked on top of the optimized gate capacitors for boosting capacitor density. We add a metal-oxide-metal capacitor using layer 2 to 5 to the accumulation mode capacitor, which improves capacitance density by 16% (denoted as MOM(2-5) in Figure 10). Finally, another metal-based capacitor, metalinsulator-metal (MIM) capacitor can be stacked at the cost of extra masks. MIM capacitors provide extra 35% improvement in capacitance density. Overall, these design strategies can save silicon area by improving capacitance density by 6.1× without an extra mask, and 8.2× with an extra mask at Vdd=0.35V.
References [1] P. Larsson, “Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance,” IEEE Journal of SolidState Circuits, Vol. 32, no.4, pp.574-576, Apr, 1997 [2] D. Vasileska, D. K. Schroder, D. K. Ferry, “Scaled silicon MOSFET’s: degradation of the total gate capacitance,” IEEE Transaction on Electron Devices, vol.44, no.4, Apr 1997 [3] E. Seevinck et al., “Static noise margin analysis of MOS SRAM cells,” IEEE Journal of Solid-State Circuits, vol. sc22, no.5, pp.748-754, Oct. 1987 [4] M. Seok, et al., “Analysis and optimization of sleep mode in subthreshold circuit design,” ACM/IEEE Design Automation Conference, 2007 [5] G. Chen, et al, “Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells,” IEEE International. Solid-State Circuits Conference, pp.288-289, 2010 [6] J. Kil, et al, “A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting,” IEEE International Symposium on Low Power Electronics and Design, pp.67-72, Aug, 2006 [7] C.-Y. Lu, J.M. Sung, “Reverse short-channel effects on threshold voltage in submicrometer scaled devices,” IEEE Electron Device Letters, vol.10, issue.10, pp.446-448, Oct. 1989 [8] L.A. Akers, “The inverse narrow width effect,” IEEE Electron Device Letters, vol.7, issue.7, pp.419-421, Jul. 1986 [9] T. Soorapanth, et al., “Analysis and optimization of accumulation-mode varactor for RF ICs,” IEEE Symposium on VLSI circuits, 1998 [10] B. Zhai, et al, “Theoretical and practical limits on dynamic voltage scaling”, ACM/IEEE Design Automation Conference, 2004 [11] B. Calhoun, et al, “Characterizing and modeling minimum energy operation for subthreshold circuits”, IEEE International Symposium on Low Power Electronics and Design, 2004 [12] D. Bol, D. Flandre, J.-D. Legat, “Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits,” IEEE International Symposium on Low Power Electronics and Design, 2009 [13] A. Agarwal, H. Li, K. Roy, “DRG-cache: a data retention gated-ground cache for low power,” ACM/IEEE Design Automation Conference, 2002 [14] B.C. Paul, “Device optimization for digital subthreshold logic operation, “IEEE Transaction on Electron Devices, vol.52, no.2, pp.237-247, Feb. 2005. [15] A. Kahng, P. Sharma, R. O. Topaloglu, “Exploiting STI stress for performance,” IEEE International Conference on Computer-aided Design, 2007 [16] V. Joshi, B. Cline, D. Sylvester, D. Blaauw, K. Agarwal, “Stress aware layout optimization,” IEEE International Symposium on Physical Design, 2008 [17] T. Sakurai, A.R. Newton, “Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas,” IEEE Journal of Solid-State Circuits, vol. 25, issue 2, pp.584-594, 1990 [18] P. Andreani, S. Mattison, “On the use of MOS varactors in RF VCO’s,” IEEE Journal of Solid-State Circuits, vol.35 no.6, pp.905-910, Jun 2000
1.0 off-chip capacitor preferred
0.6 0.4 0.2 0.0
10X savings in standby power
Wpgs [%]
0.8
100p
1n 10n Decaps [F]
100n
Figure 12. Standby power savings with remote decaps at iso-performance. The improved decap can be used for mitigating the supply noise induced by PGSs. The reduced supply noise enables the use of even smaller PGSs, which in turn can achieve a significant amount of standby power reduction. Figure 12 shows the allowed size of PGSs at different values of decaps. At the design points in the line, the main circuits operate at the same clock frequency. Although an on-chip decap larger than 1nF may not be feasible due to large silicon area, we can easily use off-chip capacitors since decaps at ULV regimes are more tolerant to the resistance of the path.
6. Conclusions In this paper, we investigate the design strategy for decaps at ULV regimes in order to mitigate the degradation of gate decoupling capacitance at lower supply voltage. The proposed decap design strategy of using capacitance-enhanced remote decaps reduces the area overhead by 6.1-8.2×, compared to conventional design approaches. When used in a design with PGSs, it can reduce standby power consumption through improved robustness against supply noise.
Acknowledgement
– the author appreciate the valuable discussion with Gregory K. Chen at Intel.
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ABSTRACT Supply noise is a critical problem for the robust operation of integrated circuits at ultra low voltage regimes. Although decoupling capacitance is a traditional solution, the reduction of gate capacitance at subthreshold voltage can cause area overhead. In this paper, we propose a decoupling capacitor design strategy to reduce area overhead. The strategy consists of two parts: 1) enhancing gate capacitance through circuit optimizations and 2) using remote decoupling capacitors. Remote decoupling capacitors, which can be placed far from the block to compensate, can minimize the area overhead of the capacitance-enhancing optimizations. They also exploit less utilizable silicon area. The proposed strategy improves the capacitance density by 6.1× without extra process steps, compared to the conventional approach. The gained robustness may be traded off for higher energy efficiency.
Norm. capacitance
4.5
Categories and Subject Descriptors B.7 [Integrated Circuits]: General General Terms: Design Keywords: ultra-low power, subthreshold operation, ultra low voltage operation, supply noise, decoupling capacitor
1. Introduction Recently ultra low voltage (ULV) operation, where the supply voltage of metal oxide semiconductor field effect transistors (MOSFET) is scaled down to near or below transistor threshold voltage (Vth), has gained a significant amount of attention due to the large (10-20×) energy savings [10][11]. ULV operation can benefit a variety of energy-constrained systems for increasing battery lifetime and reducing the volume of power sources. The applications range from implantable medical devices, to infrastructure and environment monitoring systems, to active radio frequency identification (RFID) tags. However, integrated circuits (IC) operating at ULV regimes become more sensitive to various sources of noise. Especially, noise on the supply voltage should be minimized since it can cause robustness and performance degradations, which can affect the minimum functional supply voltage (Vmin) for both logic and memory circuits. For mitigating supply noise, traditionally, decoupling capa-
4.0
tox1 tox2 tox3 tox13 orders of magnitude at the same amount of Cdecap. This also implies that smaller amount of decaps have a higher resilience against Rdist. As shown in Figure 8, with 10kȍ resistance, the design with 25pF has only 2× capacitance density. We also apply length optimization (denoted as length in Figure 10), NFETonly design (NFET in Figure 10), and consequent area savings (spacing1, spacing2 in Figure 10), which collectively provide an additional 1.85× improvement in capacitance density. All the techniques that can be used in standard cell layouts yield a 3.7× improvement, compared to the baseline design.
AE =
h⋅w (odct + 2 ⋅ (t 2od + sde) + w) ⋅ ( p 2 p + 2 ⋅ poe + h) where Lcrit > odct + 2 ⋅ (t 2od + sde) + w
[EQ3]
Figure 11. An example decap design without adhering to standard cell layout With the freedom in layout, accumulation-mode capacitors with n+ poly on n-well structure can be used for decap design. Due to the n-well and guard ring for mitigating substrate noise, it can have a lower area efficiency of ~87%. However, the effective capacitance density is slightly better than inversionmode capacitors due to higher capacitance per oxide area. In addition, the accumulation-mode capacitors maintain almost the same capacitance density (~6% degradation) at ~200mV while inversion-mode decaps exhibit 42% lower density compared to Vdd=0.35V. This makes accumulation-mode decaps
972
an attractive option for designing remote decaps at ULV regimes. Additionally, multi-layer metal-oxide-metal capacitor can be stacked on top of the optimized gate capacitors for boosting capacitor density. We add a metal-oxide-metal capacitor using layer 2 to 5 to the accumulation mode capacitor, which improves capacitance density by 16% (denoted as MOM(2-5) in Figure 10). Finally, another metal-based capacitor, metalinsulator-metal (MIM) capacitor can be stacked at the cost of extra masks. MIM capacitors provide extra 35% improvement in capacitance density. Overall, these design strategies can save silicon area by improving capacitance density by 6.1× without an extra mask, and 8.2× with an extra mask at Vdd=0.35V.
References [1] P. Larsson, “Parasitic resistance in an MOS transistor used as on-chip decoupling capacitance,” IEEE Journal of SolidState Circuits, Vol. 32, no.4, pp.574-576, Apr, 1997 [2] D. Vasileska, D. K. Schroder, D. K. Ferry, “Scaled silicon MOSFET’s: degradation of the total gate capacitance,” IEEE Transaction on Electron Devices, vol.44, no.4, Apr 1997 [3] E. Seevinck et al., “Static noise margin analysis of MOS SRAM cells,” IEEE Journal of Solid-State Circuits, vol. sc22, no.5, pp.748-754, Oct. 1987 [4] M. Seok, et al., “Analysis and optimization of sleep mode in subthreshold circuit design,” ACM/IEEE Design Automation Conference, 2007 [5] G. Chen, et al, “Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells,” IEEE International. Solid-State Circuits Conference, pp.288-289, 2010 [6] J. Kil, et al, “A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting,” IEEE International Symposium on Low Power Electronics and Design, pp.67-72, Aug, 2006 [7] C.-Y. Lu, J.M. Sung, “Reverse short-channel effects on threshold voltage in submicrometer scaled devices,” IEEE Electron Device Letters, vol.10, issue.10, pp.446-448, Oct. 1989 [8] L.A. Akers, “The inverse narrow width effect,” IEEE Electron Device Letters, vol.7, issue.7, pp.419-421, Jul. 1986 [9] T. Soorapanth, et al., “Analysis and optimization of accumulation-mode varactor for RF ICs,” IEEE Symposium on VLSI circuits, 1998 [10] B. Zhai, et al, “Theoretical and practical limits on dynamic voltage scaling”, ACM/IEEE Design Automation Conference, 2004 [11] B. Calhoun, et al, “Characterizing and modeling minimum energy operation for subthreshold circuits”, IEEE International Symposium on Low Power Electronics and Design, 2004 [12] D. Bol, D. Flandre, J.-D. Legat, “Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits,” IEEE International Symposium on Low Power Electronics and Design, 2009 [13] A. Agarwal, H. Li, K. Roy, “DRG-cache: a data retention gated-ground cache for low power,” ACM/IEEE Design Automation Conference, 2002 [14] B.C. Paul, “Device optimization for digital subthreshold logic operation, “IEEE Transaction on Electron Devices, vol.52, no.2, pp.237-247, Feb. 2005. [15] A. Kahng, P. Sharma, R. O. Topaloglu, “Exploiting STI stress for performance,” IEEE International Conference on Computer-aided Design, 2007 [16] V. Joshi, B. Cline, D. Sylvester, D. Blaauw, K. Agarwal, “Stress aware layout optimization,” IEEE International Symposium on Physical Design, 2008 [17] T. Sakurai, A.R. Newton, “Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas,” IEEE Journal of Solid-State Circuits, vol. 25, issue 2, pp.584-594, 1990 [18] P. Andreani, S. Mattison, “On the use of MOS varactors in RF VCO’s,” IEEE Journal of Solid-State Circuits, vol.35 no.6, pp.905-910, Jun 2000
1.0 off-chip capacitor preferred
0.6 0.4 0.2 0.0
10X savings in standby power
Wpgs [%]
0.8
100p
1n 10n Decaps [F]
100n
Figure 12. Standby power savings with remote decaps at iso-performance. The improved decap can be used for mitigating the supply noise induced by PGSs. The reduced supply noise enables the use of even smaller PGSs, which in turn can achieve a significant amount of standby power reduction. Figure 12 shows the allowed size of PGSs at different values of decaps. At the design points in the line, the main circuits operate at the same clock frequency. Although an on-chip decap larger than 1nF may not be feasible due to large silicon area, we can easily use off-chip capacitors since decaps at ULV regimes are more tolerant to the resistance of the path.
6. Conclusions In this paper, we investigate the design strategy for decaps at ULV regimes in order to mitigate the degradation of gate decoupling capacitance at lower supply voltage. The proposed decap design strategy of using capacitance-enhanced remote decaps reduces the area overhead by 6.1-8.2×, compared to conventional design approaches. When used in a design with PGSs, it can reduce standby power consumption through improved robustness against supply noise.
Acknowledgement
– the author appreciate the valuable discussion with Gregory K. Chen at Intel.
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