Delta-Sigma Converters using Frequency- Modulated ... - CiteSeerX
Delta-Sigma Converters using FrequencyModulated Intermediate Values Mats Høvin1, Alf Olsen2 , Tor Sverre Lande1 and Chris Toumazou3 1
Dept. of Informatics, University of Oslo, Blindern, N-0316 Oslo, Norway
2
Schlumberger Geco-Prackla, Jongsåsveien 4, N-1300 Sandvika, Norway
Dept. of Electrical & Electronic Engineering, Imperial College, Exhibition Road, London SW7 2BT, UK
Abstract
— This paper describes a new first and secondorder delta-sigma modulator (DSM) concept where the first integrator is extracted and implemented by a FM oscillator with the modulating signal as the input. The result is a simple DSM with no need for DACs, allowing straightforward multi-bit quantization. Without the FM oscillator, the modulator becomes a F/D converter with delta-sigma noise shaping. I. I N T RO D U C T I O N The delta-sigma (1-6 ) A/D conversion technique [1] is currently receiving increased attention as an attractive alternative to traditional A/D conversion. Although the DSM is well suited for VLSI implementation, multi-bit quantization is not straightforward due to DAC limitations, and the sampling speed is limited by the integrator slew-rate. By implementing the main integrator as a FM oscillator we achieve a simpler modulator without DACs, and straightforward multi-bit quantization and higher sampling frequency potential is one amongst other features. The new DSM that will be referred to as a frequency DSM (FDSM) may become a F/D converter with 1-6 noise shaping just by removing the FM oscillator. Compared to the 16 FDC in [2] the FDSM concept is simpler, and as opposed to the second-order architecture reported in [3] the FDSM offers multi-bit quantization. To illustrate why a FM oscillator may be used as an integrator we may look at the FM signal itself. An ideal logic level FM signal may be expressed as f m .t / D . Vdd =2/sgn[sin[.t /]] C . Vdd = 2/; where
.t / D 2³
Z
(1)
t
1
. fc C kx .− //d −:
(2)
In this expression fc represents the carrier frequency, x .− / the modulating signal, and k the frequency sensitivity. From (2) we see that the FM signal variable .t /=2³ is the integral of fc C kx .t /. The equation .t /=2³ may be separated into
n =2³ D Pn C n ;
(3)
where Pn is an integer representing the received number of rising FM edges at time n Ts , and n 2 [0; 1i is the phase difference between the previous rising FM edge and the sample signal edge scaled by 1= 2³ . fs x(t)
FM osc
fm(t) mod-2n counter
reg
3
reg _ + n-bit
yn=Pn-Pn-1 n-bit (no borrow)
Figure 1: A first-order FDSM II. T H E F I R S T O R D E R FDSM A very simple DSM implementation is made by replacing the single loop integrator of a first-order DSM with a FM oscillator. By doing so, we have got an integrator with a high S N R potential that never saturates, so the feedback may be removed. For integer quantization thresholds, the resulting FDSM may be implemented by the circuit illustrated in Fig. 1. The output is merely the number of received FM periods Pn Pn 1 during the sampling interval Ts D 1= f s . By replacing PP n n with n =2³ (3), and from (2) representing n =2³ as Ts niD 1 . fc C kx i /, the output may be written as yn D Ts . fc C kxn /
n C n 1 :
(4)
By considering the modulating signal xn as the input, we have a first-order DSM where the input is scaled and biased, and the quantization error n is differentiated. Although we are using a FM intermediate value, the circuit implement first-order 1-6 A/D conversion. If the signal source itself contains a FM oscillator, we have shown that for F/D conversion or digital FM demodulation, we achieve equivalent first-order 1-6 noise shaping with respect to the modulating signal by using an oversampled traditional count, dump, and reset F/D converter followed by a 1-6 decimator. The FDSM may also be described as a FM oscillator connected to a delta modulator [1] as the count and dump F/D converter actually is a delta modulator with frequency input.
The effective output word length will depend on the maximum output signal range which can be expressed (5)
where f max is the maximum frequency of the modulating signal x .t /. From (6) we see that by doubling fs we only increase the S Q N R by ³ 3dB due to the reduced S Ro . A more efficient way to increase the S Q N R is to increase the integrator gain by the frequency sensitivity k. The counter may also be considered as a first-stage count and dump decimator, and by raising fs we are just shuffling a larger part of the decimating task from the coarse count and dump decimator over to the more sophisticated 1-6 decimator. In that sense, a FM signal may be considered as an asynchronous first-order 1-6 bit-stream. With modulo-2n counting [1], we omit the traditionally speed limiting resetting operation, and the output signal bias component due to f c will be clipped down to mod-2n . f c = f s /. If the output signal bias component is known, the size n, of the modulo counter can be made as short as the smallest integer greater than maxf S Ro ; 1g without aliasing. We may therefore let the counter pass through several cycles during the sampling interval as long as the frequency deviation is small enough to keep track of the final number of cycles. A neat observation is that by using modulo arithmetic, we may for fs > 2. fc C 1 f / use a modulo-2 counter which may be replaced by a simple D flip-flop. A. The pointer-FDSM In some applications the FM signal can be generated by a ring oscillator where each inverter is approximately equally sensitive to the modulating signal. Examples are I2 L-ring oscillators [4], and ring oscillators where the inverter propagation delay is directly modulated by some physical parameter (acceleration, pressure, temperature, ..). By using the power supply voltage as the input, the frequency of an ordinary CMOS inverter based ringoscillator may also be approximated by a linear function of the input voltage in a limited range. By considering the ring oscillator itself as an modulo-n counter we are able to increase the resolution. This can be achieved by sampling the node values and generating the logical XNOR between each neighbouring nodes giving an active high “pointer” output that will run through all nodes in sequence (Fig. 2). The output may then be feed to a simple binary encoder followed by a differentiator. Since we cannot use modulo-2n
0
0
1
0 3
1
1
2
1 1
0
0
0
1
1 1 0
Figure 2: The different states of a 3-inverter ringoscillator
_
reg
corr
out
where 1 f is the maximum frequency deviation given by the maximum input signal range S Ri . Together with the first-order shaped quantization noise [1] the signal to quantization noise ratio will be ! S Ro fma x 3= 2 ³ S Q N R ³ 20 log p ; (6) 2 20 log 6 fs 2 2
0 1
binary encoder
S Ro ³ 21 f = f s D k Ð S Ri = fs ;
0 1
+
Figure 3: A 7-inverter pointer-FDSM. The outer ring symbolize the individual sample and XNOR units counting some minor digital correction must follow to form the output word stream (Fig. 3). For the pointer FDSM the S Ro will be approximately S Ro ³
21− ; f s −0
(7)
where −0 is the unmodulated delay of one inverter, and 1− is the maximum relative delay diversion of one inverter. Simulations shows insignificant S N R reduction for minor relative diversions between the −0 values. In both FDSMs (Fig. 1, Fig. 3), sampling clock phase noise (clock jitter) will be first-order noise shaped, while sampling clock frequency noise will be unshaped. The sampling clock must therefore be considered as an frequency reference unless a reference modulator is used. III. TH E S E C O N D -O R D E R FDSM By following the same way of thinking that gave the firstorder FDSM, an alternative second-order DSM may be designed. Fig. 4 illustrates a circuit that except from a scaling factor is a mathematical equivalent to a second-order MASH DSM [1], [5] with integer quantization thresholds. The firststage is however implemented as an first-order FDSM. By doing so, the input to the second-stage will be n . The output can be expressed as yn D Pn
Pn
1
C n
n
1
C žn
2žn
1
C žn 2 ;
(8)
where žn 2 [0; 1i is the second-stage quantization error. We recognize Pn Pn 1 from (4), and the output may be written as yn D Ts . fc C kxn / C žn
2žn
1
C žn 2 :
(9)
φn φn + _ detect
quantizer εn + _
+
+
the reference current should also be temporally adjusted according to these variations. A much simpler approach is using a constant reference current Ire f , and use the same Ire f to implement the feedback by discharging the capacitor during some nearby T f m interval, assuming that T f m is approximately the same for adjacent FM periods (Fig. 5). By doing so, a scaled feedback representing -1 is carried out, and by doing nothing a feedback of 0 is carried out corresponding to the equivalent DAC levels 1 and 0. In this way the feedback signal is scaled to always match the input, giving an approximately correct bit-stream output regardless of the magnitude of the reference current assuming fc × f max . By using only one charging current, and one voltage reference, there will be no linearity or matching restrictions on the capacitor. Noise introduced in the accumulator and counter, including thermal noise and sampling clock phase noise (clock jitter) will be first-order noise shaped. Sampling clock frequency noise will have the same impact on the signal as in the firstorder FDSM. The digital control logic in Fig. 5 enables fs or
del
fs
del DAC
x(t)
FM osc
fm(t)
+edge counter
reg _ +
control logic
del
reg
fs
Vref
_ +
Pn-Pn-1
+
yn
1-bit
Vc
Iref
2-bit
x(t)
A. The second-stage implementation The phase-input ( n ) to the second-stage modulator is not a directly measureable quantity, and therefore, probably the simplest way to compute n is by the estimation
n ³ 1tn = Tnf m ;
(11)
where 1tn is the time difference between the previous rising fm FM edge and the current sampling edge, and Tn is the current FM period. It is hard to know if the current rising FM edge is the last one before the sampling edge, and it is therefore easier to use the complementary phase 1 n , estimated by the time difference between the next rising FM edge and the sampling fm edge divided by Tn . By doing so, the second-stage output must be subtracted from the first-stage output. Since the internal values in the accumulator is derived from time differences, the most convenient implementation is capacitor charging by a reference current during the measuring time interval. In this way accumulation and subtraction is, in principle, straight-forward. The problem is, however, properly scaling of the reference current. The reference current must be scaled to make the resulting capacitor voltage match the quantization thresholds. Due to signal dependent variations in T f m ,
FM osc
fm(t)
mod-2n counter
reg
evaluate
Figure 4: Mathematical equivalent two-stage DSM
(n+1)-bit output
By considering the modulating signal xn as the input, we have a second-order DSM where the input is scaled and biased, and the quantization error žn is double differentiated. The RSo will be given by (5), and the S Q N R will from [1] be ! S Ro fma x 5= 2 ³2 S Q N R ³ 20 log p : 20 log p 2 fs 2 2 60 (10) By doubling fs we notice that we only gain ³ 9dB due to the reduced R So . If the signal source itself contains a FM oscillator, we have shown that for F/D conversion or digital FM demodulation, we achieve equivalent second-order 1-6 noise shaping with respect to the modulating signal by using an oversampled count, dump, and reset F/D converter with a phase controlled corrector.
reg _ + n-bit
_ + n-bit (no borrow)
Figure 5: A two-stage FDSM circuit f m .t / to access the current switch. To avoid inaccurate capacitor charging due to sloppy edges, we may use overlap charging illustrated by Qb C and Qb in Fig. 6. These intervals determined by the positive FM period, may also avoid metastability problems. Given an accurate current mirror, errors introduced by asymmetric sloppy edges will ∆t
fm(t)
Tfm
fs Qφ
IC
Qb+
TfmIref > Qφ > 0
Qf=0 or Qf=-TfmIref Qb-
Qf
feedback charge
evaluate
Figure 6: Overlap charging with sloppy edges contribute with a constant charge bias. This offset will be equal for all samples, and should be almost eliminated by the differentiator.
0
0
−20
−40
−60
Power (dB)
IV. S Y S T E M L E V E L S I M U L AT I O N S To confirm the theory, system level simulations of both firstorder and second-order FDSMs has been carried out. In order to simulate the ideal behaviour, the analog input - intermediate frequency relationship is assumed to be linear. Fig. 7 shows the output noise spectrum of a 7-inverter pointer FDSM where the loop frequency is modulated by a single sinusoid with maximum amplitude and frequency fs =215 ³ 732Hz. In this modulator, fs was set to 24MHz, −0 D 1:2nS and 1− D š5%. The node values was simulated by using 7 phase shifted FM square wave carriers. As we see from Fig. 7, the output noise spectrum is shaped as expected according to first-order 1-6 theory. To simulate the second-order FDSM, fs was set to 500KHz, and a FM square wave carrier with fc D 50MHz modulated by a single sinusoid with frequency 76 f s =215 ³ 1160Hz and frequency ratio 1 f = f c D š10% was used as the intermediate signal. A discrete time simulation routine was then used to calculate pn , n and the 5-bit output word-stream. Again the output noise spectrum is shaped as expected (Fig. 8).
−80
−100
−120
−140
−160
3
10
4
10 Frequency (Hz)
5
10
Figure 8: A 215 -point FFT analysis of a second-order FDSM output word-stream illustrating low f s operation digital CMOS, only one capacitor needed with very low precision requirements, higher sampling frequency potential. The disadvantages of the first and second-order FDSM are:
ž Sensitive to frequency modulating noise in the FM oscillator, a bias component in the output word-stream, a frequency stable clock oscillator is required (the last two points may be eliminated by using a reference modulator).
Power (dB)
-50
-100
-150
3
10
4
10
5
10 Frequency (Hz)
6
10
7
10
Figure 7: A 215 -point FFT analysis of a 7-inverter pointerFDSM output word-stream V. C O N C L U S I O N By extracting the first integrator, and using frequency as an intermediate value, a new DSM architectural concept is presented. Compared to the first-order traditional DSM, the firstorder FDSM have the following advantages:
ž Multi-bit quantization with no DAC, very simple implementation in standard digital CMOS, very high sampling potential, suited for low power supply voltage operation, potential of low power consumption. Compared to the second-order MASH DSM the secondorder FDSM have the following advantages:
ž Extended multi-bit quantization with no DACs, no stage matching problems, simpler implementation in standard
If the FM oscillator is already implemented i.e. the measured signal is given as a FM carrier, F/D conversion or digital FM demodulation may be done with first-order 1-6 noise shaping by using an oversampled traditional count and dump F/D converter followed by a 1-6 decimator. Second-order 1-6 noise shaping may also be achieved by adding a second-stage acting as an phase controlled corrector. The initial measurements on a first and second-order prototype FDSM seems to confirm the simulated results. RE F E R E N C E S [1] J. C. Candy and G. C. Temes: Oversampling Delta-Sigma data converters, IEEE Press, New York, 1992. [2] I. Galton: “Higher-Order Delta-Sigma Frequency-to-Digital conversion”, Proc. IEEE ISCAS’94, pp.441-444. [3] R. D. Beards and M. A. Copeland: “An Oversampling DeltaSigma Frequency Discriminator”, IEEE Trans. on Circuits and Systems, vol. 41, no. 2, pp.26-32, 1994. [4] H. Reichl, H. J. Hwang, and H. Riedel: “Frequency-Analog Sensors using the I2 L Technique”, Sensors and Actuators, 4, pp.247-254, 1983. [5] K. Uchimura, T. Hayashi, T. Kimura, and A. Iwata: “Oversampling A-to-D and D-to-A Converters with Multistage Noise Shaping Modulators”, IEEE Trans. Acoust., Speech, Signal Prossesing, vol. AASP-36, pp.1899-1905, 1988.
Dept. of Informatics, University of Oslo, Blindern, N-0316 Oslo, Norway
2
Schlumberger Geco-Prackla, Jongsåsveien 4, N-1300 Sandvika, Norway
Dept. of Electrical & Electronic Engineering, Imperial College, Exhibition Road, London SW7 2BT, UK
Abstract
— This paper describes a new first and secondorder delta-sigma modulator (DSM) concept where the first integrator is extracted and implemented by a FM oscillator with the modulating signal as the input. The result is a simple DSM with no need for DACs, allowing straightforward multi-bit quantization. Without the FM oscillator, the modulator becomes a F/D converter with delta-sigma noise shaping. I. I N T RO D U C T I O N The delta-sigma (1-6 ) A/D conversion technique [1] is currently receiving increased attention as an attractive alternative to traditional A/D conversion. Although the DSM is well suited for VLSI implementation, multi-bit quantization is not straightforward due to DAC limitations, and the sampling speed is limited by the integrator slew-rate. By implementing the main integrator as a FM oscillator we achieve a simpler modulator without DACs, and straightforward multi-bit quantization and higher sampling frequency potential is one amongst other features. The new DSM that will be referred to as a frequency DSM (FDSM) may become a F/D converter with 1-6 noise shaping just by removing the FM oscillator. Compared to the 16 FDC in [2] the FDSM concept is simpler, and as opposed to the second-order architecture reported in [3] the FDSM offers multi-bit quantization. To illustrate why a FM oscillator may be used as an integrator we may look at the FM signal itself. An ideal logic level FM signal may be expressed as f m .t / D . Vdd =2/sgn[sin[.t /]] C . Vdd = 2/; where
.t / D 2³
Z
(1)
t
1
. fc C kx .− //d −:
(2)
In this expression fc represents the carrier frequency, x .− / the modulating signal, and k the frequency sensitivity. From (2) we see that the FM signal variable .t /=2³ is the integral of fc C kx .t /. The equation .t /=2³ may be separated into
n =2³ D Pn C n ;
(3)
where Pn is an integer representing the received number of rising FM edges at time n Ts , and n 2 [0; 1i is the phase difference between the previous rising FM edge and the sample signal edge scaled by 1= 2³ . fs x(t)
FM osc
fm(t) mod-2n counter
reg
3
reg _ + n-bit
yn=Pn-Pn-1 n-bit (no borrow)
Figure 1: A first-order FDSM II. T H E F I R S T O R D E R FDSM A very simple DSM implementation is made by replacing the single loop integrator of a first-order DSM with a FM oscillator. By doing so, we have got an integrator with a high S N R potential that never saturates, so the feedback may be removed. For integer quantization thresholds, the resulting FDSM may be implemented by the circuit illustrated in Fig. 1. The output is merely the number of received FM periods Pn Pn 1 during the sampling interval Ts D 1= f s . By replacing PP n n with n =2³ (3), and from (2) representing n =2³ as Ts niD 1 . fc C kx i /, the output may be written as yn D Ts . fc C kxn /
n C n 1 :
(4)
By considering the modulating signal xn as the input, we have a first-order DSM where the input is scaled and biased, and the quantization error n is differentiated. Although we are using a FM intermediate value, the circuit implement first-order 1-6 A/D conversion. If the signal source itself contains a FM oscillator, we have shown that for F/D conversion or digital FM demodulation, we achieve equivalent first-order 1-6 noise shaping with respect to the modulating signal by using an oversampled traditional count, dump, and reset F/D converter followed by a 1-6 decimator. The FDSM may also be described as a FM oscillator connected to a delta modulator [1] as the count and dump F/D converter actually is a delta modulator with frequency input.
The effective output word length will depend on the maximum output signal range which can be expressed (5)
where f max is the maximum frequency of the modulating signal x .t /. From (6) we see that by doubling fs we only increase the S Q N R by ³ 3dB due to the reduced S Ro . A more efficient way to increase the S Q N R is to increase the integrator gain by the frequency sensitivity k. The counter may also be considered as a first-stage count and dump decimator, and by raising fs we are just shuffling a larger part of the decimating task from the coarse count and dump decimator over to the more sophisticated 1-6 decimator. In that sense, a FM signal may be considered as an asynchronous first-order 1-6 bit-stream. With modulo-2n counting [1], we omit the traditionally speed limiting resetting operation, and the output signal bias component due to f c will be clipped down to mod-2n . f c = f s /. If the output signal bias component is known, the size n, of the modulo counter can be made as short as the smallest integer greater than maxf S Ro ; 1g without aliasing. We may therefore let the counter pass through several cycles during the sampling interval as long as the frequency deviation is small enough to keep track of the final number of cycles. A neat observation is that by using modulo arithmetic, we may for fs > 2. fc C 1 f / use a modulo-2 counter which may be replaced by a simple D flip-flop. A. The pointer-FDSM In some applications the FM signal can be generated by a ring oscillator where each inverter is approximately equally sensitive to the modulating signal. Examples are I2 L-ring oscillators [4], and ring oscillators where the inverter propagation delay is directly modulated by some physical parameter (acceleration, pressure, temperature, ..). By using the power supply voltage as the input, the frequency of an ordinary CMOS inverter based ringoscillator may also be approximated by a linear function of the input voltage in a limited range. By considering the ring oscillator itself as an modulo-n counter we are able to increase the resolution. This can be achieved by sampling the node values and generating the logical XNOR between each neighbouring nodes giving an active high “pointer” output that will run through all nodes in sequence (Fig. 2). The output may then be feed to a simple binary encoder followed by a differentiator. Since we cannot use modulo-2n
0
0
1
0 3
1
1
2
1 1
0
0
0
1
1 1 0
Figure 2: The different states of a 3-inverter ringoscillator
_
reg
corr
out
where 1 f is the maximum frequency deviation given by the maximum input signal range S Ri . Together with the first-order shaped quantization noise [1] the signal to quantization noise ratio will be ! S Ro fma x 3= 2 ³ S Q N R ³ 20 log p ; (6) 2 20 log 6 fs 2 2
0 1
binary encoder
S Ro ³ 21 f = f s D k Ð S Ri = fs ;
0 1
+
Figure 3: A 7-inverter pointer-FDSM. The outer ring symbolize the individual sample and XNOR units counting some minor digital correction must follow to form the output word stream (Fig. 3). For the pointer FDSM the S Ro will be approximately S Ro ³
21− ; f s −0
(7)
where −0 is the unmodulated delay of one inverter, and 1− is the maximum relative delay diversion of one inverter. Simulations shows insignificant S N R reduction for minor relative diversions between the −0 values. In both FDSMs (Fig. 1, Fig. 3), sampling clock phase noise (clock jitter) will be first-order noise shaped, while sampling clock frequency noise will be unshaped. The sampling clock must therefore be considered as an frequency reference unless a reference modulator is used. III. TH E S E C O N D -O R D E R FDSM By following the same way of thinking that gave the firstorder FDSM, an alternative second-order DSM may be designed. Fig. 4 illustrates a circuit that except from a scaling factor is a mathematical equivalent to a second-order MASH DSM [1], [5] with integer quantization thresholds. The firststage is however implemented as an first-order FDSM. By doing so, the input to the second-stage will be n . The output can be expressed as yn D Pn
Pn
1
C n
n
1
C žn
2žn
1
C žn 2 ;
(8)
where žn 2 [0; 1i is the second-stage quantization error. We recognize Pn Pn 1 from (4), and the output may be written as yn D Ts . fc C kxn / C žn
2žn
1
C žn 2 :
(9)
φn φn + _ detect
quantizer εn + _
+
+
the reference current should also be temporally adjusted according to these variations. A much simpler approach is using a constant reference current Ire f , and use the same Ire f to implement the feedback by discharging the capacitor during some nearby T f m interval, assuming that T f m is approximately the same for adjacent FM periods (Fig. 5). By doing so, a scaled feedback representing -1 is carried out, and by doing nothing a feedback of 0 is carried out corresponding to the equivalent DAC levels 1 and 0. In this way the feedback signal is scaled to always match the input, giving an approximately correct bit-stream output regardless of the magnitude of the reference current assuming fc × f max . By using only one charging current, and one voltage reference, there will be no linearity or matching restrictions on the capacitor. Noise introduced in the accumulator and counter, including thermal noise and sampling clock phase noise (clock jitter) will be first-order noise shaped. Sampling clock frequency noise will have the same impact on the signal as in the firstorder FDSM. The digital control logic in Fig. 5 enables fs or
del
fs
del DAC
x(t)
FM osc
fm(t)
+edge counter
reg _ +
control logic
del
reg
fs
Vref
_ +
Pn-Pn-1
+
yn
1-bit
Vc
Iref
2-bit
x(t)
A. The second-stage implementation The phase-input ( n ) to the second-stage modulator is not a directly measureable quantity, and therefore, probably the simplest way to compute n is by the estimation
n ³ 1tn = Tnf m ;
(11)
where 1tn is the time difference between the previous rising fm FM edge and the current sampling edge, and Tn is the current FM period. It is hard to know if the current rising FM edge is the last one before the sampling edge, and it is therefore easier to use the complementary phase 1 n , estimated by the time difference between the next rising FM edge and the sampling fm edge divided by Tn . By doing so, the second-stage output must be subtracted from the first-stage output. Since the internal values in the accumulator is derived from time differences, the most convenient implementation is capacitor charging by a reference current during the measuring time interval. In this way accumulation and subtraction is, in principle, straight-forward. The problem is, however, properly scaling of the reference current. The reference current must be scaled to make the resulting capacitor voltage match the quantization thresholds. Due to signal dependent variations in T f m ,
FM osc
fm(t)
mod-2n counter
reg
evaluate
Figure 4: Mathematical equivalent two-stage DSM
(n+1)-bit output
By considering the modulating signal xn as the input, we have a second-order DSM where the input is scaled and biased, and the quantization error žn is double differentiated. The RSo will be given by (5), and the S Q N R will from [1] be ! S Ro fma x 5= 2 ³2 S Q N R ³ 20 log p : 20 log p 2 fs 2 2 60 (10) By doubling fs we notice that we only gain ³ 9dB due to the reduced R So . If the signal source itself contains a FM oscillator, we have shown that for F/D conversion or digital FM demodulation, we achieve equivalent second-order 1-6 noise shaping with respect to the modulating signal by using an oversampled count, dump, and reset F/D converter with a phase controlled corrector.
reg _ + n-bit
_ + n-bit (no borrow)
Figure 5: A two-stage FDSM circuit f m .t / to access the current switch. To avoid inaccurate capacitor charging due to sloppy edges, we may use overlap charging illustrated by Qb C and Qb in Fig. 6. These intervals determined by the positive FM period, may also avoid metastability problems. Given an accurate current mirror, errors introduced by asymmetric sloppy edges will ∆t
fm(t)
Tfm
fs Qφ
IC
Qb+
TfmIref > Qφ > 0
Qf=0 or Qf=-TfmIref Qb-
Qf
feedback charge
evaluate
Figure 6: Overlap charging with sloppy edges contribute with a constant charge bias. This offset will be equal for all samples, and should be almost eliminated by the differentiator.
0
0
−20
−40
−60
Power (dB)
IV. S Y S T E M L E V E L S I M U L AT I O N S To confirm the theory, system level simulations of both firstorder and second-order FDSMs has been carried out. In order to simulate the ideal behaviour, the analog input - intermediate frequency relationship is assumed to be linear. Fig. 7 shows the output noise spectrum of a 7-inverter pointer FDSM where the loop frequency is modulated by a single sinusoid with maximum amplitude and frequency fs =215 ³ 732Hz. In this modulator, fs was set to 24MHz, −0 D 1:2nS and 1− D š5%. The node values was simulated by using 7 phase shifted FM square wave carriers. As we see from Fig. 7, the output noise spectrum is shaped as expected according to first-order 1-6 theory. To simulate the second-order FDSM, fs was set to 500KHz, and a FM square wave carrier with fc D 50MHz modulated by a single sinusoid with frequency 76 f s =215 ³ 1160Hz and frequency ratio 1 f = f c D š10% was used as the intermediate signal. A discrete time simulation routine was then used to calculate pn , n and the 5-bit output word-stream. Again the output noise spectrum is shaped as expected (Fig. 8).
−80
−100
−120
−140
−160
3
10
4
10 Frequency (Hz)
5
10
Figure 8: A 215 -point FFT analysis of a second-order FDSM output word-stream illustrating low f s operation digital CMOS, only one capacitor needed with very low precision requirements, higher sampling frequency potential. The disadvantages of the first and second-order FDSM are:
ž Sensitive to frequency modulating noise in the FM oscillator, a bias component in the output word-stream, a frequency stable clock oscillator is required (the last two points may be eliminated by using a reference modulator).
Power (dB)
-50
-100
-150
3
10
4
10
5
10 Frequency (Hz)
6
10
7
10
Figure 7: A 215 -point FFT analysis of a 7-inverter pointerFDSM output word-stream V. C O N C L U S I O N By extracting the first integrator, and using frequency as an intermediate value, a new DSM architectural concept is presented. Compared to the first-order traditional DSM, the firstorder FDSM have the following advantages:
ž Multi-bit quantization with no DAC, very simple implementation in standard digital CMOS, very high sampling potential, suited for low power supply voltage operation, potential of low power consumption. Compared to the second-order MASH DSM the secondorder FDSM have the following advantages:
ž Extended multi-bit quantization with no DACs, no stage matching problems, simpler implementation in standard
If the FM oscillator is already implemented i.e. the measured signal is given as a FM carrier, F/D conversion or digital FM demodulation may be done with first-order 1-6 noise shaping by using an oversampled traditional count and dump F/D converter followed by a 1-6 decimator. Second-order 1-6 noise shaping may also be achieved by adding a second-stage acting as an phase controlled corrector. The initial measurements on a first and second-order prototype FDSM seems to confirm the simulated results. RE F E R E N C E S [1] J. C. Candy and G. C. Temes: Oversampling Delta-Sigma data converters, IEEE Press, New York, 1992. [2] I. Galton: “Higher-Order Delta-Sigma Frequency-to-Digital conversion”, Proc. IEEE ISCAS’94, pp.441-444. [3] R. D. Beards and M. A. Copeland: “An Oversampling DeltaSigma Frequency Discriminator”, IEEE Trans. on Circuits and Systems, vol. 41, no. 2, pp.26-32, 1994. [4] H. Reichl, H. J. Hwang, and H. Riedel: “Frequency-Analog Sensors using the I2 L Technique”, Sensors and Actuators, 4, pp.247-254, 1983. [5] K. Uchimura, T. Hayashi, T. Kimura, and A. Iwata: “Oversampling A-to-D and D-to-A Converters with Multistage Noise Shaping Modulators”, IEEE Trans. Acoust., Speech, Signal Prossesing, vol. AASP-36, pp.1899-1905, 1988.
