Deterministic Diagnostic Pattern Generation (DDPG) - Semantic Scholar
Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects Fei Wang1, 2, Yu Hu1, Huawei Li1, Xiaowei Li1, Jing Ye1, 2 1
Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China 2
Graduate University of Chinese Academy of Sciences, Beijing, China {wang_fei, huyu, lihuawei, lxw}@ict.ac.cn
Yu Huang3 3
Mentor Graphics Corporation, 300 Nickerson Rd., Marlborough, MA, 01752, USA [email protected]
Abstract Scan chain failure diagnosis has become an important means for silicon debug and yield improvement. Although plenty of prior work discussed how to perform scan chain diagnosis, most of the previously proposed techniques made an assumption that the system logic is fault-free, which could be an impractical assumption leading to incorrect diagnostic results. In this paper, we propose a scan chain Deterministic Diagnostic Pattern Generation (DDPG) method that can tolerate the faults in the system logic without degradation of chain diagnostic resolution and precision. The entire flow includes three steps. In the first step, patterns are created to propagate the state of a targeted scan cell to as many reliable observation points as possible. In the second step, the load error probability of each targeted scan cell is calculated based on the Hamming Distances between the observed responses and the expected good or faulty responses. In the last step, a suspect profile is plotted, which can be used to identify the suspect scan cell(s) based on ranking scores. Experimental results show that the diagnostic resolution and precision are not degraded even with dozens of faults injected into the system logic.
1.
Introduction
It was reported in [1] that about 10-30% of logic defects cause scan chain failures, while in another paper [2], it was even reported that chain failures account for almost 50% of chip failures. Therefore, scan chain failure diagnosis has become an important research topic in recent years. However, most of the previously proposed software-based chain diagnosis techniques [1] [3-5] [7-9] [11-13] assume the system logic is defect-free. It may be an impractical assumption that leads to incorrect diagnostic results. When scan chain defects and system logic defects co-exist on one chip, it is called compound defects [14]. According to [14], the diagnosis hit rate for compound defects can be smaller than 40% when assuming system logic is defect-free. Although hardware based scan chain defect diagnosis methods [16-18] do not have to make any assumption on the system logic, they are rarely applied to the realistic
industrial designs due to the hardware overhead of the special scan architecture and unconventional DFT flow. Even though some previous work [2] [10] [14-15] proposed some techniques that can diagnose compound defects, to the best of our knowledge, there is no Deterministic Diagnostic Pattern Generation (DDPG) methodology that is proposed to specifically target compound defects yet. In this paper, we proposed a novel DDPG method and a scan chain diagnosis technique that specifically targets compound defects. The rest of the paper is organized as follows. Session 2 explains the fault models used in this paper and reviews some previous work on related topics. Session 3 describes the proposed DDPG algorithm in detail. Session 4 illustrates the proposed diagnosis technique based on the created DDPG patterns. Experimental results are shown in session 5. Session 6 concludes the paper.
2.
Background
2.1 Scan Chain Fault Models To illustrate scan chain diagnosis techniques more easily, each scan cell in a scan chain is given an index. The cell connected to scan-output is numbered 0 and the cells in the chain are numbered incrementally from scan-output to scan-input sequentially. The scan cells between the scan chain input and the scan-input port of a scan cell are called the upstream cells of this scan cell, while the scan cells between the scan chain output and the scan-output port of a scan cell are called the downstream cells of this scan cell. Table 1. Fault models and their effects Model SA0 SA1 STR STF FTR FTF
Expected Scan Out 00001111 11110000 11110000 00001111 11110000 00001111
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Actual Scan Out 00000000 11111111 11100000 00011111 11111000 00000111
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Six types of fault models [1] are studied in this work, including stuck-at high (SA1) and stuck-at low (SA0), slow-to-rise (STR), slow-to-fall (STF), fast-to-rise (FTR), and fast-to-fall (FTF). Table 1 shows the six fault models and their effects on scan chain which consists of 8 scan cells, assuming a flush test pattern “00001111” or “11110000” is shifted in. The affected data is highlighted in underlined bold font. 2.2 Prior Work on Compound Defect Diagnosis and Diagnostic ATPG According to the patterns used for diagnosis, prior software-based chain diagnosis techniques can be classified into three categories: (1) use existing scanbased production test patterns, (2) use existing functional patterns, and (3) generate dedicated diagnostic patterns. The techniques proposed in [14-15] belong to category (1). In [14], an algorithm was proposed to diagnose general compound defects. The failures are first partitioned into two groups by X-simulation. The failure bits in one group are caused by the system logic defects and the failure bits in the other group could be caused by either chain defects or system logic defects. System logic diagnosis techniques and chain diagnosis techniques are applied to those two groups of failures respectively. In [15], a special defect called DACS was explored. DACS stands for Defect that Affect Chain and System logic. However, the method cannot diagnose the compound defects if the scan chain faults are uncorrelated with the system logic faults. The techniques proposed in [2][6][10] belong to category (2). The proposed chain algorithms usually include two parts: (1) use existing functional patterns to get some scan patterns that do not use the scan chain loading procedure so that the impact of chain defects only comes from the chain unloading procedure, and (2) apply heuristics to analyze the test failures and identify the defective cells. The heuristics include signal profiling [2], image recovery [6] and best-alignment [10]. These algorithms can tolerate a few faults in the system logic. All above-mentioned diagnosis techniques may not guarantee to get the best diagnosis results all the time because they do not generate deterministic diagnostic patterns for scan chains. As a result, their effectiveness is largely determined by the diagnosis capability of the existing patterns. Take the signal profiling method [2] as an example. Firstly, the functional test patterns are supposed to bring the circuit through a state sequence as random as possible. The randomness is measured by the signal-1 probability of the flip-flops. Afterwards, a signal profile of scan cells can be obtained from the unloaded patterns. If a scan cell’s signal probability deviates significantly from the
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expected signal-1 probability, it implies that a defect is at the downstream of this cell. However, in practice, sometimes the signal-1 (signal-0) probability of a scan cell is much more dominant than its signal-0 (signal-1) probability. In that case, it requires a very large number of patterns and long clock sequences for each pattern to randomize the signal probability. It might result in two problems: (1) simulation time could be very long and (2) the tester memory capacity might limit the collection of a large number of failing patterns. The analysis motivated us to look into the DDPG solution for compound defect diagnosis. Although DDPG has not been studied for compound defects yet, DDPG techniques for chain diagnosis, assuming system logic is defect-free, were well studied in the past [3][4][5]. DDPG algorithms are either trying to capture certain desired values in the targeted scan cells or to propagate the fault effect to a reliable observation point, including Primary Outputs (POs), good scan chains and cells in the downstream of the faulty cell. The DDPG algorithm proposed in [3] targets one scan cell at a time and starts with the cell at the scan chain input. For each targeted scan cell N, it constrains cell N and all its downstream scan cells in [N-1, 0] to the stuck-at value v. The algorithm first tries to create a test pattern to capture a logic value opposite to the stuck-at fault value v in the targeted scan cell N. Once a test pattern is created for a targeted cell, it will move to its downstream neighbor cell (N-1) and so on so forth. While applying the generated patterns on a tester, if the expected value of the targeted scan cell is observed for the first pattern, it is ascertained that the fault is at the scan-in port of this scan cell. Otherwise the fault must be at the downstream of this cell. So the algorithm continues to examine the tester result of the next pattern, until it finds a cell such that its expected value is correctly observed on the tester. In [4] the technique proposed in [3] was improved by adding one more constraint to the upstream neighbor scan cell of the targeted cell so that the logic dependency between two neighbor scan cells cannot affect diagnostic precision. In [5], a single excitation technique to generate diagnostic patterns was proposed. Each single excitation pattern has only one sensitive bit that can be flipped by the fault. This technique converts the diagnosis problem into a single stuck-at fault ATPG problem, which can be easily solved by existing ATPG tools. In the following sections, we will focus on how to extend DDPG techniques to target compound defect diagnosis.
3.
DDPG for Compound Defects
The basic idea of the proposed DDPG algorithm is to propagate the state of a targeted scan cell to as many reliable observation points as possible. This is different from the previous methods like in [3], [4] or [5], where
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they only require that a fault be propagated to one reliable observation point to be detected. The purpose of propagating the state of the targeted scan cell to multiple reliable observation points is to reduce the impact from the system logic defects. Note that in this paper, we extend the definition of reliable observation points to include the whole faulty chain, if the chain fault is a timing fault (STR, STF, FTR, or FTF). As explained later, more ATPG constraints will be added to guarantee that the captured values can be reliably observed even it is on a faulty chain.
n-1 and repeat the above ATPG procedure. The iteration stops either when we find a set of patterns that can propagate the faulty state of the candidate scan cell to n reliable observation points within Output_Set or when n = 0 (i.e., we cannot create any pattern to reliably detect the faulty state at the candidate scan cell.)
3.1
We made two enhancements in this paper, compared to prior art [3] and [4].
Pattern Generation Algorithm Overview
Figure 1 shows the proposed DDPG flow. There are three inputs for the flow: (1) A targeted scan cell. Like algorithms in [3] [4] [5], our algorithm creates patterns that target one scan cell on the faulty chain at a time. (2) Output_Set. Output_Set contains all observation points that can be reached by the targeted scan cell. This information can be obtained by structural analysis of the circuit-under-diagnosis. (3) n. n is a user-specified value and it defines the minimum number of reliable observation points a pattern has to propagate the state of the targeted cell to. It is obvious that n must be smaller than or equal to the cardinality of Output_Set. We require n>1 in our flow. Output_Set
n (n>1)
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n=n-1 Y
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Y Save the pattern Delete the observation points from Output_Set N
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End Deterministic (DDPG) Flow
Diagnostic
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Initially the algorithm tries to create patterns to propagate the faulty state of the specified candidate scan cell to n reliable observation points within Output_Set. If n is initially set too large such that no patterns can be created to satisfy the requirement, we automatically decrease n to
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(1) Constraints on loaded values
(1.A) Not all scan cells on the faulty chain need constraints. Take a scan chain with stuck-at-v fault as an example. When we target cell N, and assume we want to propagate the state of cell N to a set of selected observation points, we only need constrain the cells that sensitize the fault propagation paths. The other scan cells do not need to be constrained because even if they have wrong values, they do not have any impact on observing the state of cell N at the pre-selected observation points. (1.B) The constrained scan cells can be anywhere on the faulty scan chain instead of having to be in the downstream of the targeted cell N as proposed in [3] [4]. This is because the algorithms in [3] and [4] are based on the assumption that the system logic is defect-free. If this assumption is wrong, the diagnosis result could be also wrong. Take scan chain STR faults as an example, suppose we target cell N and assume one cell M on the faulty chain must be set to a “1” in order to propagate the state of cell N to the selected observation points. No matter whether M is downstream or upstream of cell N, we must constrain cell M’s immediate downstream neighbor (cell M-1) to “1”, which will avoid a “0->1” transition corrupting the loaded value in cell M. Similarly, if the fault type is FTR or FTF, we set the constraint to cell M’s immediate upstream neighbor (cell M+1) to avoid sensitive transition. (2) Constraints on captured values
Y
Figure 1
Note that the above-mentioned pattern generation must satisfy some ATPG constraints. The constraints can be classified into two categories.
(2.A) For stuck-at faults, the reliable observation points include the downstream cells of Lower Bound (LB) in the faulty scan chain, as well as on good scan chains and POs. For SA1 (SA0) fault, we locate LB at the cell that is the closest to the scan chain input and observed a 0 (1) on the tester. For example, if the observed values of a scan chain with stuck-at-1 fault are (11110100), then LB is at scan cell 3. (2.B) For timing faults, we can use all scan cells on the faulty chain as observation points with similar constraints described earlier in (1.B). Take a scan chain FTF fault as an example, suppose we target cell N and assume one cell M (M can be anywhere on the faulty chain) will capture a
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“1”. We must constrain cell M’s immediate upstream neighbor (cell M+1) to “1”, which will avoid a “1->0” transition corrupting the unloaded value in cell M. SI x
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An Example of Diagnosing STR fault with Existing Logic Defect
An example is shown in Figure 2. Suppose there is only one scan chain in the design and the scan chain has one STR fault. When targeting scan cell 16, an attempt is made to propagate its state to the observation points as many as possible. To achieve this, scan cells (19, 14, 5) should be constrained to (0, 0, 1). Since these scan cells are on the faulty scan chain, their loaded values may be distorted by the fault. These scan cells are called vulnerable-PPIs, which are highlighted in light green color in Figure 2. To prevent sensitive transitions from occurring on the vulnerable-PPIs, constraints on the loaded values to their immediate downstream neighbor scan cells (18, 13, 4) have to be applied, as described earlier. These neighbor cells are called protection-PPIs, which are highlighted in dark green color in Figure 2. In this example, since we already constrain cells (19, 14) to (0, 0), no matter what values are loaded to cells (18, 13), the values loaded to cells (19, 14) will not be distorted by a STR chain fault. Therefore, we do not need constrain cells (18, 13). In contrast, scan cell 4 has to be constrained to a “1” to protect scan cell 5 to get a “1”
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during loading. In addition, to trigger a fault on the targeted scan cell, cells (16, 15) should be set to (1, 0). Scan cell 15 is called trigger-PPI, which is highlighted in dark red color in Figure 2. In summary, we set constraints on the loaded states for scan cells (19, 16, 15, 14, 5, 4) as (0, 1, 0, 0, 1, 1). Meanwhile, if an observation point is a PPO in a faulty scan chain, the captured value at the observation point may be distorted by the fault during unloading process. We call such observation points vulnerable-PPOs, which are highlighted in blue color in Figure 2. To avoid sensitive transitions on vulnerable-PPOs, their immediate downstream neighbor scan cells should also be constrained to capture logic “1”. We call these PPOs protection-PPOs, which are highlighted in dark blue color in Figure 2. If all protection-PPOs captured “1”s, there are no sensitive transitions on vulnerable-PPOs, no matter whether the real fault is at the targeted cell or not. Therefore, the observed states at vulnerable-PPOs are reliable. In the example shown in Figure 2, the state of scan cell 16 can be propagated to vulnerable-PPOs at cells (21, 8, 4). Their corresponding protection-PPOs at cells (20, 7, 3) should also capture (1, 1, 1). In ATPG, we try to create patterns under the abovementioned constraints to propagate the state of the targeted scan cell to as many observation points in Output_Set as possible. If a pattern is successfully created, it is saved out and the corresponding observation points are deleted from Output_Set. The iteration repeats until we delete all observation points from Output_Set or no valid patterns can be created.
Figure 3
Cover the Output_Set by Three Patterns
To illustrate our ATPG iterations, we use an example shown in Figure 3. Assume the state of a targeted scan cell C16 has logic path to scan cell C21, C16, C8, C4, C0 and a primary output O3. Initially Output_Set consists of C21, C16, C8, C4, C0 and O3. Suppose user sets n = 2, and assume a pattern patC16,1 can be created under the constraints to propagate C16’s state to scan cell C21, C8, and C4. These 3 observation points are deleted from Output_Set after we save out patC16,1. The remaining observation points in Output_Set are C16, C0 and O3. Assume another pattern patC16,2 can be created to propagate the state of C16 to C0, O3. We delete these two observation points from Output_Set. Finally a pattern
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patC16,3 can be created to cover the last observation point C16. All observation points in Outputs_Set are covered with 3 patterns. Note that some observation point may be covered by multiple patterns, as the example shown in Figure 3. 3.2
Netlist Modification and Paths Sensitization
We may have two solutions to create patterns. One solution is to use ATPG constraints, which are supported by most commercial ATPG tools. Another solution is to modify the original netlist to add the constraints if an ATPG do not support ATPG constraints. Any ATPG tool or SAT solver can be employed as pattern generation engine on this modified netlist and the netlist modification technique can be translated into ATPG constraints. In our experiment, we use the second solution. In this subsection, we first illustrate the technique of netlist modification through an example. Next, we illustrate how to sensitize multiple paths by a general ATPG tool. A modified netlist includes two parts: one part is the original netlist, and the other part is the constraint circuit. Constraint circuit is built based on the structure of the original netlist and the constraints we discussed in the previous subsection. We explain the construction process of the constraint circuit by an example shown in Figure 4.
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Sensitize Multiple Paths to Diagnose STR Fault Using Stuck-at ATPG Tools
Assume there is a STR fault in a scan chain, and C16 is the targeted scan cell. Suppose its state is required to propagate to at least two observation points. As shown in Figure 4, the constraint circuit is drawn within a dash-line box, and the original netlist is drawn outside the box. There are two paths from the targeted scan cell C16 to
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outputs: p1 (b, f, i) and p2 (b, f, h). To sensitize a path, the off-path inputs of all the gates on the path must be set to non-controlling values. For each path, we use an AND gate to judge whether a path is a sensitized or not. In Figure 4, AND gate P1 is used to evaluate path p1, and AND gate P2 is used to evaluate path p2. The inputs of a AND gate are determined by (1) the non-controlling value of the corresponding path, (2) constraints on loaded values and captured values. If the output of the AND gate P1 (P2) is “1”, it means path p1 (p2) can be used for fault propagation. If an off-path non-controlling value or an ATPG constraint is one, it is connected to the AND gate directly. Otherwise, it is inverted before connecting to an input of an AND gate. For the example in Figure 4, on path p1, there are two gates G2 and G5. Let us consider the inputs of gate P1, based on their objectives. (1) To satisfy path sensitization condition. As for G2, the non-controlling value is zero. So C14’s PPI is inverted before connecting to P1. As for G5, the non-controlling value is one. So C5’s PPI is connected directly to another input of P1. (2) To satisfy constraints on loaded value. C5 is a vulnerable-PPI. Since it is required to be “1” to sensitize path p1, it’s protection-PPI C4 has to be set to “1” to avoid “1->0” transition that is sensitive to STR fault. (3) To satisfy constraints on captured value. The output of path p1 is at PPO scan cell C4, which is a vulnerable-PPO. Therefore, its protection-PPO C3 should capture logic “1” to prevent sensitive transition occurring on (C4, C3). Thus, C3’s PPO is connected to one input of gate P1. (4) To satisfy constraints on fault triggering. Scan cells (C16, C15) should be set to (1, 0). Hence C16’s PPI is connected to the AND gate P1 and C15’s PPI is inverted before connecting to P1. (5) To satisfy user-specified value n=2, the outputs of the AND gates P1 and P2 are connected to an AND gate P1P2, which requires both paths be used to observe the state of the targeted cell. As long as the output of P1P2 j is 1, the requirement is satisfied. After the modified netlist has all the constraints, any ATPG tool could be used to derive a test pattern to detect stuck-at 0 fault on the output of the constraint circuit. As shown in Figure 4, we could use ATPG tool to create patterns to detect the stuck-at 0 fault on j (j is declared as circuit PO). Once SA0 at j is detected, it indicates a pattern can set j to 1, and hence satisfy all constraints. In some case we are required to select n paths from M paths (n < M), we use two level AND-OR gates to implement the selection. An example of the 2 paths selection circuit is illustrated in Figure 5.
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4.
Pick 2 Out of 3 Paths
Compound Defect Diagnosis
After the patterns are created, we apply them on the tester and collect the failure log file to run compound defect diagnosis. The whole diagnosis process includes three phases, described as follows. (1) Calculate a weight for each pattern. (2) Calculate load error probability for each scan cell. (3) Calculate the suspect score. We describe these three phases in the following subsections. 4.1
Calculate a Weight for a Pattern
As described in Section 3, we target one scan cell on the faulty chain at a time. For each targeted scan cell Ci, we create a pattern set PatSetCi. Each pattern in PatSetCi is given a weight according to the number of the observation points this pattern propagates the targeted cell to. The sum of the weights for all patterns in PatSetCi is normalized to one. For example, a pattern set PatSetC16 contains two patterns patC16,1 and patC16,2, and the targeted cell is C16.The first pattern patC16,1 propagates the state of C16 to C21, C8 and C4 while the second pattern patC16,2 propagates the state of C16 to C21, C8, C0 and primary output O3. Then the weight of the first pattern is 3/7=0.43, while the weight of the second pattern is 4/7=0.57. Obviously, a pattern is given the highest weight in a pattern set, if it propagates the state of the targeted scan cell to the most number of observation points. Although the example in Figure 3 indicated multiple patterns are necessary to cover one targeted scan cell, in most of cases we found one pattern for a scan cell is enough, given a reasonable n. In that case, its weight is 1. 4.2 Calculate the Load Error Probability of a Scan Cell The load error probability of each targeted scan cell is calculated based on the patterns created for this cell.
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Firstly, Hamming Distance is defined for a created pattern. As for a pattern PatCi,j, the jth pattern created for a targeted cell Ci, Hamming Distance HCi,j is the Hamming Distance on the reliable observation points, between the expected responses and the responses observed on tester. Thereafter, Load Error Probability of a candidate scan cell Ci, denoted as LEP(Ci,j), is calculated by equation 1. LEP (Ci,j) = HCi,j / # of reliable observation points
(1)
We still use the example shown in Figure 2 to explain equation 1. When we target scan cell C16, suppose PatC16,1 propagates the state of C16 to three reliable observation points, scan cells (21, 8, 4) on the faulty chain. Assume the loaded state of C16 is fault-free, the expected machine responses of cells (21, 8, 4) is (1, 1, 1). If we observe on the tester that (21, 8, 4) = (0, 0, 1), then HC16,1 = 2. Therefore, the load error probability of this pattern can be described as LEP (C16, 1)= 2 / 3 = 0.67. Note that when the loaded state of C16 is faulty and no system logic defect exists, the cells (21, 8, 4) should capture (0, 0, 0). In this example scan cell 4 may be contaminated by defects in the system logic. As a result, the state of scan cell 4 captures “1” other than “0”. Based on our experience, the impact of system logic to Hci,j is normally smaller than the impact from the faulty chain. So we know C16 likely has an incorrect loading value in this example. 4.3
Calculate the Suspect Score.
After we have a weight for each pattern and a Load Error Probability of a scan cell for each pattern, it is straightforward to calculate a weighted Load Error Probability, denoted as WLEP(Ci), for each cell Ci and its pattern set. WLEP(Ci) is calculated as equation 2,where w(patCi,j) is the weight of pattern j in pattern set PatSetCi, described in section 4.1 and LEP(ci,j) is the Load Error Probability for scan cell Ci under pattern j. n
WLEP(Ci ) = ∑ w( patCi , j ) × LEP(Ci , j )
(2)
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Still consider the example shown in Figure2. When we target scan cell C16, we have created two patterns: patC16,1 and patC16,2. Suppose the weight of the first pattern is 0.43 and the LEP(C16,1), the load error probability of scan cell 16 under the first pattern is 0.67. Also, assume the weight of the second pattern is 0.57 and the LEP(C16,2), the load error probability of scan cell 16 under the second pattern is 1. The total score of this scan cell is calculated as: WLEP(Ci) = 0.43*0.67+0.57*1=0.86. We plot WLEP(Ci) for all targeted scan cells in a histogram, called p-graph. The x-axis of the p-graph indicates the scan cell indexes and the y-axis represents WLEP for each cell. If we treat the p-graph as a step response graph, the edge of the p-graph is where the score is dramatically changed. Therefore, the location of the edge is most likely the defect location. Edge detection
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in a step response graph is well studied in the signal process theory [22]. Equation 3 is employed to calculate a ranking score ei for each cell Ci. A sliding window with size of 2r+1 is defined for each cell Ci at the center of the sliding window. Ci is calculated with the WLEP of scan cells from i-r to i+r using Equation (3). The maximum of ei is used to detect the edge of p-graph. The fundamental principle of Equation 3 is based on a median filter [19]. Its feature of noise suppression is well-known. So any glitches on the p-graph that may lead to misdiagnosis are likely to be removed and the targeted scan cell which has the highest ranking score ei will be reported as suspect scan cell. According to ei, a graph called suspect profile can be plotted whose peak point indicates the faulty location. Examples of p-graph and suspect profile will be given in the next section.
Flt_type [1] = SA1; Flt_type [2] = SA0 ; Flt_type [3] = STR; Flt_type [4] = STF; Flt_type [5] = FTR; Flt_type [6] = FTF; For (each circuit) { For (chain = 1; chain
Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing 100190, China 2
Graduate University of Chinese Academy of Sciences, Beijing, China {wang_fei, huyu, lihuawei, lxw}@ict.ac.cn
Yu Huang3 3
Mentor Graphics Corporation, 300 Nickerson Rd., Marlborough, MA, 01752, USA [email protected]
Abstract Scan chain failure diagnosis has become an important means for silicon debug and yield improvement. Although plenty of prior work discussed how to perform scan chain diagnosis, most of the previously proposed techniques made an assumption that the system logic is fault-free, which could be an impractical assumption leading to incorrect diagnostic results. In this paper, we propose a scan chain Deterministic Diagnostic Pattern Generation (DDPG) method that can tolerate the faults in the system logic without degradation of chain diagnostic resolution and precision. The entire flow includes three steps. In the first step, patterns are created to propagate the state of a targeted scan cell to as many reliable observation points as possible. In the second step, the load error probability of each targeted scan cell is calculated based on the Hamming Distances between the observed responses and the expected good or faulty responses. In the last step, a suspect profile is plotted, which can be used to identify the suspect scan cell(s) based on ranking scores. Experimental results show that the diagnostic resolution and precision are not degraded even with dozens of faults injected into the system logic.
1.
Introduction
It was reported in [1] that about 10-30% of logic defects cause scan chain failures, while in another paper [2], it was even reported that chain failures account for almost 50% of chip failures. Therefore, scan chain failure diagnosis has become an important research topic in recent years. However, most of the previously proposed software-based chain diagnosis techniques [1] [3-5] [7-9] [11-13] assume the system logic is defect-free. It may be an impractical assumption that leads to incorrect diagnostic results. When scan chain defects and system logic defects co-exist on one chip, it is called compound defects [14]. According to [14], the diagnosis hit rate for compound defects can be smaller than 40% when assuming system logic is defect-free. Although hardware based scan chain defect diagnosis methods [16-18] do not have to make any assumption on the system logic, they are rarely applied to the realistic
industrial designs due to the hardware overhead of the special scan architecture and unconventional DFT flow. Even though some previous work [2] [10] [14-15] proposed some techniques that can diagnose compound defects, to the best of our knowledge, there is no Deterministic Diagnostic Pattern Generation (DDPG) methodology that is proposed to specifically target compound defects yet. In this paper, we proposed a novel DDPG method and a scan chain diagnosis technique that specifically targets compound defects. The rest of the paper is organized as follows. Session 2 explains the fault models used in this paper and reviews some previous work on related topics. Session 3 describes the proposed DDPG algorithm in detail. Session 4 illustrates the proposed diagnosis technique based on the created DDPG patterns. Experimental results are shown in session 5. Session 6 concludes the paper.
2.
Background
2.1 Scan Chain Fault Models To illustrate scan chain diagnosis techniques more easily, each scan cell in a scan chain is given an index. The cell connected to scan-output is numbered 0 and the cells in the chain are numbered incrementally from scan-output to scan-input sequentially. The scan cells between the scan chain input and the scan-input port of a scan cell are called the upstream cells of this scan cell, while the scan cells between the scan chain output and the scan-output port of a scan cell are called the downstream cells of this scan cell. Table 1. Fault models and their effects Model SA0 SA1 STR STF FTR FTF
Expected Scan Out 00001111 11110000 11110000 00001111 11110000 00001111
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Actual Scan Out 00000000 11111111 11100000 00011111 11111000 00000111
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Six types of fault models [1] are studied in this work, including stuck-at high (SA1) and stuck-at low (SA0), slow-to-rise (STR), slow-to-fall (STF), fast-to-rise (FTR), and fast-to-fall (FTF). Table 1 shows the six fault models and their effects on scan chain which consists of 8 scan cells, assuming a flush test pattern “00001111” or “11110000” is shifted in. The affected data is highlighted in underlined bold font. 2.2 Prior Work on Compound Defect Diagnosis and Diagnostic ATPG According to the patterns used for diagnosis, prior software-based chain diagnosis techniques can be classified into three categories: (1) use existing scanbased production test patterns, (2) use existing functional patterns, and (3) generate dedicated diagnostic patterns. The techniques proposed in [14-15] belong to category (1). In [14], an algorithm was proposed to diagnose general compound defects. The failures are first partitioned into two groups by X-simulation. The failure bits in one group are caused by the system logic defects and the failure bits in the other group could be caused by either chain defects or system logic defects. System logic diagnosis techniques and chain diagnosis techniques are applied to those two groups of failures respectively. In [15], a special defect called DACS was explored. DACS stands for Defect that Affect Chain and System logic. However, the method cannot diagnose the compound defects if the scan chain faults are uncorrelated with the system logic faults. The techniques proposed in [2][6][10] belong to category (2). The proposed chain algorithms usually include two parts: (1) use existing functional patterns to get some scan patterns that do not use the scan chain loading procedure so that the impact of chain defects only comes from the chain unloading procedure, and (2) apply heuristics to analyze the test failures and identify the defective cells. The heuristics include signal profiling [2], image recovery [6] and best-alignment [10]. These algorithms can tolerate a few faults in the system logic. All above-mentioned diagnosis techniques may not guarantee to get the best diagnosis results all the time because they do not generate deterministic diagnostic patterns for scan chains. As a result, their effectiveness is largely determined by the diagnosis capability of the existing patterns. Take the signal profiling method [2] as an example. Firstly, the functional test patterns are supposed to bring the circuit through a state sequence as random as possible. The randomness is measured by the signal-1 probability of the flip-flops. Afterwards, a signal profile of scan cells can be obtained from the unloaded patterns. If a scan cell’s signal probability deviates significantly from the
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expected signal-1 probability, it implies that a defect is at the downstream of this cell. However, in practice, sometimes the signal-1 (signal-0) probability of a scan cell is much more dominant than its signal-0 (signal-1) probability. In that case, it requires a very large number of patterns and long clock sequences for each pattern to randomize the signal probability. It might result in two problems: (1) simulation time could be very long and (2) the tester memory capacity might limit the collection of a large number of failing patterns. The analysis motivated us to look into the DDPG solution for compound defect diagnosis. Although DDPG has not been studied for compound defects yet, DDPG techniques for chain diagnosis, assuming system logic is defect-free, were well studied in the past [3][4][5]. DDPG algorithms are either trying to capture certain desired values in the targeted scan cells or to propagate the fault effect to a reliable observation point, including Primary Outputs (POs), good scan chains and cells in the downstream of the faulty cell. The DDPG algorithm proposed in [3] targets one scan cell at a time and starts with the cell at the scan chain input. For each targeted scan cell N, it constrains cell N and all its downstream scan cells in [N-1, 0] to the stuck-at value v. The algorithm first tries to create a test pattern to capture a logic value opposite to the stuck-at fault value v in the targeted scan cell N. Once a test pattern is created for a targeted cell, it will move to its downstream neighbor cell (N-1) and so on so forth. While applying the generated patterns on a tester, if the expected value of the targeted scan cell is observed for the first pattern, it is ascertained that the fault is at the scan-in port of this scan cell. Otherwise the fault must be at the downstream of this cell. So the algorithm continues to examine the tester result of the next pattern, until it finds a cell such that its expected value is correctly observed on the tester. In [4] the technique proposed in [3] was improved by adding one more constraint to the upstream neighbor scan cell of the targeted cell so that the logic dependency between two neighbor scan cells cannot affect diagnostic precision. In [5], a single excitation technique to generate diagnostic patterns was proposed. Each single excitation pattern has only one sensitive bit that can be flipped by the fault. This technique converts the diagnosis problem into a single stuck-at fault ATPG problem, which can be easily solved by existing ATPG tools. In the following sections, we will focus on how to extend DDPG techniques to target compound defect diagnosis.
3.
DDPG for Compound Defects
The basic idea of the proposed DDPG algorithm is to propagate the state of a targeted scan cell to as many reliable observation points as possible. This is different from the previous methods like in [3], [4] or [5], where
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they only require that a fault be propagated to one reliable observation point to be detected. The purpose of propagating the state of the targeted scan cell to multiple reliable observation points is to reduce the impact from the system logic defects. Note that in this paper, we extend the definition of reliable observation points to include the whole faulty chain, if the chain fault is a timing fault (STR, STF, FTR, or FTF). As explained later, more ATPG constraints will be added to guarantee that the captured values can be reliably observed even it is on a faulty chain.
n-1 and repeat the above ATPG procedure. The iteration stops either when we find a set of patterns that can propagate the faulty state of the candidate scan cell to n reliable observation points within Output_Set or when n = 0 (i.e., we cannot create any pattern to reliably detect the faulty state at the candidate scan cell.)
3.1
We made two enhancements in this paper, compared to prior art [3] and [4].
Pattern Generation Algorithm Overview
Figure 1 shows the proposed DDPG flow. There are three inputs for the flow: (1) A targeted scan cell. Like algorithms in [3] [4] [5], our algorithm creates patterns that target one scan cell on the faulty chain at a time. (2) Output_Set. Output_Set contains all observation points that can be reached by the targeted scan cell. This information can be obtained by structural analysis of the circuit-under-diagnosis. (3) n. n is a user-specified value and it defines the minimum number of reliable observation points a pattern has to propagate the state of the targeted cell to. It is obvious that n must be smaller than or equal to the cardinality of Output_Set. We require n>1 in our flow. Output_Set
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Y Save the pattern Delete the observation points from Output_Set N
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End Deterministic (DDPG) Flow
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Initially the algorithm tries to create patterns to propagate the faulty state of the specified candidate scan cell to n reliable observation points within Output_Set. If n is initially set too large such that no patterns can be created to satisfy the requirement, we automatically decrease n to
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(1) Constraints on loaded values
(1.A) Not all scan cells on the faulty chain need constraints. Take a scan chain with stuck-at-v fault as an example. When we target cell N, and assume we want to propagate the state of cell N to a set of selected observation points, we only need constrain the cells that sensitize the fault propagation paths. The other scan cells do not need to be constrained because even if they have wrong values, they do not have any impact on observing the state of cell N at the pre-selected observation points. (1.B) The constrained scan cells can be anywhere on the faulty scan chain instead of having to be in the downstream of the targeted cell N as proposed in [3] [4]. This is because the algorithms in [3] and [4] are based on the assumption that the system logic is defect-free. If this assumption is wrong, the diagnosis result could be also wrong. Take scan chain STR faults as an example, suppose we target cell N and assume one cell M on the faulty chain must be set to a “1” in order to propagate the state of cell N to the selected observation points. No matter whether M is downstream or upstream of cell N, we must constrain cell M’s immediate downstream neighbor (cell M-1) to “1”, which will avoid a “0->1” transition corrupting the loaded value in cell M. Similarly, if the fault type is FTR or FTF, we set the constraint to cell M’s immediate upstream neighbor (cell M+1) to avoid sensitive transition. (2) Constraints on captured values
Y
Figure 1
Note that the above-mentioned pattern generation must satisfy some ATPG constraints. The constraints can be classified into two categories.
(2.A) For stuck-at faults, the reliable observation points include the downstream cells of Lower Bound (LB) in the faulty scan chain, as well as on good scan chains and POs. For SA1 (SA0) fault, we locate LB at the cell that is the closest to the scan chain input and observed a 0 (1) on the tester. For example, if the observed values of a scan chain with stuck-at-1 fault are (11110100), then LB is at scan cell 3. (2.B) For timing faults, we can use all scan cells on the faulty chain as observation points with similar constraints described earlier in (1.B). Take a scan chain FTF fault as an example, suppose we target cell N and assume one cell M (M can be anywhere on the faulty chain) will capture a
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“1”. We must constrain cell M’s immediate upstream neighbor (cell M+1) to “1”, which will avoid a “1->0” transition corrupting the unloaded value in cell M. SI x
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An Example of Diagnosing STR fault with Existing Logic Defect
An example is shown in Figure 2. Suppose there is only one scan chain in the design and the scan chain has one STR fault. When targeting scan cell 16, an attempt is made to propagate its state to the observation points as many as possible. To achieve this, scan cells (19, 14, 5) should be constrained to (0, 0, 1). Since these scan cells are on the faulty scan chain, their loaded values may be distorted by the fault. These scan cells are called vulnerable-PPIs, which are highlighted in light green color in Figure 2. To prevent sensitive transitions from occurring on the vulnerable-PPIs, constraints on the loaded values to their immediate downstream neighbor scan cells (18, 13, 4) have to be applied, as described earlier. These neighbor cells are called protection-PPIs, which are highlighted in dark green color in Figure 2. In this example, since we already constrain cells (19, 14) to (0, 0), no matter what values are loaded to cells (18, 13), the values loaded to cells (19, 14) will not be distorted by a STR chain fault. Therefore, we do not need constrain cells (18, 13). In contrast, scan cell 4 has to be constrained to a “1” to protect scan cell 5 to get a “1”
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during loading. In addition, to trigger a fault on the targeted scan cell, cells (16, 15) should be set to (1, 0). Scan cell 15 is called trigger-PPI, which is highlighted in dark red color in Figure 2. In summary, we set constraints on the loaded states for scan cells (19, 16, 15, 14, 5, 4) as (0, 1, 0, 0, 1, 1). Meanwhile, if an observation point is a PPO in a faulty scan chain, the captured value at the observation point may be distorted by the fault during unloading process. We call such observation points vulnerable-PPOs, which are highlighted in blue color in Figure 2. To avoid sensitive transitions on vulnerable-PPOs, their immediate downstream neighbor scan cells should also be constrained to capture logic “1”. We call these PPOs protection-PPOs, which are highlighted in dark blue color in Figure 2. If all protection-PPOs captured “1”s, there are no sensitive transitions on vulnerable-PPOs, no matter whether the real fault is at the targeted cell or not. Therefore, the observed states at vulnerable-PPOs are reliable. In the example shown in Figure 2, the state of scan cell 16 can be propagated to vulnerable-PPOs at cells (21, 8, 4). Their corresponding protection-PPOs at cells (20, 7, 3) should also capture (1, 1, 1). In ATPG, we try to create patterns under the abovementioned constraints to propagate the state of the targeted scan cell to as many observation points in Output_Set as possible. If a pattern is successfully created, it is saved out and the corresponding observation points are deleted from Output_Set. The iteration repeats until we delete all observation points from Output_Set or no valid patterns can be created.
Figure 3
Cover the Output_Set by Three Patterns
To illustrate our ATPG iterations, we use an example shown in Figure 3. Assume the state of a targeted scan cell C16 has logic path to scan cell C21, C16, C8, C4, C0 and a primary output O3. Initially Output_Set consists of C21, C16, C8, C4, C0 and O3. Suppose user sets n = 2, and assume a pattern patC16,1 can be created under the constraints to propagate C16’s state to scan cell C21, C8, and C4. These 3 observation points are deleted from Output_Set after we save out patC16,1. The remaining observation points in Output_Set are C16, C0 and O3. Assume another pattern patC16,2 can be created to propagate the state of C16 to C0, O3. We delete these two observation points from Output_Set. Finally a pattern
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patC16,3 can be created to cover the last observation point C16. All observation points in Outputs_Set are covered with 3 patterns. Note that some observation point may be covered by multiple patterns, as the example shown in Figure 3. 3.2
Netlist Modification and Paths Sensitization
We may have two solutions to create patterns. One solution is to use ATPG constraints, which are supported by most commercial ATPG tools. Another solution is to modify the original netlist to add the constraints if an ATPG do not support ATPG constraints. Any ATPG tool or SAT solver can be employed as pattern generation engine on this modified netlist and the netlist modification technique can be translated into ATPG constraints. In our experiment, we use the second solution. In this subsection, we first illustrate the technique of netlist modification through an example. Next, we illustrate how to sensitize multiple paths by a general ATPG tool. A modified netlist includes two parts: one part is the original netlist, and the other part is the constraint circuit. Constraint circuit is built based on the structure of the original netlist and the constraints we discussed in the previous subsection. We explain the construction process of the constraint circuit by an example shown in Figure 4.
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Sensitize Multiple Paths to Diagnose STR Fault Using Stuck-at ATPG Tools
Assume there is a STR fault in a scan chain, and C16 is the targeted scan cell. Suppose its state is required to propagate to at least two observation points. As shown in Figure 4, the constraint circuit is drawn within a dash-line box, and the original netlist is drawn outside the box. There are two paths from the targeted scan cell C16 to
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outputs: p1 (b, f, i) and p2 (b, f, h). To sensitize a path, the off-path inputs of all the gates on the path must be set to non-controlling values. For each path, we use an AND gate to judge whether a path is a sensitized or not. In Figure 4, AND gate P1 is used to evaluate path p1, and AND gate P2 is used to evaluate path p2. The inputs of a AND gate are determined by (1) the non-controlling value of the corresponding path, (2) constraints on loaded values and captured values. If the output of the AND gate P1 (P2) is “1”, it means path p1 (p2) can be used for fault propagation. If an off-path non-controlling value or an ATPG constraint is one, it is connected to the AND gate directly. Otherwise, it is inverted before connecting to an input of an AND gate. For the example in Figure 4, on path p1, there are two gates G2 and G5. Let us consider the inputs of gate P1, based on their objectives. (1) To satisfy path sensitization condition. As for G2, the non-controlling value is zero. So C14’s PPI is inverted before connecting to P1. As for G5, the non-controlling value is one. So C5’s PPI is connected directly to another input of P1. (2) To satisfy constraints on loaded value. C5 is a vulnerable-PPI. Since it is required to be “1” to sensitize path p1, it’s protection-PPI C4 has to be set to “1” to avoid “1->0” transition that is sensitive to STR fault. (3) To satisfy constraints on captured value. The output of path p1 is at PPO scan cell C4, which is a vulnerable-PPO. Therefore, its protection-PPO C3 should capture logic “1” to prevent sensitive transition occurring on (C4, C3). Thus, C3’s PPO is connected to one input of gate P1. (4) To satisfy constraints on fault triggering. Scan cells (C16, C15) should be set to (1, 0). Hence C16’s PPI is connected to the AND gate P1 and C15’s PPI is inverted before connecting to P1. (5) To satisfy user-specified value n=2, the outputs of the AND gates P1 and P2 are connected to an AND gate P1P2, which requires both paths be used to observe the state of the targeted cell. As long as the output of P1P2 j is 1, the requirement is satisfied. After the modified netlist has all the constraints, any ATPG tool could be used to derive a test pattern to detect stuck-at 0 fault on the output of the constraint circuit. As shown in Figure 4, we could use ATPG tool to create patterns to detect the stuck-at 0 fault on j (j is declared as circuit PO). Once SA0 at j is detected, it indicates a pattern can set j to 1, and hence satisfy all constraints. In some case we are required to select n paths from M paths (n < M), we use two level AND-OR gates to implement the selection. An example of the 2 paths selection circuit is illustrated in Figure 5.
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Sensitized path detector Path 1
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Pick 2 Out of 3 Paths
Compound Defect Diagnosis
After the patterns are created, we apply them on the tester and collect the failure log file to run compound defect diagnosis. The whole diagnosis process includes three phases, described as follows. (1) Calculate a weight for each pattern. (2) Calculate load error probability for each scan cell. (3) Calculate the suspect score. We describe these three phases in the following subsections. 4.1
Calculate a Weight for a Pattern
As described in Section 3, we target one scan cell on the faulty chain at a time. For each targeted scan cell Ci, we create a pattern set PatSetCi. Each pattern in PatSetCi is given a weight according to the number of the observation points this pattern propagates the targeted cell to. The sum of the weights for all patterns in PatSetCi is normalized to one. For example, a pattern set PatSetC16 contains two patterns patC16,1 and patC16,2, and the targeted cell is C16.The first pattern patC16,1 propagates the state of C16 to C21, C8 and C4 while the second pattern patC16,2 propagates the state of C16 to C21, C8, C0 and primary output O3. Then the weight of the first pattern is 3/7=0.43, while the weight of the second pattern is 4/7=0.57. Obviously, a pattern is given the highest weight in a pattern set, if it propagates the state of the targeted scan cell to the most number of observation points. Although the example in Figure 3 indicated multiple patterns are necessary to cover one targeted scan cell, in most of cases we found one pattern for a scan cell is enough, given a reasonable n. In that case, its weight is 1. 4.2 Calculate the Load Error Probability of a Scan Cell The load error probability of each targeted scan cell is calculated based on the patterns created for this cell.
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Firstly, Hamming Distance is defined for a created pattern. As for a pattern PatCi,j, the jth pattern created for a targeted cell Ci, Hamming Distance HCi,j is the Hamming Distance on the reliable observation points, between the expected responses and the responses observed on tester. Thereafter, Load Error Probability of a candidate scan cell Ci, denoted as LEP(Ci,j), is calculated by equation 1. LEP (Ci,j) = HCi,j / # of reliable observation points
(1)
We still use the example shown in Figure 2 to explain equation 1. When we target scan cell C16, suppose PatC16,1 propagates the state of C16 to three reliable observation points, scan cells (21, 8, 4) on the faulty chain. Assume the loaded state of C16 is fault-free, the expected machine responses of cells (21, 8, 4) is (1, 1, 1). If we observe on the tester that (21, 8, 4) = (0, 0, 1), then HC16,1 = 2. Therefore, the load error probability of this pattern can be described as LEP (C16, 1)= 2 / 3 = 0.67. Note that when the loaded state of C16 is faulty and no system logic defect exists, the cells (21, 8, 4) should capture (0, 0, 0). In this example scan cell 4 may be contaminated by defects in the system logic. As a result, the state of scan cell 4 captures “1” other than “0”. Based on our experience, the impact of system logic to Hci,j is normally smaller than the impact from the faulty chain. So we know C16 likely has an incorrect loading value in this example. 4.3
Calculate the Suspect Score.
After we have a weight for each pattern and a Load Error Probability of a scan cell for each pattern, it is straightforward to calculate a weighted Load Error Probability, denoted as WLEP(Ci), for each cell Ci and its pattern set. WLEP(Ci) is calculated as equation 2,where w(patCi,j) is the weight of pattern j in pattern set PatSetCi, described in section 4.1 and LEP(ci,j) is the Load Error Probability for scan cell Ci under pattern j. n
WLEP(Ci ) = ∑ w( patCi , j ) × LEP(Ci , j )
(2)
j =1
Still consider the example shown in Figure2. When we target scan cell C16, we have created two patterns: patC16,1 and patC16,2. Suppose the weight of the first pattern is 0.43 and the LEP(C16,1), the load error probability of scan cell 16 under the first pattern is 0.67. Also, assume the weight of the second pattern is 0.57 and the LEP(C16,2), the load error probability of scan cell 16 under the second pattern is 1. The total score of this scan cell is calculated as: WLEP(Ci) = 0.43*0.67+0.57*1=0.86. We plot WLEP(Ci) for all targeted scan cells in a histogram, called p-graph. The x-axis of the p-graph indicates the scan cell indexes and the y-axis represents WLEP for each cell. If we treat the p-graph as a step response graph, the edge of the p-graph is where the score is dramatically changed. Therefore, the location of the edge is most likely the defect location. Edge detection
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in a step response graph is well studied in the signal process theory [22]. Equation 3 is employed to calculate a ranking score ei for each cell Ci. A sliding window with size of 2r+1 is defined for each cell Ci at the center of the sliding window. Ci is calculated with the WLEP of scan cells from i-r to i+r using Equation (3). The maximum of ei is used to detect the edge of p-graph. The fundamental principle of Equation 3 is based on a median filter [19]. Its feature of noise suppression is well-known. So any glitches on the p-graph that may lead to misdiagnosis are likely to be removed and the targeted scan cell which has the highest ranking score ei will be reported as suspect scan cell. According to ei, a graph called suspect profile can be plotted whose peak point indicates the faulty location. Examples of p-graph and suspect profile will be given in the next section.
Flt_type [1] = SA1; Flt_type [2] = SA0 ; Flt_type [3] = STR; Flt_type [4] = STF; Flt_type [5] = FTR; Flt_type [6] = FTF; For (each circuit) { For (chain = 1; chain
