Dual-Mode Switched-Capacitor DC-DC Converter for Subthreshold ...
Dual-Mode Switched-Capacitor DC-DC Converter for Subthreshold Processors with Deep Sleep Mode Julien De Vos, David Bol, Denis Flandre ICTEAM institute, Université catholique de Louvain, Belgium [email protected],[email protected],[email protected]
Abstract— Wireless sensor networks motivate the development of ultra-low power nodes based on subthreshold processors. As such applications are highly duty cycled, subthreshold processors must support two modes of operation: active mode and sleep mode in which RAM, timer and interrupt control must nevertheless remain powered on. In this paper, we propose a dual-mode switched-capacitor DC-DC converter to power such subthreshold processors with high efficiencies in both modes. It delivers a 0.4V output voltage from a 1-1.2V input source. Simulations in 0.13µm CMOS technology show that the efficiency reaches 74% on a 100µW load, corresponding to the processor active mode. Adaptive body biasing and adaptive internal clock generation supplied by the output voltage allow the converter to maintain an efficiency of 60% on a load as low as 100nW, corresponding to the processor sleep mode.
I.
INTRODUCTION
The vision of energy-autonomous applications is becoming a reality [1]. Increasing needs for distributed electronics, such as wireless sensor networks, has led to the development of ultra-low-power circuits. Subthreshold processors operating with a supply voltage VDD as low as 0.3-0.5V and consuming less than 30pJ per clock cycle have been demonstrated [2]. In order to save even more average power, these processors can enter a deep sleep mode, with power and clock gating techniques [2][3][4]. Combined with energy harvesting techniques, some applications are able to last for decades without the need for battery replacement [3]. However few DC-DC converters have been proposed to supply such ultra-low-power processors with 0.3-0.5 VDD, from the main supply at 1-1.2V used for I/Os and peripherals. Traditional buck converters suffer from their need of an inductor, which is not efficient at low load [1]. LowDropOut linear regulators (LDO) and other purely linear converters need a quiescent current to work properly. This is hardly acceptable if they need to power a load below 1µW. Switched-Capacitor (SC) converters are promising for such applications. In [2], [5] and [7] the authors contributed to the development of SC converters with a large output voltage range. The converters were developed for a processor using dynamic voltage scaling (DVS) techniques. However these converters fail to efficiently power loads below 1µW associated with sleep mode [6]. Let us indeed mention that the ultra-low VDD delivered by the converter must be maintained in sleep mode for data retention of subthreshold SRAM memories and always-on circuitry such as timers and interrupt
controller. In this paper we propose a new approach focusing on two operation modes. The purpose is to efficiently supply an ultralow power processor consuming typically 100µW in active mode, with the capability of entering a sleep mode at 100nW. It is assumed that the converter is operating in subthreshold region with a 400mV ultra-low VDD. The proposed architecture can of course be transposed to other operating points. For powering such light loads, it is critical to observe an extremely tight power budget for the circuitry of the converter. To help in this task, we use adaptive body bias techniques for some of the converter switches and we power some converter’s circuitries with the low output voltage, allowing adaptive internal clock generation. This paper is organized as follows. Section II reviews switched-capacitors converter concepts. Section III describes the structure of the proposed converter. Section IV presents the simulation results and Section V the conclusions. II.
SWITCHED-CAPACITOR CONVERTERS
In SC converters, capacitors are used to transfer charges from the input to the load circuits. As stated in Eq. (1) the transferred power (Pload) depends on the frequency (fs) at which charges are transferred to the load, the total value of the transfer capacitors (CT), the difference between loaded and unloaded output voltage (∆V) and the output voltage (VOUT): (1) Pload = f s C T V OUT Δ V Let us quickly review the main contributors to efficiency loss in SC converters. Previously-reported solutions to minimize them are also presented. A. Linear losses SC converters use passive components for the power conversion. Therefore the efficiency is limited to a maximal value (nmax) depending on the topology of the capacitor networks, the input voltage (VIN), and the output voltage (VOUT) [8]: 1 VOUT (2) n max = M V IN where M is the conversion ratio at no load. As the load current increases, VOUT has to be decreased in order to allow the converter’s transfer capacitors to provide enough charge to the output. It is possible to choose M such that these losses are
Fig. 1. Architecture of the proposed switched-capacitor DC-DC converter.
minimized. However, if the powered circuits have to operate over a wide voltage range, a reconfigurable array of capacitors [2] should be used to keep these losses reasonable. B. Bottom-plate capacitance losses When considering front-end MOS or back-end MIM (MetalInsulator-Metal) capacitors, a parasitic capacitance appears between the bottom plate of the transfer capacitors and the substrate. If the bottom plate is switching, this capacitor is charged and discharged. This switching does not contribute to the energy transfer and is thus unwanted. Capacitors built close to the substrate such as MOS capacitors should therefore be avoided. Moreover, the use of Pulse Frequency Modulation (PFM) instead of Pulse Width Modulation (PWM) reduces the number of switching of this capacitor [5]. C. Gate switch losses The switches in the capacitor network typically use wide transistors. Charging and discharging the gate capacitances of these transistors induce losses. A common way to minimize them is to dynamically adapt the size of the switches to the current to be driven [5]. PFM also reduces the gate switching. D. Control losses Finally, there are losses in all the control circuits such as comparators or clock generation. Analog circuits hungry for quiescent current should be avoided. Low power techniques for digital circuits such as subthreshold design or body biasing can be useful. This is the object of this paper. III.
PROPOSED CONVERTER ARCHITECTURE
The present converter needs to be operated either in Medium-Power (MP) mode or in Ultra-Low-Power (ULP) mode, corresponding to the active and sleep modes of a subthreshold processor respectively. Typical associated loads are 100µW and 100nW. Fig. 1 shows the proposed topology. MP and ULP modes are successively discussed in this section. A. MP mode This mode aims at powering a subthreshold processor in active mode with a 100µW typical load. First a clocked comparator senses the output voltage. The assumption is made here that the processor uses an external clock close to 20MHz, which will also be used for the comparator. As long as the output voltage is higher than the reference voltage VREF, a
Fig. 2. Capacitor network. Switches S3, S4 and S5 can be body biased. S1 is built with PMOS, S2 to S5 are build with NMOS.
TRIGGER signal remains low so that S1 and S3 switches charge the transfer capacitors C1 and C2 to VDD/2 (Fig. 2), with no transmission to the output. If VOUT falls under VREF, the comparator forces the TRIGGER signal, and control signals for the switches of the capacitor networks are generated by the non overlapping clock block. This block ensures that S1 and S3 are never closed at the same time as S2, S4 and S5. When it receives a TRIGGER signal from the comparator it closes S2, S4 and S5 so that charges are transferred to the load. This makes VOUT rise higher than VREF. The clock generator and level shifter block is not used in MP mode. A look at the schematic of the capacitor network (Fig. 2) shows that NMOS of S3, S4, and S5 are reverse body biased if the body contact is connected to ground. Indeed, the source of transistors in switches S3, S4 and S5 are connected to the upper plate of C1 or C2. This leads to a lower ON current for these devices and therefore to the need for wider devices. This induces high gate switch losses. One way to reduce this is to connect the body of these transistors to the output voltage. This is done by BB Switch block. Simulations show that this allows for reducing the size of the devices by a factor of 1.6×. B. ULP mode The purpose of ULP mode is to supply a subthreshold processor in sleep mode, with a 100nW typical load for SRAM data retention and always-on circuitry. This mode is primarily similar to MP mode with key differences. 1) According to Eq. (1), either smaller transfer capacitors or a lower clock frequency can be used to accommodate the load of only hundreds of nWs. Clocking the comparator with the external 20MHz clock signal consumes prohibitive power as compared to the ultra-low load in this mode. Therefore an internal clock generator is added to the architecture. Thus the choice was made to operate at low frequency and to keep the same transfer capacitors. The clock generator is made of 57 inverters forming a ring oscillator. It does not have to generate a precise frequency. In order to reduce the frequency as well as the consumption of the ring oscillator this block is not supplied by the high input voltage but by the low output voltage. Moreover, long-channel MOSFET devices are used to further limit the clock frequency and thereby the power consumption. The generated clock frequency is approximately 80 kHz at 0.4V and typical conditions (Fig. 3). As the clock generator uses the output voltage, the converter needs to be started in MP mode.
Fig. 3. Frequency generated by the clock generator based on a 57-stage inverter ring oscillator, at 25°C. The frequency increases with the output voltage as the ring oscillator is supplied by the output voltage.
Fig. 4. Efficiency of the converter with varying load power.
2) As the switches have more time to transfer charges to the capacitor, smaller devices can be used. As shown in Fig. 2, two devices have been used for each switch. The largest one is used in MP mode and the smallest one for ULP mode. Finally, in order to reduce leakage of switches S3, S4 and S5, the body bias used in MP mode is cancelled. The transistors of these switches are therefore reverse body biased, which efficiently reduces their leakage. IV.
SIMULATION RESULTS
SPICE simulations of the proposed circuit have been carried out. Results are obtained using foundry models of a 0.13µm CMOS technology. Unless otherwise specified, the temperature is 25°C, the input voltage is 1V and the output voltage is 0.4V. In this case, the values for M, and nmax from Eq. (2) are 0.5, and 80% respectively. Efficiency nlin of a linear converter would be the conversion ratio. In this case it is 40%. The total on-chip capacitance for charge transfer is 200pF built with MIM capacitors. MIM capacitors have been chosen because they are further away from the substrate, allowing a reduction of bottom-plate capacitance losses. As in Fig. 1, an output capacitor CLOAD of 2nF is added. This capacitor reduces voltage ripple at the output. Simulated ripple is less than 10mV and 15mV in MP and ULP mode. This
Fig. 5. Efficiency of the converter with varying reference voltage. Load is set to 100µW for MP mode and to 100nW for ULP mode.
Fig. 6. Efficiency of the converter with varying input voltage. Load is set to 100µW for MP mode and to 100 nW for ULP mode.
capacitor could be off-chip or on-chip using MOS capacitors for higher density. Results are presented in Fig. 3 to 6. Fig. 4 demonstrates that the use of a dual-mode converter yields a good efficiency over a wide range of loads from 100µW down to 100nW. At 500nW, the efficiency in ULP mode is close to the ideal limit of a SC converter in such configuration (80%). For higher loads, VOUT starts to drop because the transfer capacitors cannot supply enough charges to CLOAD at such low frequency. As stated in Eq. (2), efficiency thus falls as VOUT decreases. Converter must therefore switch to MP mode for higher loads. Efficiency drops below nlin for loads below 30nW due to control losses. The same behavior is observed in MP mode with peak efficiency around 100µW. Fig. 3 and 5 show the benefits of using the output voltage to supply the ring oscillators in ULP mode. With a fixed external clock, MP mode fails to follow VREF above 420mV whereas ULP mode can go up to 450mV. Indeed as VOUT increases, the frequency of the ring oscillator increases too, thereby allowing charges to be transferred to the output more often as shown in Eq. (1). Similarly when VOUT decreases, more charges are transferred to the output for each switching. Therefore, few switchings are needed and the automatic clock frequency
Metric Technology Area Input voltage [V] Output voltage [V] Load range
Table I - Comparison with recent SC DC-DC converters. This work [5] [2] [9] 130nm 180nm 65nm 130nm 0.13 mm² 0.57mm² 0.12mm² 0.26mm² 1-1.2 1.8 1.2 2.5 - 3.6
Peak efficiency Efficiency at 100nW
0.3 - 0.4
0.3 - 1.1
0.3 - 1.1
0.44
10nW-125µW
5µW1mW 74% @50µW NA
1µW-0.5mW
2nW250nW 56% @13µW 44%
74% @100µW 74% @500nW 60%
78% @50µW NA (56% @ 500nW)
scaling reduces losses in control circuitry. Fig. 6 shows the efficiency variations with the input voltage. As given by Eq. (2), it decreases as the input voltage increases, following the theoretical efficiency limit. Table I compares the converter performances with state-ofthe-art switched-capacitors converters. In [2] and [5], the converter is designed to supply a dynamic voltage scaled (DVS) processor. They use a reconfigurable array of capacitors, in order to be able to create a large range of output voltage. They also use PFM and varying switch size to reduce losses of the converter. In [9], an SC converter and an LDO regulator are used together to address low-power loads requirements. The table shows that for medium loads of tenths of µWs the proposed converter has a similar efficiency to recent works whereas for ultra-low loads a significant improvement is obtained. A corner analysis was also performed to further validate the robustness of the proposed circuit. Simulations show that the worst-case corner for functionality is with small capacitors at low temperature with slow devices, which limits subthreshold current [10]. Small capacitors reduce the CT in Eq. (1) and therefore limit the charges that can be transmitted to the load at each cycle. The other corners reduce the ON current of the switches. The devices have more difficulties to transfer charges from the input to CT or from CT to the load within the time they are turned ON. This reduces also the power that can be transferred to the load. Fig. 7 shows the maximal output voltage that can be delivered by the converter for increasing loads. Worst-case corners are shown and compared to typical conditions. In ULP mode, the clock generator and level shifter block fails at extremely low temperature for loads higher than 250nW because the output voltage becomes too low. Indeed under these conditions the generated clock frequency is lower, thereby limiting the output power as stated in Eq. (1) and reducing the maximal output voltage. V.
CONCLUSION
This paper presents a dual-mode switched-capacitor DC-DC converter for supplying subthreshold processors. The converter is implemented and simulated in a commercial 0.13µm CMOS technology. It transfers charges from a 1V1.2V DC input to a 0.3-0.4V DC output. The medium-power (MP) mode corresponds to the processor active mode with up to 125 µW load and the ULP (Ultra-Low-Power) mode fits processor sleep mode up to 500nW. In MP mode, efficiency
Fig. 7. Maximal VOUT for increasing output power in (a) MP and (b) ULP mode. ULP mode fails at low temperature for loads bigger than 250nW.
reaches 74% for 100µW loads which is close to state-of-theart switched capacitor converters. Thanks to adaptive body biasing and adaptive internal clock generation supplied by the output voltage, the efficiency in ULP mode reaches 74% for 500nW loads and remains above 60% for loads as low as 100nW. ACKNOWLEDGMENT J. De Vos and D. Bol are with Université catholique de Louvain as research fellow and postdoctoral researcher, respectively, from the National Foundation for Scientific Research (FNRS) of Belgium. REFERENCES [1]
M. Belleville et al, “Energy Autonomous Sensor Systems: State and Perspectives of a Ubiquitous Sensor Technology,” in Advances in sensors and interfaces IWASI, 2009, pp. 134-138. [2] J. Kwong et al, “A 65 nm sub Vt Microcontroller with Integrated SRAM and Switched Capacitor DC-DC Converter”, in Journal of solid state circuits, vol.44, no.1, Jan. 2009, pp. 115-126. [3] G. Chen et al, “Millimeter-scale Nearly Perpetual Sensor System with Stacked Battery and Solar Cells”, in Int. Solid State Circuits Conf. ISSCC, 2010, pp. 288-289. [4] D. Bol et al, “ Robustness-Aware Sleep Transistor Engineering for Power-Gated Nanometer Sub threshold Circuits”, International Symposium on Circuits and Systems ISCAS, 2010, pp. 1484-1487. [5] Y. Ramadass abd A. Chandrakasan, “Voltage scalable switched capacitor DC-DC converter for ultra-low-power on-chip applications” in Power Electronics Specialists Conference PESC, 2007, pp. 2353-2359. [6] MSP430™16-bit Ultra-Low Power MCUs datasheet, Texas Instrument, available at www.ti.com, 2005. [7] O. A-T. Hasib, “Fully Integrated Ultra-Low-Power Asynchronously Driven Step-Down DC-DC Converter”, in Int. Symp. On Circuits and System ISCAS, 2010, pp. 877-880. [8] M. S. Makowski and D.Maksimovic,” Performance limits of switchedcapacitor DC-DC converters”, in Power Electronics Specialist Conference PESC, 1995, pp. 1215-1221, vol. 2. [9] M. Wieckowski et al, “A Hybrid DC-DC Converter for Sub-Microwatt Sub 1-V Implantable Applications”, in Symposium. on VLSI circuits , 2009, pp. 166-167. [10] D. Bol et al, “The Detrimental Impact of Negative Celsius Temperature on Ultra-Low-Voltage CMOS Logic”, European Solid-State CIRcuits Conference ESSCIRC, 2010, (accepted paper to be published).
Abstract— Wireless sensor networks motivate the development of ultra-low power nodes based on subthreshold processors. As such applications are highly duty cycled, subthreshold processors must support two modes of operation: active mode and sleep mode in which RAM, timer and interrupt control must nevertheless remain powered on. In this paper, we propose a dual-mode switched-capacitor DC-DC converter to power such subthreshold processors with high efficiencies in both modes. It delivers a 0.4V output voltage from a 1-1.2V input source. Simulations in 0.13µm CMOS technology show that the efficiency reaches 74% on a 100µW load, corresponding to the processor active mode. Adaptive body biasing and adaptive internal clock generation supplied by the output voltage allow the converter to maintain an efficiency of 60% on a load as low as 100nW, corresponding to the processor sleep mode.
I.
INTRODUCTION
The vision of energy-autonomous applications is becoming a reality [1]. Increasing needs for distributed electronics, such as wireless sensor networks, has led to the development of ultra-low-power circuits. Subthreshold processors operating with a supply voltage VDD as low as 0.3-0.5V and consuming less than 30pJ per clock cycle have been demonstrated [2]. In order to save even more average power, these processors can enter a deep sleep mode, with power and clock gating techniques [2][3][4]. Combined with energy harvesting techniques, some applications are able to last for decades without the need for battery replacement [3]. However few DC-DC converters have been proposed to supply such ultra-low-power processors with 0.3-0.5 VDD, from the main supply at 1-1.2V used for I/Os and peripherals. Traditional buck converters suffer from their need of an inductor, which is not efficient at low load [1]. LowDropOut linear regulators (LDO) and other purely linear converters need a quiescent current to work properly. This is hardly acceptable if they need to power a load below 1µW. Switched-Capacitor (SC) converters are promising for such applications. In [2], [5] and [7] the authors contributed to the development of SC converters with a large output voltage range. The converters were developed for a processor using dynamic voltage scaling (DVS) techniques. However these converters fail to efficiently power loads below 1µW associated with sleep mode [6]. Let us indeed mention that the ultra-low VDD delivered by the converter must be maintained in sleep mode for data retention of subthreshold SRAM memories and always-on circuitry such as timers and interrupt
controller. In this paper we propose a new approach focusing on two operation modes. The purpose is to efficiently supply an ultralow power processor consuming typically 100µW in active mode, with the capability of entering a sleep mode at 100nW. It is assumed that the converter is operating in subthreshold region with a 400mV ultra-low VDD. The proposed architecture can of course be transposed to other operating points. For powering such light loads, it is critical to observe an extremely tight power budget for the circuitry of the converter. To help in this task, we use adaptive body bias techniques for some of the converter switches and we power some converter’s circuitries with the low output voltage, allowing adaptive internal clock generation. This paper is organized as follows. Section II reviews switched-capacitors converter concepts. Section III describes the structure of the proposed converter. Section IV presents the simulation results and Section V the conclusions. II.
SWITCHED-CAPACITOR CONVERTERS
In SC converters, capacitors are used to transfer charges from the input to the load circuits. As stated in Eq. (1) the transferred power (Pload) depends on the frequency (fs) at which charges are transferred to the load, the total value of the transfer capacitors (CT), the difference between loaded and unloaded output voltage (∆V) and the output voltage (VOUT): (1) Pload = f s C T V OUT Δ V Let us quickly review the main contributors to efficiency loss in SC converters. Previously-reported solutions to minimize them are also presented. A. Linear losses SC converters use passive components for the power conversion. Therefore the efficiency is limited to a maximal value (nmax) depending on the topology of the capacitor networks, the input voltage (VIN), and the output voltage (VOUT) [8]: 1 VOUT (2) n max = M V IN where M is the conversion ratio at no load. As the load current increases, VOUT has to be decreased in order to allow the converter’s transfer capacitors to provide enough charge to the output. It is possible to choose M such that these losses are
Fig. 1. Architecture of the proposed switched-capacitor DC-DC converter.
minimized. However, if the powered circuits have to operate over a wide voltage range, a reconfigurable array of capacitors [2] should be used to keep these losses reasonable. B. Bottom-plate capacitance losses When considering front-end MOS or back-end MIM (MetalInsulator-Metal) capacitors, a parasitic capacitance appears between the bottom plate of the transfer capacitors and the substrate. If the bottom plate is switching, this capacitor is charged and discharged. This switching does not contribute to the energy transfer and is thus unwanted. Capacitors built close to the substrate such as MOS capacitors should therefore be avoided. Moreover, the use of Pulse Frequency Modulation (PFM) instead of Pulse Width Modulation (PWM) reduces the number of switching of this capacitor [5]. C. Gate switch losses The switches in the capacitor network typically use wide transistors. Charging and discharging the gate capacitances of these transistors induce losses. A common way to minimize them is to dynamically adapt the size of the switches to the current to be driven [5]. PFM also reduces the gate switching. D. Control losses Finally, there are losses in all the control circuits such as comparators or clock generation. Analog circuits hungry for quiescent current should be avoided. Low power techniques for digital circuits such as subthreshold design or body biasing can be useful. This is the object of this paper. III.
PROPOSED CONVERTER ARCHITECTURE
The present converter needs to be operated either in Medium-Power (MP) mode or in Ultra-Low-Power (ULP) mode, corresponding to the active and sleep modes of a subthreshold processor respectively. Typical associated loads are 100µW and 100nW. Fig. 1 shows the proposed topology. MP and ULP modes are successively discussed in this section. A. MP mode This mode aims at powering a subthreshold processor in active mode with a 100µW typical load. First a clocked comparator senses the output voltage. The assumption is made here that the processor uses an external clock close to 20MHz, which will also be used for the comparator. As long as the output voltage is higher than the reference voltage VREF, a
Fig. 2. Capacitor network. Switches S3, S4 and S5 can be body biased. S1 is built with PMOS, S2 to S5 are build with NMOS.
TRIGGER signal remains low so that S1 and S3 switches charge the transfer capacitors C1 and C2 to VDD/2 (Fig. 2), with no transmission to the output. If VOUT falls under VREF, the comparator forces the TRIGGER signal, and control signals for the switches of the capacitor networks are generated by the non overlapping clock block. This block ensures that S1 and S3 are never closed at the same time as S2, S4 and S5. When it receives a TRIGGER signal from the comparator it closes S2, S4 and S5 so that charges are transferred to the load. This makes VOUT rise higher than VREF. The clock generator and level shifter block is not used in MP mode. A look at the schematic of the capacitor network (Fig. 2) shows that NMOS of S3, S4, and S5 are reverse body biased if the body contact is connected to ground. Indeed, the source of transistors in switches S3, S4 and S5 are connected to the upper plate of C1 or C2. This leads to a lower ON current for these devices and therefore to the need for wider devices. This induces high gate switch losses. One way to reduce this is to connect the body of these transistors to the output voltage. This is done by BB Switch block. Simulations show that this allows for reducing the size of the devices by a factor of 1.6×. B. ULP mode The purpose of ULP mode is to supply a subthreshold processor in sleep mode, with a 100nW typical load for SRAM data retention and always-on circuitry. This mode is primarily similar to MP mode with key differences. 1) According to Eq. (1), either smaller transfer capacitors or a lower clock frequency can be used to accommodate the load of only hundreds of nWs. Clocking the comparator with the external 20MHz clock signal consumes prohibitive power as compared to the ultra-low load in this mode. Therefore an internal clock generator is added to the architecture. Thus the choice was made to operate at low frequency and to keep the same transfer capacitors. The clock generator is made of 57 inverters forming a ring oscillator. It does not have to generate a precise frequency. In order to reduce the frequency as well as the consumption of the ring oscillator this block is not supplied by the high input voltage but by the low output voltage. Moreover, long-channel MOSFET devices are used to further limit the clock frequency and thereby the power consumption. The generated clock frequency is approximately 80 kHz at 0.4V and typical conditions (Fig. 3). As the clock generator uses the output voltage, the converter needs to be started in MP mode.
Fig. 3. Frequency generated by the clock generator based on a 57-stage inverter ring oscillator, at 25°C. The frequency increases with the output voltage as the ring oscillator is supplied by the output voltage.
Fig. 4. Efficiency of the converter with varying load power.
2) As the switches have more time to transfer charges to the capacitor, smaller devices can be used. As shown in Fig. 2, two devices have been used for each switch. The largest one is used in MP mode and the smallest one for ULP mode. Finally, in order to reduce leakage of switches S3, S4 and S5, the body bias used in MP mode is cancelled. The transistors of these switches are therefore reverse body biased, which efficiently reduces their leakage. IV.
SIMULATION RESULTS
SPICE simulations of the proposed circuit have been carried out. Results are obtained using foundry models of a 0.13µm CMOS technology. Unless otherwise specified, the temperature is 25°C, the input voltage is 1V and the output voltage is 0.4V. In this case, the values for M, and nmax from Eq. (2) are 0.5, and 80% respectively. Efficiency nlin of a linear converter would be the conversion ratio. In this case it is 40%. The total on-chip capacitance for charge transfer is 200pF built with MIM capacitors. MIM capacitors have been chosen because they are further away from the substrate, allowing a reduction of bottom-plate capacitance losses. As in Fig. 1, an output capacitor CLOAD of 2nF is added. This capacitor reduces voltage ripple at the output. Simulated ripple is less than 10mV and 15mV in MP and ULP mode. This
Fig. 5. Efficiency of the converter with varying reference voltage. Load is set to 100µW for MP mode and to 100nW for ULP mode.
Fig. 6. Efficiency of the converter with varying input voltage. Load is set to 100µW for MP mode and to 100 nW for ULP mode.
capacitor could be off-chip or on-chip using MOS capacitors for higher density. Results are presented in Fig. 3 to 6. Fig. 4 demonstrates that the use of a dual-mode converter yields a good efficiency over a wide range of loads from 100µW down to 100nW. At 500nW, the efficiency in ULP mode is close to the ideal limit of a SC converter in such configuration (80%). For higher loads, VOUT starts to drop because the transfer capacitors cannot supply enough charges to CLOAD at such low frequency. As stated in Eq. (2), efficiency thus falls as VOUT decreases. Converter must therefore switch to MP mode for higher loads. Efficiency drops below nlin for loads below 30nW due to control losses. The same behavior is observed in MP mode with peak efficiency around 100µW. Fig. 3 and 5 show the benefits of using the output voltage to supply the ring oscillators in ULP mode. With a fixed external clock, MP mode fails to follow VREF above 420mV whereas ULP mode can go up to 450mV. Indeed as VOUT increases, the frequency of the ring oscillator increases too, thereby allowing charges to be transferred to the output more often as shown in Eq. (1). Similarly when VOUT decreases, more charges are transferred to the output for each switching. Therefore, few switchings are needed and the automatic clock frequency
Metric Technology Area Input voltage [V] Output voltage [V] Load range
Table I - Comparison with recent SC DC-DC converters. This work [5] [2] [9] 130nm 180nm 65nm 130nm 0.13 mm² 0.57mm² 0.12mm² 0.26mm² 1-1.2 1.8 1.2 2.5 - 3.6
Peak efficiency Efficiency at 100nW
0.3 - 0.4
0.3 - 1.1
0.3 - 1.1
0.44
10nW-125µW
5µW1mW 74% @50µW NA
1µW-0.5mW
2nW250nW 56% @13µW 44%
74% @100µW 74% @500nW 60%
78% @50µW NA (56% @ 500nW)
scaling reduces losses in control circuitry. Fig. 6 shows the efficiency variations with the input voltage. As given by Eq. (2), it decreases as the input voltage increases, following the theoretical efficiency limit. Table I compares the converter performances with state-ofthe-art switched-capacitors converters. In [2] and [5], the converter is designed to supply a dynamic voltage scaled (DVS) processor. They use a reconfigurable array of capacitors, in order to be able to create a large range of output voltage. They also use PFM and varying switch size to reduce losses of the converter. In [9], an SC converter and an LDO regulator are used together to address low-power loads requirements. The table shows that for medium loads of tenths of µWs the proposed converter has a similar efficiency to recent works whereas for ultra-low loads a significant improvement is obtained. A corner analysis was also performed to further validate the robustness of the proposed circuit. Simulations show that the worst-case corner for functionality is with small capacitors at low temperature with slow devices, which limits subthreshold current [10]. Small capacitors reduce the CT in Eq. (1) and therefore limit the charges that can be transmitted to the load at each cycle. The other corners reduce the ON current of the switches. The devices have more difficulties to transfer charges from the input to CT or from CT to the load within the time they are turned ON. This reduces also the power that can be transferred to the load. Fig. 7 shows the maximal output voltage that can be delivered by the converter for increasing loads. Worst-case corners are shown and compared to typical conditions. In ULP mode, the clock generator and level shifter block fails at extremely low temperature for loads higher than 250nW because the output voltage becomes too low. Indeed under these conditions the generated clock frequency is lower, thereby limiting the output power as stated in Eq. (1) and reducing the maximal output voltage. V.
CONCLUSION
This paper presents a dual-mode switched-capacitor DC-DC converter for supplying subthreshold processors. The converter is implemented and simulated in a commercial 0.13µm CMOS technology. It transfers charges from a 1V1.2V DC input to a 0.3-0.4V DC output. The medium-power (MP) mode corresponds to the processor active mode with up to 125 µW load and the ULP (Ultra-Low-Power) mode fits processor sleep mode up to 500nW. In MP mode, efficiency
Fig. 7. Maximal VOUT for increasing output power in (a) MP and (b) ULP mode. ULP mode fails at low temperature for loads bigger than 250nW.
reaches 74% for 100µW loads which is close to state-of-theart switched capacitor converters. Thanks to adaptive body biasing and adaptive internal clock generation supplied by the output voltage, the efficiency in ULP mode reaches 74% for 500nW loads and remains above 60% for loads as low as 100nW. ACKNOWLEDGMENT J. De Vos and D. Bol are with Université catholique de Louvain as research fellow and postdoctoral researcher, respectively, from the National Foundation for Scientific Research (FNRS) of Belgium. REFERENCES [1]
M. Belleville et al, “Energy Autonomous Sensor Systems: State and Perspectives of a Ubiquitous Sensor Technology,” in Advances in sensors and interfaces IWASI, 2009, pp. 134-138. [2] J. Kwong et al, “A 65 nm sub Vt Microcontroller with Integrated SRAM and Switched Capacitor DC-DC Converter”, in Journal of solid state circuits, vol.44, no.1, Jan. 2009, pp. 115-126. [3] G. Chen et al, “Millimeter-scale Nearly Perpetual Sensor System with Stacked Battery and Solar Cells”, in Int. Solid State Circuits Conf. ISSCC, 2010, pp. 288-289. [4] D. Bol et al, “ Robustness-Aware Sleep Transistor Engineering for Power-Gated Nanometer Sub threshold Circuits”, International Symposium on Circuits and Systems ISCAS, 2010, pp. 1484-1487. [5] Y. Ramadass abd A. Chandrakasan, “Voltage scalable switched capacitor DC-DC converter for ultra-low-power on-chip applications” in Power Electronics Specialists Conference PESC, 2007, pp. 2353-2359. [6] MSP430™16-bit Ultra-Low Power MCUs datasheet, Texas Instrument, available at www.ti.com, 2005. [7] O. A-T. Hasib, “Fully Integrated Ultra-Low-Power Asynchronously Driven Step-Down DC-DC Converter”, in Int. Symp. On Circuits and System ISCAS, 2010, pp. 877-880. [8] M. S. Makowski and D.Maksimovic,” Performance limits of switchedcapacitor DC-DC converters”, in Power Electronics Specialist Conference PESC, 1995, pp. 1215-1221, vol. 2. [9] M. Wieckowski et al, “A Hybrid DC-DC Converter for Sub-Microwatt Sub 1-V Implantable Applications”, in Symposium. on VLSI circuits , 2009, pp. 166-167. [10] D. Bol et al, “The Detrimental Impact of Negative Celsius Temperature on Ultra-Low-Voltage CMOS Logic”, European Solid-State CIRcuits Conference ESSCIRC, 2010, (accepted paper to be published).
