Dynamic power efficiency improvement for PWM class-D amplifier
LETTER
IEICE Electronics Express, Vol.10, No.6, 1–6
Dynamic power efficiency improvement for PWM class-D amplifier Chun Wei Lin1a) and Bing Shiun Hsieh2 1
Department of Electronic Engineering, National Yunlin University of Science & Technology, 123 University Road, Douliou, Yunlin 64002, Taiwan, R. O. C. 2 Graduate School of Engineering Science and Technology, National Yunlin University of Science & Technology, 123 University Road, Douliou, Yunlin 64002, Taiwan, R. O. C. a) [email protected]
Abstract: This paper presents the technique to dynamically enhance the power efficiency of PWM class-D amplifier over a wide range of modulation indexes. The power stage of amplifier is segmented into several small stages and selectively enabled according to the power demand (i.e. modulation indexes). The capability of power delivery is dynamically adjusted to minimize the power loss in case of different modulation indexes improving the power efficiency, especially for small modulation index. The simulation results show that the amplifier remains high power efficiency over a wide range of modulation indexes. The maximum improvement on power efficiency is over 27% for the case of small modulation index. Moreover, for the region of power efficiency greater than 80%, the improvement is 13.5% than that of conventional design. Keywords: power efficiency, PWM class-D amplifier, modulation index, power loss Classification: Integrated circuits References [1] M. A. Rojas-Gonzalez and E. Sanchez-Sinencio, “Low-power high-efficiency class D audio power amplifiers,” IEEE J SolidState Circuits, vol. 44, no. 12, pp. 3272–3284, Dec. 2009. [2] J. S. Chang, M. T. Tan, Z. Cheng, and Y. C. Tong, “Analysis and design of power efficient class D amplifier output stages,” IEEE Trans Circuits Syst I Reg Papers, vol. 47, no. 6, pp. 897–902, June 2000. [3] L. Dooper and M. Berkhout, “A 3.4 W digital-in class-D audio amplifier in 0.14 m CMOS,” IEEE J SolidState Circuits, vol. 47, no. 7, pp. 1524–1534, July 2012. [4] C. W. Lin, B. S. Hsieh, and Y. C. Lin, “Enhanced design of filterless class-D audio amplifier,” Proc IEEE Design Automation and Test in Europe, pp. 1397–1402, 2009.
© IEICE 2013
DOI: 10.1587/elex.10.20130073 Received January 29, 2013 Accepted March 05, 2013 Published March 26, 2013
1
IEICE Electronics Express, Vol.10, No.6, 1–6
1 Introduction High-efficiency class-D amplifier has become an attractive solution for audio driver in applications with tight power consumption and low-voltage requirements [1]. In compare with class-A/AB amplifier, class-D amplifier features very high power efficiency (i.e. >80%) over a large operation region. However, the power efficiency of amplifier is rapidly reduced when output power is less than 30% of maximum power because the power transistors design is usually optimized for the case of maximum power delivery. Therefore, prior research work suggested that the size of power transistors should be optimized by considering a range of power demand (i.e. modulation index) instead of only maximum modulation index and the chip layout should be realized as waffle structure instead of finger structure [2]. In contrast to optimize the sizes of power transistors, the power efficiency could also be improved by optimizing the control process of power stage for power delivery. By segmenting and properly controlling the power transistors and their gate drivers, parts of them are sufficient to provide the power demand of light loading which gives a substantial reduction in quiescent current and dynamic power loss [3]. The critical factor is how to improve power efficiency within the region of small modulation index without sacrificing the capability of power delivery for large modulation index. For this purpose, we develop a method to dynamically enhance power efficiency over a wide range of modulation indexes.
2 The power loss in the PWM class-D amplifier Fig. 1(a) shows the fundamental PWM class-D amplifier which consists of PWM modulator, gate drivers, full-bridge power stages and LC filter. The power consumption of power transistors and gate drivers usually dominates total power loss Ploss composed of static power loss Ps and dynamic power
© IEICE 2013
DOI: 10.1587/elex.10.20130073 Received January 29, 2013 Accepted March 05, 2013 Published March 26, 2013
Fig. 1. (a) Block diagram of PWM class-D amplifier, (b) Dynamic/static power losses versus modulation index, (c) Power efficiency versus modulation index. 2
IEICE Electronics Express, Vol.10, No.6, 1–6
loss Pd . The static power loss is also called the “conduction loss” and its value is depended on the on-resistance ron of power transistors and modulation index D (i.e. the ratio between amplitude of input signal and carrier signal). The dynamic power losses are originated from switching losses on capacitive load Csw and short-circuit current Isc of power transistor and gate driver during the transition. To minimize this shortcircuit current, the driving capability of gate driver should be carefully designed. Once the sizes of power transistors are determined, the switching loss on capacitive load could be further estimated. Therefore, the power efficiency can be estimated by following equation: ð%Þ ¼
Pout Pout Pout ¼ ¼ Pout þ Ploss Pout þ ½Pd þ Ps Pout þ ½ðPsc þ Psw Þ þ Pon
(1)
, where Psc , Psw and Pon denote power loss of short-circuit current, switching loss on capacitive load and conduction loss respectively. The static power loss dominates the total power loss in general when modulation index is more than 0.3 and could be reduced by enhancing the driving capability (i.e. larger transistor size). However, the parasitic capacitance of larger power transistors would enlarge the dynamic power loss that may be the prime loss in case of small modulation index. Therefore, the driving capability of power transistors should be compromised to power loss in practice and optimized to fit the power efficiency for a wide range of power demand. For instance, Fig. 1(b)(c) shows the power losses and power efficiency with respect to modulation indexes individually optimized for three single modulation index, D ¼ 0:1, D ¼ 0:3 and D ¼ 0:9 [2]. The case D ¼ 0:9, is the general design case featuring higher power efficiency in the region of large modulation index because of lower on-resistance and static power loss. However, compared to the case of D ¼ 0:3 or D ¼ 0:1, it also increases the capacitive load and dynamic power loss which reduces power efficiency rapidly in the region of small modulation index. For this reason, in case of different modulation indexes, the gate drivers and power transistors should be dynamically adjusted to make less dynamic and static power loss. In other words, the higher maximum-flatten response of power efficiency leads to least average power loss.
3 The proposed method
© IEICE 2013
DOI: 10.1587/elex.10.20130073 Received January 29, 2013 Accepted March 05, 2013 Published March 26, 2013
The proposed method consists of a multilevel generator, segmented power stages and gate drivers as shown in Fig. 2(a). The input signal is processed by PWM modulator as usual and then the modulated signal is fed into segmented gate drivers and multilevel generator simultaneously. The multilevel generator translates this modulated signal into digital binary codes representing duty ratio of modulated signal and power demand of input signal. In order to obtain maximum-flatten response of power efficiency, the capability of power delivery should be dynamically adjusted according to the power demand. The output signal of multilevel generator is hence used to selectively enable part of the segmented gate drivers and power stages that are in need of conduction. The multilevel generator basically is a time-to-digital converter consisting of a set of delay cell and an adder as shown in Fig. 2(b) [4]. The delay cell is a series of D flip-flop and each flip-flop provides 3
IEICE Electronics Express, Vol.10, No.6, 1–6
Fig. 2. (a) The proposed scheme, (b) The multilevel generator, (c) The segmented power stages and gate drivers. propagation delay T . The modulated PWM signal f ðtÞ is fed into delay cell and propagated to be f ðt k T Þ consequently. If the number of Dflip-flop is M and carrier period of modulation is Ts , the delayed pulse signal of PWM can be further expressed as f ðt k Ts =M Þ. That is, the time slot of one period Ts is divided into M time slots and the PWM signal is arranged into each time slot. The adder then summarizes the value of signals in each time slot and results in a summation: M X Ts f tk mulðtÞ ¼ (2) M k¼1 Because the output signal of multilevel generator varies with the delayed pulse signal of PWM immediately, we have to describe the relationship between them by a macro point of view taking its average value. The average value of output signal of multilevel generator within one period is then expressed as: Z Ts Z Ts X M 1 1 Ts dt mulðtÞdt ¼ f tk mulðtÞavg ¼ Ts 0 Ts 0 k¼1 M (3) M 1 X tn ¼ A tn ¼ ðA M Þ Ts Ts k¼1
© IEICE 2013
DOI: 10.1587/elex.10.20130073 Received January 29, 2013 Accepted March 05, 2013 Published March 26, 2013
, where A and tn denote to amplitude and pulse width of PWM signal. According to Eq. (3), the average value of multilevel generator is proportional to the duty ratio (i.e. tn =Ts ) of PWM signal representing the power demand linearly in digital codes. Thus, we can adjust the power delivery directly by using the multilevel generator to enable the required segmented drivers and power stages. Fig. 2(c) shows the segmented gate drivers and full-bridge power stages which consists of pull-up stages (i.e. Up-PMOS/NMOS) and pull-down 4
IEICE Electronics Express, Vol.10, No.6, 1–6
stages (i.e. Dn-PMOS/NMOS). From the multilevel generator, the M-state binary codes are converted into thermometer codes by the decoder yielding M control states. Therefore, except zero-state, we need (M12 pull-down stages and (M12 pull-up stages to produce totally M states. In addition, M should be odd number so that the output states of full-bridge power stages can be symmetric to zero-state. The control states of full-bridge power stages can be further reduced because the conduction states of pullup and pull-down are complementary that the required conduction currents are equal and just in opposite direction. Moreover, due to the output signal of multilevel generator varies with delayed pulse signal of PWM immediately, the output signal of multilevel generator often jumps between adjacent codes that may change too fast for controlling power stages. We hence lump those adjacent codes together to simply this problem by following rules: If 1 mulðtÞ ðM þ1Þ=2, mul0 ¼ i
for mulðtÞ varies between i and iþ1
If ðM þ1Þ=2 mulðtÞ M, mul0 ¼ iþ1 for mulðtÞ varies between i and iþ1 For example, M13 and mult varies between 12 and 13, means large duty ratio of PWM signal and great power demand from input signal. The 6 segmented gate drivers and full-bridge power stages are all on duty in this situation. On the contrary, mult varies between 7 and 8, means smaller power demand that requires few segmented gate driver and full-bridge power stage. Through applying proposed method, the segmented gate drivers and power stages are selectively enabled on demand that gives substantial reduction in dynamic power loss. The power efficiency is indeed improved over a wide range of modulation indexes, especially for small modulation index.
4 Simulation results
© IEICE 2013
DOI: 10.1587/elex.10.20130073 Received January 29, 2013 Accepted March 05, 2013 Published March 26, 2013
In this section, to demonstrate the improvement on power efficiency, we used TSMC 5V-0.35-um CMOS technology to implement three cases of PWM class-D amplifiers including (I) applying proposed method, (II) conventional optimization for maximum power delivery D ¼ 0:9 and (III) optimization for a range of modulation index D ¼ 0:1 0:9 [2]. All of three amplifiers were with two-level PWM and full-bridge power stage. In addition, the used low-pass filter and speaker were with inductance Lo ¼ 45 H, capacitance Co ¼ 1:5 F and resistance RL ¼ 8 . For the proposed method, we segmented the power stages and gate drivers of amplifier into 6 sub-stages as shown in Fig. 2(c) and each of them were optimized to corresponding modulation indexes uniformly within the region of D ¼ 0:1 0:9. Consequently, we inserted the multilevel generator to enable the conduction of segmented power stages according to its states which represent to different power demand. Fig. 3(a) shows the total-harmonic-distortion (THD) of class-D amplifiers with proposed method and conventional optimization of D ¼ 0:9 respectively. Because the power stage of class-D amplifier has non-zero on-resistance in practice, the on-resistance of the power stage slightly varies with different modulation indexes and results in a few THD losses. By applying widely used 1st-order integrator to perform feedback 5
IEICE Electronics Express, Vol.10, No.6, 1–6
Fig. 3. (a) The comparison of THD versus output power, (b) The comparison of power efficiency versus modulation index. compensation which often seen in recent research works, this THD loss can be removed and Fig. 3(a) shows that THD loss is almost negligible. Fig. 3(b) shows the power efficiency of three class-D amplifiers. It can be seen that at most 27% and 13% improvement on power efficiency in comparison with the other two designs when modulation index is below 30% of the maximum modulation index. Moreover, for the region of power efficiency greater than 80%, the region of modulation index is expanded from (0.26～1) to (0.16～1) that almost 13.5% improved than that of case II. This is because only parts of the power stages and gate drivers are enabled to drive speaker when the power demand is small that greatly reduces the dynamic power loss and quiescent current. In contrast to low power demand, within the region of large modulation index, all power stages are enabled and feature a lower on-resistance. The power stages hence minimize the static power loss and achieve very high power efficiency.
5 Conclusions
© IEICE 2013
DOI: 10.1587/elex.10.20130073 Received January 29, 2013 Accepted March 05, 2013 Published March 26, 2013
The dynamic power efficiency improvement technique has been presented to reduce the power loss of PWM class-D amplifier in the region of small power demand and keep high power efficiency over a wide range of modulation indexes. The proposed method dynamically adjusts the capability of power delivery according to the power demand; indeed, the amplifier has higher maximum-flatten response of power efficiency. The simulation results of proposed method show that over 27% improvement of power efficiency for small modulation index and the range of modulation index has 13.5% expansion for the region of high power efficiency. 6
IEICE Electronics Express, Vol.10, No.6, 1–6
Dynamic power efficiency improvement for PWM class-D amplifier Chun Wei Lin1a) and Bing Shiun Hsieh2 1
Department of Electronic Engineering, National Yunlin University of Science & Technology, 123 University Road, Douliou, Yunlin 64002, Taiwan, R. O. C. 2 Graduate School of Engineering Science and Technology, National Yunlin University of Science & Technology, 123 University Road, Douliou, Yunlin 64002, Taiwan, R. O. C. a) [email protected]
Abstract: This paper presents the technique to dynamically enhance the power efficiency of PWM class-D amplifier over a wide range of modulation indexes. The power stage of amplifier is segmented into several small stages and selectively enabled according to the power demand (i.e. modulation indexes). The capability of power delivery is dynamically adjusted to minimize the power loss in case of different modulation indexes improving the power efficiency, especially for small modulation index. The simulation results show that the amplifier remains high power efficiency over a wide range of modulation indexes. The maximum improvement on power efficiency is over 27% for the case of small modulation index. Moreover, for the region of power efficiency greater than 80%, the improvement is 13.5% than that of conventional design. Keywords: power efficiency, PWM class-D amplifier, modulation index, power loss Classification: Integrated circuits References [1] M. A. Rojas-Gonzalez and E. Sanchez-Sinencio, “Low-power high-efficiency class D audio power amplifiers,” IEEE J SolidState Circuits, vol. 44, no. 12, pp. 3272–3284, Dec. 2009. [2] J. S. Chang, M. T. Tan, Z. Cheng, and Y. C. Tong, “Analysis and design of power efficient class D amplifier output stages,” IEEE Trans Circuits Syst I Reg Papers, vol. 47, no. 6, pp. 897–902, June 2000. [3] L. Dooper and M. Berkhout, “A 3.4 W digital-in class-D audio amplifier in 0.14 m CMOS,” IEEE J SolidState Circuits, vol. 47, no. 7, pp. 1524–1534, July 2012. [4] C. W. Lin, B. S. Hsieh, and Y. C. Lin, “Enhanced design of filterless class-D audio amplifier,” Proc IEEE Design Automation and Test in Europe, pp. 1397–1402, 2009.
© IEICE 2013
DOI: 10.1587/elex.10.20130073 Received January 29, 2013 Accepted March 05, 2013 Published March 26, 2013
1
IEICE Electronics Express, Vol.10, No.6, 1–6
1 Introduction High-efficiency class-D amplifier has become an attractive solution for audio driver in applications with tight power consumption and low-voltage requirements [1]. In compare with class-A/AB amplifier, class-D amplifier features very high power efficiency (i.e. >80%) over a large operation region. However, the power efficiency of amplifier is rapidly reduced when output power is less than 30% of maximum power because the power transistors design is usually optimized for the case of maximum power delivery. Therefore, prior research work suggested that the size of power transistors should be optimized by considering a range of power demand (i.e. modulation index) instead of only maximum modulation index and the chip layout should be realized as waffle structure instead of finger structure [2]. In contrast to optimize the sizes of power transistors, the power efficiency could also be improved by optimizing the control process of power stage for power delivery. By segmenting and properly controlling the power transistors and their gate drivers, parts of them are sufficient to provide the power demand of light loading which gives a substantial reduction in quiescent current and dynamic power loss [3]. The critical factor is how to improve power efficiency within the region of small modulation index without sacrificing the capability of power delivery for large modulation index. For this purpose, we develop a method to dynamically enhance power efficiency over a wide range of modulation indexes.
2 The power loss in the PWM class-D amplifier Fig. 1(a) shows the fundamental PWM class-D amplifier which consists of PWM modulator, gate drivers, full-bridge power stages and LC filter. The power consumption of power transistors and gate drivers usually dominates total power loss Ploss composed of static power loss Ps and dynamic power
© IEICE 2013
DOI: 10.1587/elex.10.20130073 Received January 29, 2013 Accepted March 05, 2013 Published March 26, 2013
Fig. 1. (a) Block diagram of PWM class-D amplifier, (b) Dynamic/static power losses versus modulation index, (c) Power efficiency versus modulation index. 2
IEICE Electronics Express, Vol.10, No.6, 1–6
loss Pd . The static power loss is also called the “conduction loss” and its value is depended on the on-resistance ron of power transistors and modulation index D (i.e. the ratio between amplitude of input signal and carrier signal). The dynamic power losses are originated from switching losses on capacitive load Csw and short-circuit current Isc of power transistor and gate driver during the transition. To minimize this shortcircuit current, the driving capability of gate driver should be carefully designed. Once the sizes of power transistors are determined, the switching loss on capacitive load could be further estimated. Therefore, the power efficiency can be estimated by following equation: ð%Þ ¼
Pout Pout Pout ¼ ¼ Pout þ Ploss Pout þ ½Pd þ Ps Pout þ ½ðPsc þ Psw Þ þ Pon
(1)
, where Psc , Psw and Pon denote power loss of short-circuit current, switching loss on capacitive load and conduction loss respectively. The static power loss dominates the total power loss in general when modulation index is more than 0.3 and could be reduced by enhancing the driving capability (i.e. larger transistor size). However, the parasitic capacitance of larger power transistors would enlarge the dynamic power loss that may be the prime loss in case of small modulation index. Therefore, the driving capability of power transistors should be compromised to power loss in practice and optimized to fit the power efficiency for a wide range of power demand. For instance, Fig. 1(b)(c) shows the power losses and power efficiency with respect to modulation indexes individually optimized for three single modulation index, D ¼ 0:1, D ¼ 0:3 and D ¼ 0:9 [2]. The case D ¼ 0:9, is the general design case featuring higher power efficiency in the region of large modulation index because of lower on-resistance and static power loss. However, compared to the case of D ¼ 0:3 or D ¼ 0:1, it also increases the capacitive load and dynamic power loss which reduces power efficiency rapidly in the region of small modulation index. For this reason, in case of different modulation indexes, the gate drivers and power transistors should be dynamically adjusted to make less dynamic and static power loss. In other words, the higher maximum-flatten response of power efficiency leads to least average power loss.
3 The proposed method
© IEICE 2013
DOI: 10.1587/elex.10.20130073 Received January 29, 2013 Accepted March 05, 2013 Published March 26, 2013
The proposed method consists of a multilevel generator, segmented power stages and gate drivers as shown in Fig. 2(a). The input signal is processed by PWM modulator as usual and then the modulated signal is fed into segmented gate drivers and multilevel generator simultaneously. The multilevel generator translates this modulated signal into digital binary codes representing duty ratio of modulated signal and power demand of input signal. In order to obtain maximum-flatten response of power efficiency, the capability of power delivery should be dynamically adjusted according to the power demand. The output signal of multilevel generator is hence used to selectively enable part of the segmented gate drivers and power stages that are in need of conduction. The multilevel generator basically is a time-to-digital converter consisting of a set of delay cell and an adder as shown in Fig. 2(b) [4]. The delay cell is a series of D flip-flop and each flip-flop provides 3
IEICE Electronics Express, Vol.10, No.6, 1–6
Fig. 2. (a) The proposed scheme, (b) The multilevel generator, (c) The segmented power stages and gate drivers. propagation delay T . The modulated PWM signal f ðtÞ is fed into delay cell and propagated to be f ðt k T Þ consequently. If the number of Dflip-flop is M and carrier period of modulation is Ts , the delayed pulse signal of PWM can be further expressed as f ðt k Ts =M Þ. That is, the time slot of one period Ts is divided into M time slots and the PWM signal is arranged into each time slot. The adder then summarizes the value of signals in each time slot and results in a summation: M X Ts f tk mulðtÞ ¼ (2) M k¼1 Because the output signal of multilevel generator varies with the delayed pulse signal of PWM immediately, we have to describe the relationship between them by a macro point of view taking its average value. The average value of output signal of multilevel generator within one period is then expressed as: Z Ts Z Ts X M 1 1 Ts dt mulðtÞdt ¼ f tk mulðtÞavg ¼ Ts 0 Ts 0 k¼1 M (3) M 1 X tn ¼ A tn ¼ ðA M Þ Ts Ts k¼1
© IEICE 2013
DOI: 10.1587/elex.10.20130073 Received January 29, 2013 Accepted March 05, 2013 Published March 26, 2013
, where A and tn denote to amplitude and pulse width of PWM signal. According to Eq. (3), the average value of multilevel generator is proportional to the duty ratio (i.e. tn =Ts ) of PWM signal representing the power demand linearly in digital codes. Thus, we can adjust the power delivery directly by using the multilevel generator to enable the required segmented drivers and power stages. Fig. 2(c) shows the segmented gate drivers and full-bridge power stages which consists of pull-up stages (i.e. Up-PMOS/NMOS) and pull-down 4
IEICE Electronics Express, Vol.10, No.6, 1–6
stages (i.e. Dn-PMOS/NMOS). From the multilevel generator, the M-state binary codes are converted into thermometer codes by the decoder yielding M control states. Therefore, except zero-state, we need (M12 pull-down stages and (M12 pull-up stages to produce totally M states. In addition, M should be odd number so that the output states of full-bridge power stages can be symmetric to zero-state. The control states of full-bridge power stages can be further reduced because the conduction states of pullup and pull-down are complementary that the required conduction currents are equal and just in opposite direction. Moreover, due to the output signal of multilevel generator varies with delayed pulse signal of PWM immediately, the output signal of multilevel generator often jumps between adjacent codes that may change too fast for controlling power stages. We hence lump those adjacent codes together to simply this problem by following rules: If 1 mulðtÞ ðM þ1Þ=2, mul0 ¼ i
for mulðtÞ varies between i and iþ1
If ðM þ1Þ=2 mulðtÞ M, mul0 ¼ iþ1 for mulðtÞ varies between i and iþ1 For example, M13 and mult varies between 12 and 13, means large duty ratio of PWM signal and great power demand from input signal. The 6 segmented gate drivers and full-bridge power stages are all on duty in this situation. On the contrary, mult varies between 7 and 8, means smaller power demand that requires few segmented gate driver and full-bridge power stage. Through applying proposed method, the segmented gate drivers and power stages are selectively enabled on demand that gives substantial reduction in dynamic power loss. The power efficiency is indeed improved over a wide range of modulation indexes, especially for small modulation index.
4 Simulation results
© IEICE 2013
DOI: 10.1587/elex.10.20130073 Received January 29, 2013 Accepted March 05, 2013 Published March 26, 2013
In this section, to demonstrate the improvement on power efficiency, we used TSMC 5V-0.35-um CMOS technology to implement three cases of PWM class-D amplifiers including (I) applying proposed method, (II) conventional optimization for maximum power delivery D ¼ 0:9 and (III) optimization for a range of modulation index D ¼ 0:1 0:9 [2]. All of three amplifiers were with two-level PWM and full-bridge power stage. In addition, the used low-pass filter and speaker were with inductance Lo ¼ 45 H, capacitance Co ¼ 1:5 F and resistance RL ¼ 8 . For the proposed method, we segmented the power stages and gate drivers of amplifier into 6 sub-stages as shown in Fig. 2(c) and each of them were optimized to corresponding modulation indexes uniformly within the region of D ¼ 0:1 0:9. Consequently, we inserted the multilevel generator to enable the conduction of segmented power stages according to its states which represent to different power demand. Fig. 3(a) shows the total-harmonic-distortion (THD) of class-D amplifiers with proposed method and conventional optimization of D ¼ 0:9 respectively. Because the power stage of class-D amplifier has non-zero on-resistance in practice, the on-resistance of the power stage slightly varies with different modulation indexes and results in a few THD losses. By applying widely used 1st-order integrator to perform feedback 5
IEICE Electronics Express, Vol.10, No.6, 1–6
Fig. 3. (a) The comparison of THD versus output power, (b) The comparison of power efficiency versus modulation index. compensation which often seen in recent research works, this THD loss can be removed and Fig. 3(a) shows that THD loss is almost negligible. Fig. 3(b) shows the power efficiency of three class-D amplifiers. It can be seen that at most 27% and 13% improvement on power efficiency in comparison with the other two designs when modulation index is below 30% of the maximum modulation index. Moreover, for the region of power efficiency greater than 80%, the region of modulation index is expanded from (0.26～1) to (0.16～1) that almost 13.5% improved than that of case II. This is because only parts of the power stages and gate drivers are enabled to drive speaker when the power demand is small that greatly reduces the dynamic power loss and quiescent current. In contrast to low power demand, within the region of large modulation index, all power stages are enabled and feature a lower on-resistance. The power stages hence minimize the static power loss and achieve very high power efficiency.
5 Conclusions
© IEICE 2013
DOI: 10.1587/elex.10.20130073 Received January 29, 2013 Accepted March 05, 2013 Published March 26, 2013
The dynamic power efficiency improvement technique has been presented to reduce the power loss of PWM class-D amplifier in the region of small power demand and keep high power efficiency over a wide range of modulation indexes. The proposed method dynamically adjusts the capability of power delivery according to the power demand; indeed, the amplifier has higher maximum-flatten response of power efficiency. The simulation results of proposed method show that over 27% improvement of power efficiency for small modulation index and the range of modulation index has 13.5% expansion for the region of high power efficiency. 6
