Effective on-chip inductance modeling for multiple ... - People @EECS
Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion Yu Cao, Xuejue Huang, Norman Chang', Shen Lin', 0. Sam Nakagawa', Weize Xie', and Chenming Hu EECS Department, University of California, at Berkeley, Berkeley, CA 94720, USA 'Hewlett-Packard Laboratories, Palo Alto, CA 94303, USA Email: [email protected] With increasing chip size and the number of data bits, many long global lines run in parallel in the same layer. Besides metal-to-ground capacitance (C,) and selfinductance (L.q),coupling capacitance (C,) and mutual inductance (L,) are also important for correct delay and noise estimation. In the RC line model, the orthogonal layer can approximately be treated as a ground plane for capacitance coupling simulation [7]. Since C , drops quickly with increasing spacing, the nearest neighboring lines (first neighbors) will see the most of the charge excited by the aggressor. Other farther neighboring lines (second and the higher order neighbors) contribute minimally to capacitance coupling. In this sense, capacitance coupling is a 'short range' effect, and we only need to include the first neighbors into delay and noise calculation. Fig. l a shows the dominant 'charge sharing' path for capacitance coupling (C,+ C,). The 1'' neighbors shield most of the capacitance coupling from higher order neighbors.
Abstract A new approach to handle the inductance effect on multiple signal lines is presented. The worst case switching pattern is first identijied. Then a numerical approach is used to model the effective loop inductance (Leg)for multiple lines. Based on look-up table for Leg, an equivalent single line model can be generated to decouple a specific signal line from the others to per$orm static timing analysis. Compared to the use of f i l l RLC netlist for multiple lines, this approach greatly improves the computation eficiency and maintains accuracy for timing and signal integrity analysis. Applications to repeater insertion in the critical path chains are demonstrated. For a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, w e j n d that same number of repeaters is inserted for optimal delay according to both the RC and RLC multiple line models.
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1. Introduction As VLSI design enters Deep-Sub-Micron (DSM) era, scaled feature sizes, an increased number of metal layers, and larger chip dimensions have helped to achieve faster, more complex, and more powerful design 113. Chip operation frequency nowadays is pushed into Gigahertz region with much shorter signal rise time. To accommodate this technology trend, designers must be more careful in handling interconnect delay and cross-talk noise, especially in critical path timing analysis, to reach higher clock frequency. In design automation, interconnect is usually modeled as a resistance-capacitance netlist for timing and noise prediction [2-41, because line inductance is negligible under low clock frequency. When the clock frequency approaches one Gigahertz, the impedance contributed by line inductance (wL)will be comparable to the line resistance [5-61. The inclusion of inductance not only slows down the signal delay, but also causes voltage overshoot and reduces rise time, which can introduce large crosstalk noise on neighboring lines [7j.
0-7695-1025-6/01$10.00 0 2001 IEEE
b. Three major paths for inductive current return: (1) +cc; (2) exx;(3) +C,ec&,.
Figure 1. Short range capacitance coupling vs. long range inductance coupling.
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In contrast to the RC case, inductance coupling excites an induced current that needs to find a return path to form the current loop. Unfortunately, with the receiver’s gate capacitance (C,.,,,,,,,) loaded at the end of wire, there is no DC path for the return current directly back to the ground. The orthogonal layer cannot be the ground plane anymore because L, is zero for two perpendicular lines. The retum current must go through C,, C,, or Crecrever of the co-planar signal lines until it goes back to AC ground or hits the power and ground lines, which can shield further coupling, as shown in Fig. 1b. Because the loop impedances of each of these paths are comparable, there is no dominant route for inductive current return. Furthermore, all higher neighbors should be taken into consideration because the mutual inductance Lm decays slowly with increasing spacing [8-91. Therefore, inductance coupling is a ‘long range’ issue and the full inductance matrix is necessary for a correct RLC model representation [lo]. Because of the long range coupling characteristics of inductance coupling, accurate estimation of delay and noise for RLC lines is usually a time consuming task. For example, if there are N signal lines, we must include NC,, (N+l)C,, and a (N+2)x(N+2) partial inductance (L,Tand Lm) matrix into simulation for correct results. For this reason, a full partial inductance representation is physically accurate but computationally costly. Particularly in determining the operating frequency of a chip, current EDA tools usually check a specific single line chain on critical path and examine the worst-case delay for repeater insertion and timing optimization. Since the operating frequency affects the entire chip and must be checked globally, use of a full netlist would be very computationally intensive. For this purpose, it would be preferable to develop an algorithm to reduce the multiple line condition to a single line model. This equivalent single line model should be able to take the neighboring line effects into account for delay estimation while greatly improving efficiency. In the conventional RC line model, due to short-range capacitance coupling, this simplification is realized by introducing a switch factor to effectively model first order coupling capacitances. The specific line can then be decoupled from the others by using an effective capacitance Ce~(C,+2qC,),as shown in Fig. 2a. Depending on the switching pattern, q is between ( 0 , 2) for a step input or {-1, 3 ) for a ramp input [ll]. However, for the RLC line model, all neighboring lines between the same powerlground lines should be included, thus increasing the decoupling complexity. In the following sections, we will first introduce the effective loop inductance (Le8) concept to simplify the multiple RLC line problem into a single RL,f&,ff model as shown in Fig. 2b, and then explain a practical approach to model 15, which can handle the extra delay and noise caused by inductance. Applications to repeater insertion and critical path delay optimization will also be discussed.
a. Decoupling in RC line model
c, f
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L=//=LCdw.I,
S,
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~drnt,,
we,,,,,, tn,J
b. Decoupling in RLC line model
Figure 2. Simplification of multiple lines into single line improves simulation efficiency.
2. Effective Loop Inductance Modeling 2.1. Effective Loop Inductance Lefl Partial inductances L, and L, can accurately model the RLC line behavior, but they involve too many elements for simulation. With the knowledge that the induced current forms a loop and that all the inductance effects can be reflected by the loop RLC elements response, a loop inductance (Ll0,,J can be used to simplify the problem [7]. Using the correct L/7 or segment length> 6”). In the future, we will address an analytical approach for L, to further improve simulation efficiency.
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5. References [ 13 Intemational Technology Roadmap for Semiconductors
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a N = l , w=l.Opm, I=11000pm, wd”vc,=lOOpm,tnrr=80ps
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Number of Repeaters b. N=5, w=2.0pm, s=2.0pm, I=11000pm, ww,.,=lOOpm, r,.=tOps
Figure 10. Optimal number of repeaters: single line case and multiple line case.
4. Summary and Conclusion In this work, we develop an efficient way to handle delay and noise estimation for multiple on-chip global wires. Effective loop inductance, instead of partial inductance, directly determines the electrical characteristics of the coupling interconnect and greatly reduces the number of elements for further modeling and estimation. Thus, accurate Lcflmodeling becomes the main target. T o highlight the inductance effect for timing analysis, our model is focused on the extra delay introduced purely by inclusion of Le? By using the Le# look-up table, we studied the inductance effect on repeater insertion. For a single line, Leflis the self inductance L,. Extra inductance for a single line causes a more linear dependence of a line delay on line length, which has a larger slope than the quadratic de-
(ITRS), 1999. [2] H. B. Bakoglu, “Circuits, Interconnections, and Packaging for VLSI”, Addison-Wesley Pub. Co., 1990. [3] T. Sakurai, “Approximation of Wiring Delay in MOSFET LSI”, IEEE Jour. of Solid-State Circuits, vol. 18, pp. 41 8426, Aug. 1983. [4] S. Nakagawa, D. Sylvester, J. G. McBride, and S. Y. Oh, “On-Chip Cross Talk Noise Model for Deep-Submicrometer ULSl Interconnect”, H P Journal, pp. 39-45, Aug. 1998. [5] A. Deutsch, et al., “When are Transmission-Line Effects Important for On-Chip Interconnects?’, IEEE Trans. on Microwave Theory Tech., vol. 45, pp. 1836-1846, Oct. 1997. [6] A. Deutsch, et al., “The Importance of Inductance and Inductive Coupling for On-Chip Wiring”, Proc. o f l E E E 6-rh Electrical Petformance of Electronic Packaging, pp. 53-56, Oct. 1997. [7] C. K. Cheng, J. Lillis, S. Lin, and N. Chang, “Interconnect Analysis and Synthesis”, John Wiley & Sons, Inc., 1999. [8] Frederick W. Grover, “Inductance Calculations Working Formulas and Tables”, Dover Publications, Inc., 1946. [9] S . Lin, N. Chang, and S . Nakagawa, “Quick On-Chip Selfand Mutual-Inductance Screen”, International Symposium of Quality Electronic Design (ISQED), Mar. 1999. [10]B. Krauter and L. Pilleggi, “Generation Sparse Partial Inductance Matrices with Guaranteed Stability”, Proc. oflEEE ICCAD, pp 45-52, NOV.1995. [11]A. Kahng, S. Muddu, and E. Sarto, “On Switch Factor Based Analysis of Coupled RC Interconnects”, Proc. of DAC, pp. 79-84, Jun, 2000. [12]N. Chang, S. Lin, L. He, S. Nakagawa, and W. Xie, “Clocktree RLC Extraction with Efficient Inductance Modeling”, Prod. of DATE, 2000. [13]L. He, N. Chang, S. Lin, and O.S. Nakagawa, “An Efficient Inductance Modeling for On-Chip Interconnects,” P roc. of CICC, pp. 457-460,1999. [14]Y. Cao, X. Huang, D. Sylvester, N. Chang, and C. Hu, “A New Analytical Model for On-Chip RLC Coupling Interconnect”, to be published at IEDM, Dec. 2000. [15]Y. 1. Ismail, and E. G. Friedman, “Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits’’, Proc. ofDAC, pp. 721-724, Jun. 1!)99. [16]N. Chang, G. Zavagli, K. Rahmat, J. Ku, J. Wanek, and S.Y. Oh, “Signal Net Optimization via Repeater Insertion and Transistor Sizing”, HP Design Tech. Conf., 1997.
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Abstract A new approach to handle the inductance effect on multiple signal lines is presented. The worst case switching pattern is first identijied. Then a numerical approach is used to model the effective loop inductance (Leg)for multiple lines. Based on look-up table for Leg, an equivalent single line model can be generated to decouple a specific signal line from the others to per$orm static timing analysis. Compared to the use of f i l l RLC netlist for multiple lines, this approach greatly improves the computation eficiency and maintains accuracy for timing and signal integrity analysis. Applications to repeater insertion in the critical path chains are demonstrated. For a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, w e j n d that same number of repeaters is inserted for optimal delay according to both the RC and RLC multiple line models.
1'' neighbors
I\
Aggressor
/
1. Introduction As VLSI design enters Deep-Sub-Micron (DSM) era, scaled feature sizes, an increased number of metal layers, and larger chip dimensions have helped to achieve faster, more complex, and more powerful design 113. Chip operation frequency nowadays is pushed into Gigahertz region with much shorter signal rise time. To accommodate this technology trend, designers must be more careful in handling interconnect delay and cross-talk noise, especially in critical path timing analysis, to reach higher clock frequency. In design automation, interconnect is usually modeled as a resistance-capacitance netlist for timing and noise prediction [2-41, because line inductance is negligible under low clock frequency. When the clock frequency approaches one Gigahertz, the impedance contributed by line inductance (wL)will be comparable to the line resistance [5-61. The inclusion of inductance not only slows down the signal delay, but also causes voltage overshoot and reduces rise time, which can introduce large crosstalk noise on neighboring lines [7j.
0-7695-1025-6/01$10.00 0 2001 IEEE
b. Three major paths for inductive current return: (1) +cc; (2) exx;(3) +C,ec&,.
Figure 1. Short range capacitance coupling vs. long range inductance coupling.
185
In contrast to the RC case, inductance coupling excites an induced current that needs to find a return path to form the current loop. Unfortunately, with the receiver’s gate capacitance (C,.,,,,,,,) loaded at the end of wire, there is no DC path for the return current directly back to the ground. The orthogonal layer cannot be the ground plane anymore because L, is zero for two perpendicular lines. The retum current must go through C,, C,, or Crecrever of the co-planar signal lines until it goes back to AC ground or hits the power and ground lines, which can shield further coupling, as shown in Fig. 1b. Because the loop impedances of each of these paths are comparable, there is no dominant route for inductive current return. Furthermore, all higher neighbors should be taken into consideration because the mutual inductance Lm decays slowly with increasing spacing [8-91. Therefore, inductance coupling is a ‘long range’ issue and the full inductance matrix is necessary for a correct RLC model representation [lo]. Because of the long range coupling characteristics of inductance coupling, accurate estimation of delay and noise for RLC lines is usually a time consuming task. For example, if there are N signal lines, we must include NC,, (N+l)C,, and a (N+2)x(N+2) partial inductance (L,Tand Lm) matrix into simulation for correct results. For this reason, a full partial inductance representation is physically accurate but computationally costly. Particularly in determining the operating frequency of a chip, current EDA tools usually check a specific single line chain on critical path and examine the worst-case delay for repeater insertion and timing optimization. Since the operating frequency affects the entire chip and must be checked globally, use of a full netlist would be very computationally intensive. For this purpose, it would be preferable to develop an algorithm to reduce the multiple line condition to a single line model. This equivalent single line model should be able to take the neighboring line effects into account for delay estimation while greatly improving efficiency. In the conventional RC line model, due to short-range capacitance coupling, this simplification is realized by introducing a switch factor to effectively model first order coupling capacitances. The specific line can then be decoupled from the others by using an effective capacitance Ce~(C,+2qC,),as shown in Fig. 2a. Depending on the switching pattern, q is between ( 0 , 2) for a step input or {-1, 3 ) for a ramp input [ll]. However, for the RLC line model, all neighboring lines between the same powerlground lines should be included, thus increasing the decoupling complexity. In the following sections, we will first introduce the effective loop inductance (Le8) concept to simplify the multiple RLC line problem into a single RL,f&,ff model as shown in Fig. 2b, and then explain a practical approach to model 15, which can handle the extra delay and noise caused by inductance. Applications to repeater insertion and critical path delay optimization will also be discussed.
a. Decoupling in RC line model
c, f
5
L,
L=//=LCdw.I,
S,
A!
~drnt,,
we,,,,,, tn,J
b. Decoupling in RLC line model
Figure 2. Simplification of multiple lines into single line improves simulation efficiency.
2. Effective Loop Inductance Modeling 2.1. Effective Loop Inductance Lefl Partial inductances L, and L, can accurately model the RLC line behavior, but they involve too many elements for simulation. With the knowledge that the induced current forms a loop and that all the inductance effects can be reflected by the loop RLC elements response, a loop inductance (Ll0,,J can be used to simplify the problem [7]. Using the correct L/7 or segment length> 6”). In the future, we will address an analytical approach for L, to further improve simulation efficiency.
Y
5. References [ 13 Intemational Technology Roadmap for Semiconductors
0
1
2
3
4
5
6
Number of Repeaters
/
a N = l , w=l.Opm, I=11000pm, wd”vc,=lOOpm,tnrr=80ps
0.40 Opt.#ofrpt: RC: 1; RLC:l;
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Number of Repeaters b. N=5, w=2.0pm, s=2.0pm, I=11000pm, ww,.,=lOOpm, r,.=tOps
Figure 10. Optimal number of repeaters: single line case and multiple line case.
4. Summary and Conclusion In this work, we develop an efficient way to handle delay and noise estimation for multiple on-chip global wires. Effective loop inductance, instead of partial inductance, directly determines the electrical characteristics of the coupling interconnect and greatly reduces the number of elements for further modeling and estimation. Thus, accurate Lcflmodeling becomes the main target. T o highlight the inductance effect for timing analysis, our model is focused on the extra delay introduced purely by inclusion of Le? By using the Le# look-up table, we studied the inductance effect on repeater insertion. For a single line, Leflis the self inductance L,. Extra inductance for a single line causes a more linear dependence of a line delay on line length, which has a larger slope than the quadratic de-
(ITRS), 1999. [2] H. B. Bakoglu, “Circuits, Interconnections, and Packaging for VLSI”, Addison-Wesley Pub. Co., 1990. [3] T. Sakurai, “Approximation of Wiring Delay in MOSFET LSI”, IEEE Jour. of Solid-State Circuits, vol. 18, pp. 41 8426, Aug. 1983. [4] S. Nakagawa, D. Sylvester, J. G. McBride, and S. Y. Oh, “On-Chip Cross Talk Noise Model for Deep-Submicrometer ULSl Interconnect”, H P Journal, pp. 39-45, Aug. 1998. [5] A. Deutsch, et al., “When are Transmission-Line Effects Important for On-Chip Interconnects?’, IEEE Trans. on Microwave Theory Tech., vol. 45, pp. 1836-1846, Oct. 1997. [6] A. Deutsch, et al., “The Importance of Inductance and Inductive Coupling for On-Chip Wiring”, Proc. o f l E E E 6-rh Electrical Petformance of Electronic Packaging, pp. 53-56, Oct. 1997. [7] C. K. Cheng, J. Lillis, S. Lin, and N. Chang, “Interconnect Analysis and Synthesis”, John Wiley & Sons, Inc., 1999. [8] Frederick W. Grover, “Inductance Calculations Working Formulas and Tables”, Dover Publications, Inc., 1946. [9] S . Lin, N. Chang, and S . Nakagawa, “Quick On-Chip Selfand Mutual-Inductance Screen”, International Symposium of Quality Electronic Design (ISQED), Mar. 1999. [10]B. Krauter and L. Pilleggi, “Generation Sparse Partial Inductance Matrices with Guaranteed Stability”, Proc. oflEEE ICCAD, pp 45-52, NOV.1995. [11]A. Kahng, S. Muddu, and E. Sarto, “On Switch Factor Based Analysis of Coupled RC Interconnects”, Proc. of DAC, pp. 79-84, Jun, 2000. [12]N. Chang, S. Lin, L. He, S. Nakagawa, and W. Xie, “Clocktree RLC Extraction with Efficient Inductance Modeling”, Prod. of DATE, 2000. [13]L. He, N. Chang, S. Lin, and O.S. Nakagawa, “An Efficient Inductance Modeling for On-Chip Interconnects,” P roc. of CICC, pp. 457-460,1999. [14]Y. Cao, X. Huang, D. Sylvester, N. Chang, and C. Hu, “A New Analytical Model for On-Chip RLC Coupling Interconnect”, to be published at IEDM, Dec. 2000. [15]Y. 1. Ismail, and E. G. Friedman, “Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits’’, Proc. ofDAC, pp. 721-724, Jun. 1!)99. [16]N. Chang, G. Zavagli, K. Rahmat, J. Ku, J. Wanek, and S.Y. Oh, “Signal Net Optimization via Repeater Insertion and Transistor Sizing”, HP Design Tech. Conf., 1997.
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