Failure Analysis and Test Solutions for Low-Power SRAMs (PDF ...
2011 Asian Test Symposium
Failure Analysis and Test Solutions for Low-Power SRAMs L. B. Zordan1 A. Bosio1 L. Dilillo1 P. Girard1 S. Pravossoudovitch1 A. Todri1 A. Virazel1 N. Badereddine2 1
LIRMM - Université Montpellier II / CNRS 161, rue Ada – 34095 Montpellier Cedex 5, France E-mail: @lirmm.fr
2
Intel Mobile Communications 2600, route des Crêtes – 06560 Sophia-Antipolis, France E-mail: [email protected]
Abstract—Low-power SRAMs embed power gating facilities for reducing power consumption. Power gating is applied using power switches for controlling the supply voltage applied to the memory cells i.e. one or more memory blocks can be disconnected from the power supply during a long time of inactivity, thus reducing the power consumption. In this paper, we provide a detailed analysis on the impact that defective power switches impose on the behavior of SRAM core-cells. Furthermore, we propose efficient test solutions to detect such faulty behaviors.
accurate and reliable operation of the SRAM. Our study analyzes the impact of defective power switches on the behavior of SRAM core-cells. Additionally, we propose efficient test solutions to detect such faulty behaviors. Our test strategy consists in providing realistic fault models and practical test solution with minimal application time [3]. II.
Keywords—SRAM, low-power design, failure analysis, memory test, power switch.
I.
INTRODUCTION
With the growing demand of high performance, multifunctional and hand-held devices, power dissipation has emerged as a major design concern. Simultaneously, technology scaling is shrinking device’s features as well as lowering the supply and threshold voltages which cause a significant increase of the leakage current. Leakage power has now become a major component of the total power dissipation in CMOS circuits [1]. In System-on-Chip (SoC) designs, embedded memories occupy a vast area of the design and contribute considerably to the chip’s static and dynamic power consumption. Various techniques have been proposed to reduce the static power consumption of SRAMs. Power gating is a widely and effective applied technique for reducing static power by shutting off idle memory blocks. At architectural level, power gating provides several power management modes for a given SRAM device. In general, three modes can be distinguished as: (1) active or standby mode, (2) deep-sleep mode, and (3) power-off mode. In active mode, the memory is connected to the nominal power supply voltage and performs any read/write operations. In deep-sleep mode, the memory is in an intermediate low-power mode such that the power supply voltage of the peripheral circuitry of the memory is gated-off, while the power supply voltage of the core-cell array is lowered at a level that allows data retention [2]. Finally, in power-off mode, the power supply voltage of the whole memory is shut off such that core-cells are no longer able to retain any data.
Figure 1. Power gating architecture
During the active mode, all PMOS transistors are activated (PMOS gates set to logic ‘0’). This configuration allows the core-cell array to be powered by nominal VDD. In both deepsleep and power-off modes, the PMOS transistors are deactivated (PMOS gates set to logic ‘1’), hence the core-cell array is no longer supplied by the nominal VDD. In deep-sleep mode, a voltage regulation system generates a fixed voltage level (Vreg in Figure 1), lower than the nominal VDD, to be provided to the core-cell array. The lower voltage drastically reduces the power consumption due to current leakage.
Power gating is generally implemented using power switches, which enable SRAM’s power management modes by varying the supply voltage to the core-cells and peripheral circuitry. Fault-free operation of power switches is crucial for 1081-7735/11 $26.00 © 2011 IEEE DOI 10.1109/ATS.2011.97
POWER GATING ARCHITECTURE AND FUNCTIONALITY
Power gating of a core-cell array is generally implemented through a network of PMOS transistors that are structured in several segments. In the considered structure, each segment is composed of four PMOS transistors. Figure 1 gives the scheme of a four-transistor power switch segment, which allows a wake up phase divided in four. Compared to segments composed by a single and large transistor, the structure with segments formed by several transistors proved higher circuit reliability and better controllability of the power management scheme [4].
The transition from sleep to active mode (wake up) is made in four steps. In Figure 2, the waveforms show the 459
already elapsed but the full power supply voltage of the core-cell array is still not reached.
voltage levels applied to each transistor of the power switch as well as the power voltage level of the cell array when transitioning from deep-sleep to active mode. The wake-up operation starts by setting the !SLEEP signal to logic ‘1’. The signals CTRL0 to CTRL3 are respectively applied to the gates of each PMOS transistor in a segment. The PMOS transistors are turned on in a cascade fashion, by decreasing order of impedance. This solution avoids peak rush-in currents during wake-up. At the end of this phase (time T3 in Figure 2), the power supply of the core-cell array (VDD_CC) is charged from a fixed voltage (Vreg) up to the nominal VDD (Vreg < VDD).
•
A power switch must be able to draw enough current for performing operations on the memory. This requires all four PMOS transistors activated. Therefore, a delay on any of the PMOS control signals may lead to a faulty behavior when performing operations on the SRAM with not all transistors activated.
•
The above effects may be exacerbated by corecell asymmetries due to process variations as well as by excessive noise on the power supply grid. Meaningful test solutions will be presented to detect such faulty behaviors. IV.
CONCLUSION
Malfunctioning of power switches can impact the performance and reliability of low-power SRAMs. Early operations performed on an SRAM with incorrect wake-up phase may not succeed. Furthermore, delays that affect the control of the power switch transistors can also lead to faulty operations. The goal of the proposed study is to investigate the conditions in which power-gated SRAMs will experience faulty behaviors and furthermore propose test solutions for detecting the related faults. REFERENCES [1] Figure 2. Switching from deep-sleep to active mode
III.
FAULTY SCENARIOS
[2]
In this work, we provide an in-depth analysis of low-power SRAMs failures summarized as: •
[3]
During the wake-up phase, a delay on the control signal !SLEEP can significantly increase the VDD_CC charging time. Thus, memory operations may fail when the wake-up time is
[4]
460
K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage Reduction Mechanism and Leakage Reduction Techniques in DeepSubmicrometer CMOS Circuits”, Proc. of IEEE, 2003, volume 91, pp. 305-327. K. Flautner et al, “Drowsy caches: simple techniques for reducing leakage power”, Proc. of ISCAS, 2002, pp. 148-157. A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch and A. Virazel, “Advanced Test Methods for SRAMs Effective Solutions for Dynamic Fault Detection in Nanoscale Technologies”, ISBN: 978-1-4419-0937-4, Springer, 2009. S. K. Goel, M. Meijer, and J. P. de Gyvs, “Testing and Diagnosis of Power Switches in SOCs”, Proc. of ETS, 2006, pp. 145-150.
Failure Analysis and Test Solutions for Low-Power SRAMs L. B. Zordan1 A. Bosio1 L. Dilillo1 P. Girard1 S. Pravossoudovitch1 A. Todri1 A. Virazel1 N. Badereddine2 1
LIRMM - Université Montpellier II / CNRS 161, rue Ada – 34095 Montpellier Cedex 5, France E-mail: @lirmm.fr
2
Intel Mobile Communications 2600, route des Crêtes – 06560 Sophia-Antipolis, France E-mail: [email protected]
Abstract—Low-power SRAMs embed power gating facilities for reducing power consumption. Power gating is applied using power switches for controlling the supply voltage applied to the memory cells i.e. one or more memory blocks can be disconnected from the power supply during a long time of inactivity, thus reducing the power consumption. In this paper, we provide a detailed analysis on the impact that defective power switches impose on the behavior of SRAM core-cells. Furthermore, we propose efficient test solutions to detect such faulty behaviors.
accurate and reliable operation of the SRAM. Our study analyzes the impact of defective power switches on the behavior of SRAM core-cells. Additionally, we propose efficient test solutions to detect such faulty behaviors. Our test strategy consists in providing realistic fault models and practical test solution with minimal application time [3]. II.
Keywords—SRAM, low-power design, failure analysis, memory test, power switch.
I.
INTRODUCTION
With the growing demand of high performance, multifunctional and hand-held devices, power dissipation has emerged as a major design concern. Simultaneously, technology scaling is shrinking device’s features as well as lowering the supply and threshold voltages which cause a significant increase of the leakage current. Leakage power has now become a major component of the total power dissipation in CMOS circuits [1]. In System-on-Chip (SoC) designs, embedded memories occupy a vast area of the design and contribute considerably to the chip’s static and dynamic power consumption. Various techniques have been proposed to reduce the static power consumption of SRAMs. Power gating is a widely and effective applied technique for reducing static power by shutting off idle memory blocks. At architectural level, power gating provides several power management modes for a given SRAM device. In general, three modes can be distinguished as: (1) active or standby mode, (2) deep-sleep mode, and (3) power-off mode. In active mode, the memory is connected to the nominal power supply voltage and performs any read/write operations. In deep-sleep mode, the memory is in an intermediate low-power mode such that the power supply voltage of the peripheral circuitry of the memory is gated-off, while the power supply voltage of the core-cell array is lowered at a level that allows data retention [2]. Finally, in power-off mode, the power supply voltage of the whole memory is shut off such that core-cells are no longer able to retain any data.
Figure 1. Power gating architecture
During the active mode, all PMOS transistors are activated (PMOS gates set to logic ‘0’). This configuration allows the core-cell array to be powered by nominal VDD. In both deepsleep and power-off modes, the PMOS transistors are deactivated (PMOS gates set to logic ‘1’), hence the core-cell array is no longer supplied by the nominal VDD. In deep-sleep mode, a voltage regulation system generates a fixed voltage level (Vreg in Figure 1), lower than the nominal VDD, to be provided to the core-cell array. The lower voltage drastically reduces the power consumption due to current leakage.
Power gating is generally implemented using power switches, which enable SRAM’s power management modes by varying the supply voltage to the core-cells and peripheral circuitry. Fault-free operation of power switches is crucial for 1081-7735/11 $26.00 © 2011 IEEE DOI 10.1109/ATS.2011.97
POWER GATING ARCHITECTURE AND FUNCTIONALITY
Power gating of a core-cell array is generally implemented through a network of PMOS transistors that are structured in several segments. In the considered structure, each segment is composed of four PMOS transistors. Figure 1 gives the scheme of a four-transistor power switch segment, which allows a wake up phase divided in four. Compared to segments composed by a single and large transistor, the structure with segments formed by several transistors proved higher circuit reliability and better controllability of the power management scheme [4].
The transition from sleep to active mode (wake up) is made in four steps. In Figure 2, the waveforms show the 459
already elapsed but the full power supply voltage of the core-cell array is still not reached.
voltage levels applied to each transistor of the power switch as well as the power voltage level of the cell array when transitioning from deep-sleep to active mode. The wake-up operation starts by setting the !SLEEP signal to logic ‘1’. The signals CTRL0 to CTRL3 are respectively applied to the gates of each PMOS transistor in a segment. The PMOS transistors are turned on in a cascade fashion, by decreasing order of impedance. This solution avoids peak rush-in currents during wake-up. At the end of this phase (time T3 in Figure 2), the power supply of the core-cell array (VDD_CC) is charged from a fixed voltage (Vreg) up to the nominal VDD (Vreg < VDD).
•
A power switch must be able to draw enough current for performing operations on the memory. This requires all four PMOS transistors activated. Therefore, a delay on any of the PMOS control signals may lead to a faulty behavior when performing operations on the SRAM with not all transistors activated.
•
The above effects may be exacerbated by corecell asymmetries due to process variations as well as by excessive noise on the power supply grid. Meaningful test solutions will be presented to detect such faulty behaviors. IV.
CONCLUSION
Malfunctioning of power switches can impact the performance and reliability of low-power SRAMs. Early operations performed on an SRAM with incorrect wake-up phase may not succeed. Furthermore, delays that affect the control of the power switch transistors can also lead to faulty operations. The goal of the proposed study is to investigate the conditions in which power-gated SRAMs will experience faulty behaviors and furthermore propose test solutions for detecting the related faults. REFERENCES [1] Figure 2. Switching from deep-sleep to active mode
III.
FAULTY SCENARIOS
[2]
In this work, we provide an in-depth analysis of low-power SRAMs failures summarized as: •
[3]
During the wake-up phase, a delay on the control signal !SLEEP can significantly increase the VDD_CC charging time. Thus, memory operations may fail when the wake-up time is
[4]
460
K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage Reduction Mechanism and Leakage Reduction Techniques in DeepSubmicrometer CMOS Circuits”, Proc. of IEEE, 2003, volume 91, pp. 305-327. K. Flautner et al, “Drowsy caches: simple techniques for reducing leakage power”, Proc. of ISCAS, 2002, pp. 148-157. A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch and A. Virazel, “Advanced Test Methods for SRAMs Effective Solutions for Dynamic Fault Detection in Nanoscale Technologies”, ISBN: 978-1-4419-0937-4, Springer, 2009. S. K. Goel, M. Meijer, and J. P. de Gyvs, “Testing and Diagnosis of Power Switches in SOCs”, Proc. of ETS, 2006, pp. 145-150.
