Fast and accurate quasi-three-dimensional capacitance determination ...
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Fast and Accurate Quasi-Three-Dimensional Capacitance Determination of Multilayer VLSI Interconnects Woojin Jin, Yungseon Eo, William R. Eisenstadt, Senior Member, IEEE, and Jongin Shim
Intermediate capacitance matrices concerned with a denotes a designated line in the th layer. The set of solid ground layers. Fringing capacitance of the th line in the th layer. Note that the spacing between the th line and the th line in the th layer is . Fringing capacitance of the th line in the th layer when the spacing between the th line and the th line in the th layer is infinite. That is, the th line is completely isolated from other lines. Intermetal dielectric thickness between the th layer th layer. The zeroth layer is assumed and the to be a system ground. Line length of a line in the th layer. Spacing between the th line and the th line in the th layer. Line thickness of a line in the th layer. Line width of the th line in the th layer. Filling factor concerned with a designated line in the th layer. That is, means that how much the designated line in the th layer is overlapped with th layer metals. the Filling factor concerned with a designated line in means how much the the th layer. That is, designated line in the th layer is overlapped with th layer metals.
Abstract—A new fast and accurate capacitance determination methodology for intricate multilayer VLSI interconnects is presented. Since a multilayer interconnect structure is too complicated to be directly tractable, it is simplified by investigating charge distributions within the system. The quasi-three-dimensional (3-D) capacitances of the structure are then determined by combining a set of solid-ground-based two-dimensional (2-D) capacitances and shielding effects that can be independently calculated from the simplified structure. The shielding effects due to the neighboring lines of a line can be analytically determined from the given layout dimensions. The solid-ground-based 2-D capacitances can also be quickly computed from the simplified structure. Thus, the proposed capacitance determination methodology is much more costefficient than conventional 3-D-based methods. It is shown that the calculated quasi-3-D capacitances have excellent agreement with 3-D field-solver-based results within 5% error. Index Terms—Crosstalk, interconnect capacitance, multilayer, shielding effect, signal delay, VLSI interconnects.
NOMENCLATURE1 Capacitance matrix concerned with a designated line in the th layer. Total overlap capacitance between a designated line th layer lines. of the th layer and the Parallel-plate capacitance between a line of the th layer and the system ground. Self-capacitance of a line of the th layer (i.e., the capacitance between the line and the system ground). Self-capacitance of a line of the th layer when it is completely isolated from other neighboring lines of the th layer (it is the special case of ). Total underlap capacitance between a designated th layer lines. line of the th layer and the Manuscript received September 14, 1999; revised July 28, 2000. This work was supported by the Center for Electronic Packaging Materials, Korea Science and Engineering Foundation. W. Jin, Y. Eo, and J. Shim are with the Department of Electrical and Computer Engineering, Hanyang University, Kyungki-Do 425-791, South Korea (e-mail: [email protected]; [email protected]). W. R. Eisenstadt is with the Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611-6130 USA (e-mail: [email protected]). Publisher Item Identifier S 1063-8210(01)03297-8. 1Note: A superscript is employed to denote layer information, not as a power index.
I. INTRODUCTION
A
S MINIMUM feature size continues to be scaled down, modern VLSI circuits can cost-effectively integrate a myriad of functional circuit blocks on a single chip [1]. In contrast, circuit clock frequency, which is now near the gigahertz range, keeps increasing [1]–[4]. In such high-performance VLSI circuits, interconnect lines, rather than the gates, are the major limiting factors of the circuit performance [2]–[7]. The primary adverse effects due to the interconnect lines are the signal delay and crosstalk [8]. As a technology becomes more advanced, the effects will be more apparent since the future clock frequencies will be higher and interconnect structures will be longer as well as much tighter. The accurate determination of interconnect capacitance is important in order to accurately characterize IC signal delay and crosstalk. Thus, considerable effort has been exerted on the interconnect capacitance extraction. To date, two-dimensional (2-D)-based capacitance extraction methodologies have been
1063–8210/01$10.00 © 2001 IEEE
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Fig. 1. Schematic description for the capacitance determination of a multilayer interconnect structure.
widely employed for IC computer-aided design (CAD) timing verification and signal integrity analysis since IC capacitances can be quickly determined by them [9]–[11]. However, modern multilayered interconnect structures have inherent three-dimensional (3-D) properties that should not be neglected any longer. Although 2-D techniques are very efficient in computation time, they are not accurate enough for the signal integrity verification of today’s VLSI circuits. In order to improve capacitance simulation, many 3-D-based techniques have been developed [12]–[16]. However, these 3-D techniques need a huge amount of computation time even for a relatively simple 3-D structure. Thus, there has been a growing need for a fast as well as an accurate 3-D-based capacitance extraction methodology. Recently, efficient quasi-3-D capacitance extraction methodologies for multilayer interconnect structures were developed [17]–[20]. In [17], [19], and [20], empirical capacitance models based on 2-D and 3-D simulation-based data were presented. However, such empirical models are too inaccurate to be employed in modern high-performance IC design. In [18], the capacitance extraction problem was ac-
tually simplified by using five fundamental steps that can simplify the complicated interconnects structure. However, the technique requires preprocessed capacitance libraries based on specific structures. Thus, it is not efficient or general. Further, the empirical fitting for the library construction may cause inaccuracy problem. In this paper, a new accurate as well as efficient multilayer interconnect capacitance extraction method is presented. The capacitance calculation procedures of the method are schematically described in Fig. 1 (see the gray boxes). That is, first, a given 3-D structure is simplified by investigating negative charge distribution characteristics corresponding to positive charges. Second, a set of solid grounds corresponding to a designated line (we define the line as an objective line) is established, followed by the solid-ground-based 2-D capacitance extraction for the simplified structure. Third, shielding effects between lines are analytically determined from the layout of the simplified structure. Last, the quasi-3-D capacitances concerned with the objective line are calculated by combining the solid-ground-based 2-D capacitances (intermediate capaci-
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Fig. 2.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 3, JUNE 2001
A general multilayer interconnect structure.
tances) with the shielding effects. The solid-ground-based 2-D capacitance matrices and the shielding effects corresponding to the designated objective line can be easily calculated from the layout geometry even in complicated multilayer structures. Thus, the technique can substantially reduce the capacitance determination time. It is shown that the calculated capacitances have excellent agreements with 3-D field-solver-based results, within 5% error.
II. QUASI-3-D CAPACITANCE DETERMINATION A multilayer interconnect structure is inherently a 3-D structure that makes a direct capacitance parameter extraction impractical due to the huge amount of computation time. However, the problem can be overcome if a given layout structure is simplified without losing its physical characteristics. An IC interconnect structure for a capacitance determination can be simplified a fair amount by investigating the negative charges corresponding to the positive charges in the system. Since an electric field is a conservative field, the negative charges corresponding to the positive charges must exist within a system. The negative charge distributions corresponding to the positive charges vary with the geometry of the structure (i.e., space, thickness, width, etc.), although the total amount of charges does not vary. Thus, by investigating the ratio of the negative charge distribution to the positive charge, the system can be simplified. That is, in places with a small charge ratio indicates that the negatively charged line has little effect on the nearby positively charged line, the negatively charged lines can be neglected for the capacitance determination. Thus, by defining the charge ratio ( ) as the amount of negative charges of a line near that of the positive charges of an objective line, the system can be simplified a fair amount. In addition, considering the shielding effects between the lines, the problem is further simplified. That is, the inherent 3-D-problem can be solved by using a quasi-2-D technique with the shielding effects. Thus, the accurate quasi-3-D capacitances
can be readily determined. This is discussed in the ensuing sections in more detail. A. Structure Simplification In a multilayer interconnect structure, as shown in Fig. 2, a direct capacitance parameter extraction is impractical due to the complexity in its structure. Thus, the structure needs to be simplified as much as possible. In real interconnect structures, most of the negative charges corresponding to the positive charges of an objective line are distributed over the neighboring lines of the objective line. Since all other lines except for the negatively charged lines can be deleted from the system, the structure can be substantially simplified. For example, a charge ratio concerned with the structure of Fig. 3(a) is shown in Fig. 3(b). It is evident that the layers far away from the th layer (i.e., objective layer) have little effect on the system. The effect is more apparent as the line spacing of th layer becomes closer. Thus, the structure of Fig. 2 the can be fairly simplified, as shown in Fig. 4, treating both the th layers as solid ground planes. B. Shielding Effects Although the complicated structure can be simplified as shown in Fig. 4, it cannot be treated as a 2-D structure. However, once the shielding effects due to the neighboring lines (i.e., neighboring lines within the objective layer and neighboring lines between the layers) are determined, the 3-D effects can be neglected, thereby determining the quasi-3-D capacitances by using a 2-D technique. 1) Shielding Effect Within a Layer: The self-capacitance for a completely isolated line, as shown in Fig. 5(a), can be represented by (1) is the fringing capacitance for the infinite spacing Note that can be fairly well modeled in terms of between the lines.
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Fig. 3. Total negative charge distribution on (j charge ratio.
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0 2)th layer corresponding to the positive charge of the objective line on the j th layer. (a) The structure. (b) The
Fig. 4. The simplified structure of the Fig. 2 with the negative charge distribution concept. (Note that only the (j significant effect on the objective line).
the aspect ratio of an interconnect structure [21]. However, more practically, the line may not be completely isolated as shown in Fig. 5(b). The per-unit-length self-capacitance of such a noniso-
6 2)th layers and the (j 6 1)th layers have
lated line can be formulated by (2)
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Fig. 5. Capacitances with the fringing effects. (a) An isolated line. (b) Coupled lines.
where and are the fringing capacitances with the and , respectively. They are also functions spacing of and the spacing of the intermetal dielectric thickness and ). Note that as the space between between the lines ( an objective line and a neighboring line decreases, the fringing capacitance also decreases. Furthermore, if its dielectric thickness increases, the fringing capacitance decreases. Thus, the fringing capacitance can be modeled well as for
where
(3)
is (4)
For the structure shown in Fig. 5(b), the accuracy of (2) according to the aspect ratio variation is shown in Fig. 6. This shows excellent agreement with 3-D field-solver-based results within 5% error. 2) Interlayer Shielding Effect: In addition to the shielding effect between the lines within the same layer, there is another shielding effect due to the interlayer metals (i.e., the shielding effect between layers). The interlayer shielding effect can be formulated with the overlap capacitance (or underlap capacitances) between the objective line and other layer lines, as shown in Fig. 7. The overlap capacitance can be accurately calculated by introducing a filling factor, which denotes the portion of the objective line length that is overlapped with the other layer metals.
Fig. 6. Fringing capacitance variations with the line width and line spacing between the lines.
Moreover, the overlap capacitances can be determined by using the solid-ground-based per-unit-length self-capacitance of the objective line, which has adjacent lines (i.e., nonisolated line) as shown in Fig. 5(b). Thus, the total overlap capacitance associated with the objective line shown in Fig. 7 can be represented by (5)
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Fig. 7. The multilayer structure and overlap capacitance corresponding to a designated objective line.
where
Thus, similarly, since the overlap capacitance associated with the objective line can be determined by using (5), the total overlap capacitance can be calculated by using the ). solid-ground-based per-unit-length self-capacitance ( uses only a (3 3) matrix, as shown in Fig. 5(b). Note that Now, a filling factor concerned with the th layer objective line th layer can be formulated as and the (6) Then, combining (5) with (6), (6) can become a more compact form as follows:
shielding effects) is determined by regarding a group of metal layers as the solid grounds. The solid ground means that a layer (or layers) is considered to be a perfect ground plane. The superscript of the denotes the th layer that has the objecdenotes a set of solid ground tive line, and the subscript means that the objective layers. For example, 2 th layers are considered to line is in the th layer and is a be the solid ground, as shown in Fig. 8. Note that 2-D-based capacitance matrix. Then the quasi-3-D interconnect capacitances concerned with the th layer objective line can be calculated by combining the separately determined shielding efand ) with the solid-ground-based intermediate fects ( . Note that the general procedures capacitance matrices for the quasi-3-D capacitance calculation are exactly equal to the flow diagram of Fig. 1. It is noteworthy that the multilayer capacitances concerned with an objective line can be readily determined without resorting to the time-consuming 3-D calculation. In the next section, the methodology will be discussed in more detail with an example.
(7) III. EXAMPLE AND VERIFICATION OF THE ALGORITHM Thus, the total overlap capacitance can be readily calculated (i.e., th layer filling factor concerned with only if are determined. is a the th layer objective line) and , metal widths ( and function of dielectric thickness ), and metal spacings ( and ). It can be readily determined from the given layout geometry. C. Quasi-3-D Capacitance Determination Exploiting the previous results, the quasi-3-D capacitance can be readily determined. The calculation procedures can be summarized as follows. Once the system is simplified, a set of inter(which do not consider the mediate capacitance matrices
In this section, the capacitance calculation procedures are explained in more detail by using a multilayer structure, as shown in Fig. 2. It is assumed that the objective line is in the th layer. First, the structure can be simplified according to the methodology of the previous section, as shown in Fig. 4. Then the capacitance matrix of the structure concerned with the objective 3 3 matrix if the numbers line becomes an th and th are and , respecof the lines of the tively. Note the simplified structure has five layers. The overlap and underlap capacitances can be calculated by combining the solid-ground-based intermediate capacitance [i.e., (3 3) maand ). That is, we only trix] and filling factors (i.e.,
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Fig. 8. 2-D structures with the solid grounds, i.e., (d) F .
[ ]
[F ]
. Shown are the structures for (a)
[F ]
, (b)
[F ]
, (c)
[F ]
, and
Fig. 9. A simple structure for the numerical example of the quasi-3-D capacitance determination. (a) Geometrical dimension. (b) Capacitances concerned with the objective line ( C c c c , where c c c c c ).
[ ] = [0
0 ]
+ +
+
need the 2-D solid-ground-based capacitances for the calculation of the capacitances that are associated with the simplified structure (Fig. 4). The 2-D intermediate capacitances for the are schematically shown in Fig. 8. The interstructure mediate capacitances can be determined by using the structures as shown in Fig. 8. That is (8)
(9)
(10)
(11) Note that these capacitances can be readily determined since they are 2-D in structure. Then the filling factors concerned 1 th layer ( and ) can be determined with the by using (6). Finally, the capacitances associated with the objective line can be calculated by combining the intermediate capacitance matrices (i.e.,
JIN et al.: QUASI-3-D CAPACITANCE DETERMINATION
Fig. 10.
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A numerical example for the capacitance determination procedures concerned with the objective line of the structure of Fig. 9.
and ) with the filling factors and ). That is, considering the shielding effects (i.e., matrix associated with the objective line of each layer, the can be determined as follows:
be derived as
(13) (12) Since the matrix of (12) is 3 3, the coupling capacitances in the same layer as the objective line can be extracted by using (12) [i.e., off-diagonal elements of the matrix (12)]. Similarly, the total overlap capacitance and total underlap capacitance can
(14)
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TABLE I THE ACCURACY AND RUN-TIME COMPARISON
Fig. 11. Extracted capacitance variations according to the number of the underlayer conductors (i.e., the filling factor variation).
The self-capacitance can be determined as follows:
(15) For a numerical example, the capacitance determination procedures of the structure of Fig. 9 are described step by step in Fig. 10 (refer to Fig. 1 for each step). The results are compared with the 3-D field-solver-based values in Fig. 11 and are found to have excellent agreement. In addition, capacitances for a more complicated structure, as shown in Fig. 13, are determined. The results also have excellent agreement with a 3-D field-solver (MAXWELL), as shown in Table I. As can be seen in Table I, the computation time of the proposed technique is 26 times faster than that of 3-D-based techniques. Furthermore, the capacitance for the heterogeneous structure can be determined by dividing it into parts whenever the objective line encounters discontinuities such as bend, via, etc. Then the capacitance of the objective line can be derived by summing up all the partial capacitances. IV. APPLICATION OF THE ALGORITHM IN GENERAL STRUCTURE The signal delay and crosstalk for extremely complicated interconnect circuits with shielding layers was evaluated by using the proposed quasi-3-D capacitance extraction method. To show the shielding effect, a test circuit cascaded with various interconnect line cells is defined, as shown in Fig. 12(a). Then the signal delay and crosstalk are investigated for the structure. In Fig. 12(a), the CMOS inverters of size and (W/L) are (W/L) used for both the driver and the receiver. Both the rise time and fall time of an input pulse are assumed to be 0.1 ns. The
Fig. 12. Test circuit model for various interconnect structures. The circuit is cascaded with ten cells composed of interconnect lines. (a) Circuit configuration. (b) Switching conditions.
circuit switching conditions are defined as shown in Fig. 12(b). The capacitance parameters for each cell, i.e., Fig. 13, are determined by using both the proposed quasi-3-D method and the 3-D field-solver. The parameters are summarized in Table I. The circuit performance is investigated by using a general-purpose circuit simulator, HSPICE. The circuit responses of the structure of Fig. 12 are shown in Fig. 14. It is clearly shown that the capacitance variations due to the shielding effect between the lines or between the layers have considerable effects on both the signal delay and crosstalk noise since the neighboring metals modify field patterns (i.e., the coupling capacitances and the self-capacitance) of the objective line. Thus, the 3-D effects of the interconnect lines cannot be neglected for the signal integrity analysis of today’s high-performance VLSI circuits. However, it is not practical to use the conventional 3-D-based methods because of the huge computation time. In contrast, the proposed quasi-3-D technique can be usefully employed for complicated interconnect structures since its computational time is similar to the conventional 2-D capacitance determination, preserving the accuracy similar to the 3-D-based techniques.
JIN et al.: QUASI-3-D CAPACITANCE DETERMINATION
Fig. 13.
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An interconnect structure to investigate the shielding effects of Fig. 12.
tance determination method that can efficiently take the 3-D effect into account was developed. In order to use the quasi-3-D technique, shielding effects and solid-ground-based 2-D capacitance from a given layout geometry were determined. Since the shielding effects and the solid-ground-based capacitance matrices can be readily determined from the layout geometry, the accurate as well as efficient quasi-3-D capacitances associated with an objective line can be readily determined. To demonstrate the method’s efficiency and accuracy, the capacitance parameters and circuit responses were benchmarked with 3-D field-solver-based results. It was shown that the results have excellent agreements with 3-D field solver-based results within about 5% error. Thus, the proposed technique can be usefully employed for the verification of the signal integrity of today’s complicated IC interconnects. ACKNOWLEDGMENT (a)
The authors wish to acknowledge that the CAD tools were provided by IDEC. REFERENCES
(b) Fig. 14. Signal transients for the network using the cell of Fig. 13. (a) The signal transients due to switching case A of Fig. 13. (b) The crosstalk noises due to switching case B of Fig. 13.
V. SUMMARY AND CONCLUSION In this paper, a new capacitance parameter determination method was presented. An inherently complicated IC interconnect structure was simplified by investigating charge distributions within the system. Then a new efficient capaci-
[1] “International technology roadmap for semiconductors,”, SIA Rep., 1999. [2] P. J. Restle, K. A. Jenkins, A. Deutsch, and P. W. Cook, “Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocess,” IEEE J. Solid-State Circuits, vol. 33, pp. 662–665, Apr. 1998. [3] C. Akrout et al., “A 480-MHz RISC microprocessor in a 0.12-m L CMOS technology with copper interconnects,” IEEE J. Solid-State Circuits, vol. 33, pp. 1609–1616, Nov. 1998. [4] D. W. Bailey and B. J. Benschneider, “Clocking design and analysis for a 600-MHz alpha microprocessor,” IEEE J. Solid-State Circuits, vol. 33, pp. 1627–1633, Nov. 1998. [5] M. T. Bohr, “Interconnect scaling—The real limiter to high performance ULSI,” in Proc. IEEE Int. Electron Device Meeting Tech. Dig., Dec. 1995, pp. 241–244. [6] A. Deutsch et al., “When are transmission-line effects important for on-chip interconnects?,” IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1836–1834, Oct. 1997. [7] J.-S. Yim and C.-M. Kyung, “Reducing cross-coupling among interconnect wires in deep-submicron datapath design,” in Proc. 36th Design Automation Conf., 1999, pp. 485–490. [8] H. B. Bakoglu, Circuits, Interconnects and Packaging for VLSI. New York: Addison-Wesley, 1990. [9] W. T. Weeks, “Calculation of coefficients of capacitance of multiconductor transmission lines in the presence of a dielectric interface,” IEEE Trans. Microwave Theory Tech., vol. MTT-18, pp. 35–43, Jan. 1970. [10] D. Homentcovschi and R. Oprea, “Analytically determined quasistatic parameters of shielded or open multiconductor microstrip lines,” IEEE Trans. Microwave Theory Tech., vol. 46, pp. 18–24, Jan. 1998. [11] E. A. Dengi, “Boundary element method macromodels for 2-D hierarchical capacitance extraction,” in Proc. 35th Design Automation Conf., 1998, pp. 218–223. [12] J. Zheng, Z.-F. Li, and X.-N. Qian, “An efficient solver for the threedimensional capacitance of the interconnects in high speed digital circuit by the multiresolution method of moments,” IEEE Trans. Adv. Packag., vol. 22, pp. 9–15, Feb. 1999.
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[13] H.-M. How and C.-S. Sheen, and C.-Y. Wu, “A novel modeling technique for efficiently computing 3-D capacitances of VLSI multilevel interconnections-BFEM,” IEEE Trans. Electron Devices, vol. 45, pp. 200–205, Jan. 1999. [14] V. Veremey and R. Mittra, “A technique for fast calculation of capacitance matrices of interconnect structures,” IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 21, pp. 241–249, Aug. 1998. [15] A. H. Zemanian, R. P. Tewarson, C. P. Ju, and J. F. Jen, “Three-dimensional capacitance computations for VLSI/ULSI interconnections,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 1319–1326, Dec. 1989. [16] K. Nabors, S. Kim, and J. White, “Fast capacitance extraction of general three-dimensional structures,” IEEE Trans. Microwave Theory Tech., vol. 40, pp. 1496–1506, July 1992. [17] J.-H. Chern, J. Huang, L. Arledge, P.-C. Li, and P. Yang, “Multilevel metal capacitance models for CAD design synthesis systems,” IEEE Electron Device Lett., vol. 13, pp. 32–34, Jan. 1992. [18] J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali, and S. H.-C. Yen, “Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology,” in Proc. 34th Design Automation Conf., 1997, pp. 627–632. [19] N. D. Arora, K. V. Raol, R. Schumann, and L. M. Richardson, “Modeling and extraction of interconnect capacitance for multilayer VLSI circuits,” IEEE Trans. Computer-Aided Design, vol. 15, pp. 58–67, Jan. 1996. [20] U. Choudhury and A. Sangiovanni-Vincentelli, “Automatic generation of analytical models for interconnect capacitances,” IEEE Trans. Computer-Aided Design, vol. 14, pp. 470–480, Apr. 1995. [21] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. New York: Cambridge Univ. Press, 1998.
Woojin Jin received the B.S. and M.S. degrees in electronic engineering from Hanyang University, Korea, in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree. His research interests are in the area of high-speed VLSI circuit design, simulation methodology of solid-state circuits, and integrated circuit packaging.
Yungseon Eo received the B.S. and M.S. degrees in electronic engineering from Hanyang University, Seoul, Korea, in 1983 and 1985, respectively, and the Ph.D. degree in electrical engineering from the University of Florida, Gainesville, in 1993. From 1986 to 1988, he was with the Korea Telecommunication Authority Research Center, Seoul, where he performed telecommunication network planning and software design. From 1993 to 1994, he performed s-parameter-based BJT device characterization and modeling for high-speed circuit design at Applied Micro Circuits Corporation, San Diego, CA. From 1994 to 1995, he was with the Research and Development Center of LSI Logic Corporation, Santa Clara, CA, where he worked in the area of signal integrity characterization and modeling of high-speed CMOS circuits and interconnects. In 1995, he joined the Department of Electrical and Computer Engineering, Hanyang University, Ansan, Korea, where he is now an Associate Professor. His research interests are high-frequency characterization and modeling of integrated circuits and interconnects and high-speed VLSI circuit packaging.
William R. Eisenstadt (S’78–M’84–SM’92) received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1979, 1981, and 1986, respectively. In 1984, he joined the Faculty of the University of Florida, Gainesville, where he is now an Associate Professor. His research is concerned with highfrequency characterization, simulation, and modeling of integrated circuit devices, packages, and interconnect. In addition, he is interested in large-signal microwave-circuit and analog-circuit design. Dr. Eisenstadt received the NSF Presidential Young Investigator Award in 1985.
Jongin Shim was born in Kangreung, Korea, in 1960. He received the B.S. and M.S. degrees in electronics from Seoul National University, Seoul, Korea, in 1983 and 1985, respectively, and the Ph.D. degree from the Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan, in 1992. His Ph.D. dissertation was mainly concerned with static and dynamic properties of single-mode lasers such as DR distributed Bragg reflector and distributed feedback lasers. From 1985 to 1988, he was with the Electronics and Telecommunications Research Institute (ETRI), Taejon, Korea, where he worked on InGaAsP-InP optoelectronics lasers. In 1992, he joined the Optoelectronics Research Laboratory of NEC, Tsukuba, Japan, where he conducted research on tunability and coherence of semiconductor lasers and their fabrication technology by selective MOVPE growth. He has since joined the Department of Electrical and Computer Engineering, Hanyang University, Ansan, Korea, as an Associate Professor. His primary interests are optoelectronic semiconductor device modeling and optoelectronic packaging. Dr. Shim received a Student Award of Excellence in 1992 from the Tokyo Institute of Technology.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 3, JUNE 2001
Fast and Accurate Quasi-Three-Dimensional Capacitance Determination of Multilayer VLSI Interconnects Woojin Jin, Yungseon Eo, William R. Eisenstadt, Senior Member, IEEE, and Jongin Shim
Intermediate capacitance matrices concerned with a denotes a designated line in the th layer. The set of solid ground layers. Fringing capacitance of the th line in the th layer. Note that the spacing between the th line and the th line in the th layer is . Fringing capacitance of the th line in the th layer when the spacing between the th line and the th line in the th layer is infinite. That is, the th line is completely isolated from other lines. Intermetal dielectric thickness between the th layer th layer. The zeroth layer is assumed and the to be a system ground. Line length of a line in the th layer. Spacing between the th line and the th line in the th layer. Line thickness of a line in the th layer. Line width of the th line in the th layer. Filling factor concerned with a designated line in the th layer. That is, means that how much the designated line in the th layer is overlapped with th layer metals. the Filling factor concerned with a designated line in means how much the the th layer. That is, designated line in the th layer is overlapped with th layer metals.
Abstract—A new fast and accurate capacitance determination methodology for intricate multilayer VLSI interconnects is presented. Since a multilayer interconnect structure is too complicated to be directly tractable, it is simplified by investigating charge distributions within the system. The quasi-three-dimensional (3-D) capacitances of the structure are then determined by combining a set of solid-ground-based two-dimensional (2-D) capacitances and shielding effects that can be independently calculated from the simplified structure. The shielding effects due to the neighboring lines of a line can be analytically determined from the given layout dimensions. The solid-ground-based 2-D capacitances can also be quickly computed from the simplified structure. Thus, the proposed capacitance determination methodology is much more costefficient than conventional 3-D-based methods. It is shown that the calculated quasi-3-D capacitances have excellent agreement with 3-D field-solver-based results within 5% error. Index Terms—Crosstalk, interconnect capacitance, multilayer, shielding effect, signal delay, VLSI interconnects.
NOMENCLATURE1 Capacitance matrix concerned with a designated line in the th layer. Total overlap capacitance between a designated line th layer lines. of the th layer and the Parallel-plate capacitance between a line of the th layer and the system ground. Self-capacitance of a line of the th layer (i.e., the capacitance between the line and the system ground). Self-capacitance of a line of the th layer when it is completely isolated from other neighboring lines of the th layer (it is the special case of ). Total underlap capacitance between a designated th layer lines. line of the th layer and the Manuscript received September 14, 1999; revised July 28, 2000. This work was supported by the Center for Electronic Packaging Materials, Korea Science and Engineering Foundation. W. Jin, Y. Eo, and J. Shim are with the Department of Electrical and Computer Engineering, Hanyang University, Kyungki-Do 425-791, South Korea (e-mail: [email protected]; [email protected]). W. R. Eisenstadt is with the Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611-6130 USA (e-mail: [email protected]). Publisher Item Identifier S 1063-8210(01)03297-8. 1Note: A superscript is employed to denote layer information, not as a power index.
I. INTRODUCTION
A
S MINIMUM feature size continues to be scaled down, modern VLSI circuits can cost-effectively integrate a myriad of functional circuit blocks on a single chip [1]. In contrast, circuit clock frequency, which is now near the gigahertz range, keeps increasing [1]–[4]. In such high-performance VLSI circuits, interconnect lines, rather than the gates, are the major limiting factors of the circuit performance [2]–[7]. The primary adverse effects due to the interconnect lines are the signal delay and crosstalk [8]. As a technology becomes more advanced, the effects will be more apparent since the future clock frequencies will be higher and interconnect structures will be longer as well as much tighter. The accurate determination of interconnect capacitance is important in order to accurately characterize IC signal delay and crosstalk. Thus, considerable effort has been exerted on the interconnect capacitance extraction. To date, two-dimensional (2-D)-based capacitance extraction methodologies have been
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Fig. 1. Schematic description for the capacitance determination of a multilayer interconnect structure.
widely employed for IC computer-aided design (CAD) timing verification and signal integrity analysis since IC capacitances can be quickly determined by them [9]–[11]. However, modern multilayered interconnect structures have inherent three-dimensional (3-D) properties that should not be neglected any longer. Although 2-D techniques are very efficient in computation time, they are not accurate enough for the signal integrity verification of today’s VLSI circuits. In order to improve capacitance simulation, many 3-D-based techniques have been developed [12]–[16]. However, these 3-D techniques need a huge amount of computation time even for a relatively simple 3-D structure. Thus, there has been a growing need for a fast as well as an accurate 3-D-based capacitance extraction methodology. Recently, efficient quasi-3-D capacitance extraction methodologies for multilayer interconnect structures were developed [17]–[20]. In [17], [19], and [20], empirical capacitance models based on 2-D and 3-D simulation-based data were presented. However, such empirical models are too inaccurate to be employed in modern high-performance IC design. In [18], the capacitance extraction problem was ac-
tually simplified by using five fundamental steps that can simplify the complicated interconnects structure. However, the technique requires preprocessed capacitance libraries based on specific structures. Thus, it is not efficient or general. Further, the empirical fitting for the library construction may cause inaccuracy problem. In this paper, a new accurate as well as efficient multilayer interconnect capacitance extraction method is presented. The capacitance calculation procedures of the method are schematically described in Fig. 1 (see the gray boxes). That is, first, a given 3-D structure is simplified by investigating negative charge distribution characteristics corresponding to positive charges. Second, a set of solid grounds corresponding to a designated line (we define the line as an objective line) is established, followed by the solid-ground-based 2-D capacitance extraction for the simplified structure. Third, shielding effects between lines are analytically determined from the layout of the simplified structure. Last, the quasi-3-D capacitances concerned with the objective line are calculated by combining the solid-ground-based 2-D capacitances (intermediate capaci-
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Fig. 2.
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A general multilayer interconnect structure.
tances) with the shielding effects. The solid-ground-based 2-D capacitance matrices and the shielding effects corresponding to the designated objective line can be easily calculated from the layout geometry even in complicated multilayer structures. Thus, the technique can substantially reduce the capacitance determination time. It is shown that the calculated capacitances have excellent agreements with 3-D field-solver-based results, within 5% error.
II. QUASI-3-D CAPACITANCE DETERMINATION A multilayer interconnect structure is inherently a 3-D structure that makes a direct capacitance parameter extraction impractical due to the huge amount of computation time. However, the problem can be overcome if a given layout structure is simplified without losing its physical characteristics. An IC interconnect structure for a capacitance determination can be simplified a fair amount by investigating the negative charges corresponding to the positive charges in the system. Since an electric field is a conservative field, the negative charges corresponding to the positive charges must exist within a system. The negative charge distributions corresponding to the positive charges vary with the geometry of the structure (i.e., space, thickness, width, etc.), although the total amount of charges does not vary. Thus, by investigating the ratio of the negative charge distribution to the positive charge, the system can be simplified. That is, in places with a small charge ratio indicates that the negatively charged line has little effect on the nearby positively charged line, the negatively charged lines can be neglected for the capacitance determination. Thus, by defining the charge ratio ( ) as the amount of negative charges of a line near that of the positive charges of an objective line, the system can be simplified a fair amount. In addition, considering the shielding effects between the lines, the problem is further simplified. That is, the inherent 3-D-problem can be solved by using a quasi-2-D technique with the shielding effects. Thus, the accurate quasi-3-D capacitances
can be readily determined. This is discussed in the ensuing sections in more detail. A. Structure Simplification In a multilayer interconnect structure, as shown in Fig. 2, a direct capacitance parameter extraction is impractical due to the complexity in its structure. Thus, the structure needs to be simplified as much as possible. In real interconnect structures, most of the negative charges corresponding to the positive charges of an objective line are distributed over the neighboring lines of the objective line. Since all other lines except for the negatively charged lines can be deleted from the system, the structure can be substantially simplified. For example, a charge ratio concerned with the structure of Fig. 3(a) is shown in Fig. 3(b). It is evident that the layers far away from the th layer (i.e., objective layer) have little effect on the system. The effect is more apparent as the line spacing of th layer becomes closer. Thus, the structure of Fig. 2 the can be fairly simplified, as shown in Fig. 4, treating both the th layers as solid ground planes. B. Shielding Effects Although the complicated structure can be simplified as shown in Fig. 4, it cannot be treated as a 2-D structure. However, once the shielding effects due to the neighboring lines (i.e., neighboring lines within the objective layer and neighboring lines between the layers) are determined, the 3-D effects can be neglected, thereby determining the quasi-3-D capacitances by using a 2-D technique. 1) Shielding Effect Within a Layer: The self-capacitance for a completely isolated line, as shown in Fig. 5(a), can be represented by (1) is the fringing capacitance for the infinite spacing Note that can be fairly well modeled in terms of between the lines.
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Fig. 3. Total negative charge distribution on (j charge ratio.
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0 2)th layer corresponding to the positive charge of the objective line on the j th layer. (a) The structure. (b) The
Fig. 4. The simplified structure of the Fig. 2 with the negative charge distribution concept. (Note that only the (j significant effect on the objective line).
the aspect ratio of an interconnect structure [21]. However, more practically, the line may not be completely isolated as shown in Fig. 5(b). The per-unit-length self-capacitance of such a noniso-
6 2)th layers and the (j 6 1)th layers have
lated line can be formulated by (2)
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Fig. 5. Capacitances with the fringing effects. (a) An isolated line. (b) Coupled lines.
where and are the fringing capacitances with the and , respectively. They are also functions spacing of and the spacing of the intermetal dielectric thickness and ). Note that as the space between between the lines ( an objective line and a neighboring line decreases, the fringing capacitance also decreases. Furthermore, if its dielectric thickness increases, the fringing capacitance decreases. Thus, the fringing capacitance can be modeled well as for
where
(3)
is (4)
For the structure shown in Fig. 5(b), the accuracy of (2) according to the aspect ratio variation is shown in Fig. 6. This shows excellent agreement with 3-D field-solver-based results within 5% error. 2) Interlayer Shielding Effect: In addition to the shielding effect between the lines within the same layer, there is another shielding effect due to the interlayer metals (i.e., the shielding effect between layers). The interlayer shielding effect can be formulated with the overlap capacitance (or underlap capacitances) between the objective line and other layer lines, as shown in Fig. 7. The overlap capacitance can be accurately calculated by introducing a filling factor, which denotes the portion of the objective line length that is overlapped with the other layer metals.
Fig. 6. Fringing capacitance variations with the line width and line spacing between the lines.
Moreover, the overlap capacitances can be determined by using the solid-ground-based per-unit-length self-capacitance of the objective line, which has adjacent lines (i.e., nonisolated line) as shown in Fig. 5(b). Thus, the total overlap capacitance associated with the objective line shown in Fig. 7 can be represented by (5)
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Fig. 7. The multilayer structure and overlap capacitance corresponding to a designated objective line.
where
Thus, similarly, since the overlap capacitance associated with the objective line can be determined by using (5), the total overlap capacitance can be calculated by using the ). solid-ground-based per-unit-length self-capacitance ( uses only a (3 3) matrix, as shown in Fig. 5(b). Note that Now, a filling factor concerned with the th layer objective line th layer can be formulated as and the (6) Then, combining (5) with (6), (6) can become a more compact form as follows:
shielding effects) is determined by regarding a group of metal layers as the solid grounds. The solid ground means that a layer (or layers) is considered to be a perfect ground plane. The superscript of the denotes the th layer that has the objecdenotes a set of solid ground tive line, and the subscript means that the objective layers. For example, 2 th layers are considered to line is in the th layer and is a be the solid ground, as shown in Fig. 8. Note that 2-D-based capacitance matrix. Then the quasi-3-D interconnect capacitances concerned with the th layer objective line can be calculated by combining the separately determined shielding efand ) with the solid-ground-based intermediate fects ( . Note that the general procedures capacitance matrices for the quasi-3-D capacitance calculation are exactly equal to the flow diagram of Fig. 1. It is noteworthy that the multilayer capacitances concerned with an objective line can be readily determined without resorting to the time-consuming 3-D calculation. In the next section, the methodology will be discussed in more detail with an example.
(7) III. EXAMPLE AND VERIFICATION OF THE ALGORITHM Thus, the total overlap capacitance can be readily calculated (i.e., th layer filling factor concerned with only if are determined. is a the th layer objective line) and , metal widths ( and function of dielectric thickness ), and metal spacings ( and ). It can be readily determined from the given layout geometry. C. Quasi-3-D Capacitance Determination Exploiting the previous results, the quasi-3-D capacitance can be readily determined. The calculation procedures can be summarized as follows. Once the system is simplified, a set of inter(which do not consider the mediate capacitance matrices
In this section, the capacitance calculation procedures are explained in more detail by using a multilayer structure, as shown in Fig. 2. It is assumed that the objective line is in the th layer. First, the structure can be simplified according to the methodology of the previous section, as shown in Fig. 4. Then the capacitance matrix of the structure concerned with the objective 3 3 matrix if the numbers line becomes an th and th are and , respecof the lines of the tively. Note the simplified structure has five layers. The overlap and underlap capacitances can be calculated by combining the solid-ground-based intermediate capacitance [i.e., (3 3) maand ). That is, we only trix] and filling factors (i.e.,
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Fig. 8. 2-D structures with the solid grounds, i.e., (d) F .
[ ]
[F ]
. Shown are the structures for (a)
[F ]
, (b)
[F ]
, (c)
[F ]
, and
Fig. 9. A simple structure for the numerical example of the quasi-3-D capacitance determination. (a) Geometrical dimension. (b) Capacitances concerned with the objective line ( C c c c , where c c c c c ).
[ ] = [0
0 ]
+ +
+
need the 2-D solid-ground-based capacitances for the calculation of the capacitances that are associated with the simplified structure (Fig. 4). The 2-D intermediate capacitances for the are schematically shown in Fig. 8. The interstructure mediate capacitances can be determined by using the structures as shown in Fig. 8. That is (8)
(9)
(10)
(11) Note that these capacitances can be readily determined since they are 2-D in structure. Then the filling factors concerned 1 th layer ( and ) can be determined with the by using (6). Finally, the capacitances associated with the objective line can be calculated by combining the intermediate capacitance matrices (i.e.,
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Fig. 10.
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A numerical example for the capacitance determination procedures concerned with the objective line of the structure of Fig. 9.
and ) with the filling factors and ). That is, considering the shielding effects (i.e., matrix associated with the objective line of each layer, the can be determined as follows:
be derived as
(13) (12) Since the matrix of (12) is 3 3, the coupling capacitances in the same layer as the objective line can be extracted by using (12) [i.e., off-diagonal elements of the matrix (12)]. Similarly, the total overlap capacitance and total underlap capacitance can
(14)
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TABLE I THE ACCURACY AND RUN-TIME COMPARISON
Fig. 11. Extracted capacitance variations according to the number of the underlayer conductors (i.e., the filling factor variation).
The self-capacitance can be determined as follows:
(15) For a numerical example, the capacitance determination procedures of the structure of Fig. 9 are described step by step in Fig. 10 (refer to Fig. 1 for each step). The results are compared with the 3-D field-solver-based values in Fig. 11 and are found to have excellent agreement. In addition, capacitances for a more complicated structure, as shown in Fig. 13, are determined. The results also have excellent agreement with a 3-D field-solver (MAXWELL), as shown in Table I. As can be seen in Table I, the computation time of the proposed technique is 26 times faster than that of 3-D-based techniques. Furthermore, the capacitance for the heterogeneous structure can be determined by dividing it into parts whenever the objective line encounters discontinuities such as bend, via, etc. Then the capacitance of the objective line can be derived by summing up all the partial capacitances. IV. APPLICATION OF THE ALGORITHM IN GENERAL STRUCTURE The signal delay and crosstalk for extremely complicated interconnect circuits with shielding layers was evaluated by using the proposed quasi-3-D capacitance extraction method. To show the shielding effect, a test circuit cascaded with various interconnect line cells is defined, as shown in Fig. 12(a). Then the signal delay and crosstalk are investigated for the structure. In Fig. 12(a), the CMOS inverters of size and (W/L) are (W/L) used for both the driver and the receiver. Both the rise time and fall time of an input pulse are assumed to be 0.1 ns. The
Fig. 12. Test circuit model for various interconnect structures. The circuit is cascaded with ten cells composed of interconnect lines. (a) Circuit configuration. (b) Switching conditions.
circuit switching conditions are defined as shown in Fig. 12(b). The capacitance parameters for each cell, i.e., Fig. 13, are determined by using both the proposed quasi-3-D method and the 3-D field-solver. The parameters are summarized in Table I. The circuit performance is investigated by using a general-purpose circuit simulator, HSPICE. The circuit responses of the structure of Fig. 12 are shown in Fig. 14. It is clearly shown that the capacitance variations due to the shielding effect between the lines or between the layers have considerable effects on both the signal delay and crosstalk noise since the neighboring metals modify field patterns (i.e., the coupling capacitances and the self-capacitance) of the objective line. Thus, the 3-D effects of the interconnect lines cannot be neglected for the signal integrity analysis of today’s high-performance VLSI circuits. However, it is not practical to use the conventional 3-D-based methods because of the huge computation time. In contrast, the proposed quasi-3-D technique can be usefully employed for complicated interconnect structures since its computational time is similar to the conventional 2-D capacitance determination, preserving the accuracy similar to the 3-D-based techniques.
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Fig. 13.
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An interconnect structure to investigate the shielding effects of Fig. 12.
tance determination method that can efficiently take the 3-D effect into account was developed. In order to use the quasi-3-D technique, shielding effects and solid-ground-based 2-D capacitance from a given layout geometry were determined. Since the shielding effects and the solid-ground-based capacitance matrices can be readily determined from the layout geometry, the accurate as well as efficient quasi-3-D capacitances associated with an objective line can be readily determined. To demonstrate the method’s efficiency and accuracy, the capacitance parameters and circuit responses were benchmarked with 3-D field-solver-based results. It was shown that the results have excellent agreements with 3-D field solver-based results within about 5% error. Thus, the proposed technique can be usefully employed for the verification of the signal integrity of today’s complicated IC interconnects. ACKNOWLEDGMENT (a)
The authors wish to acknowledge that the CAD tools were provided by IDEC. REFERENCES
(b) Fig. 14. Signal transients for the network using the cell of Fig. 13. (a) The signal transients due to switching case A of Fig. 13. (b) The crosstalk noises due to switching case B of Fig. 13.
V. SUMMARY AND CONCLUSION In this paper, a new capacitance parameter determination method was presented. An inherently complicated IC interconnect structure was simplified by investigating charge distributions within the system. Then a new efficient capaci-
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[13] H.-M. How and C.-S. Sheen, and C.-Y. Wu, “A novel modeling technique for efficiently computing 3-D capacitances of VLSI multilevel interconnections-BFEM,” IEEE Trans. Electron Devices, vol. 45, pp. 200–205, Jan. 1999. [14] V. Veremey and R. Mittra, “A technique for fast calculation of capacitance matrices of interconnect structures,” IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 21, pp. 241–249, Aug. 1998. [15] A. H. Zemanian, R. P. Tewarson, C. P. Ju, and J. F. Jen, “Three-dimensional capacitance computations for VLSI/ULSI interconnections,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 1319–1326, Dec. 1989. [16] K. Nabors, S. Kim, and J. White, “Fast capacitance extraction of general three-dimensional structures,” IEEE Trans. Microwave Theory Tech., vol. 40, pp. 1496–1506, July 1992. [17] J.-H. Chern, J. Huang, L. Arledge, P.-C. Li, and P. Yang, “Multilevel metal capacitance models for CAD design synthesis systems,” IEEE Electron Device Lett., vol. 13, pp. 32–34, Jan. 1992. [18] J. Cong, L. He, A. B. Kahng, D. Noice, N. Shirali, and S. H.-C. Yen, “Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology,” in Proc. 34th Design Automation Conf., 1997, pp. 627–632. [19] N. D. Arora, K. V. Raol, R. Schumann, and L. M. Richardson, “Modeling and extraction of interconnect capacitance for multilayer VLSI circuits,” IEEE Trans. Computer-Aided Design, vol. 15, pp. 58–67, Jan. 1996. [20] U. Choudhury and A. Sangiovanni-Vincentelli, “Automatic generation of analytical models for interconnect capacitances,” IEEE Trans. Computer-Aided Design, vol. 14, pp. 470–480, Apr. 1995. [21] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits. New York: Cambridge Univ. Press, 1998.
Woojin Jin received the B.S. and M.S. degrees in electronic engineering from Hanyang University, Korea, in 1998 and 2000, respectively, where he is currently pursuing the Ph.D. degree. His research interests are in the area of high-speed VLSI circuit design, simulation methodology of solid-state circuits, and integrated circuit packaging.
Yungseon Eo received the B.S. and M.S. degrees in electronic engineering from Hanyang University, Seoul, Korea, in 1983 and 1985, respectively, and the Ph.D. degree in electrical engineering from the University of Florida, Gainesville, in 1993. From 1986 to 1988, he was with the Korea Telecommunication Authority Research Center, Seoul, where he performed telecommunication network planning and software design. From 1993 to 1994, he performed s-parameter-based BJT device characterization and modeling for high-speed circuit design at Applied Micro Circuits Corporation, San Diego, CA. From 1994 to 1995, he was with the Research and Development Center of LSI Logic Corporation, Santa Clara, CA, where he worked in the area of signal integrity characterization and modeling of high-speed CMOS circuits and interconnects. In 1995, he joined the Department of Electrical and Computer Engineering, Hanyang University, Ansan, Korea, where he is now an Associate Professor. His research interests are high-frequency characterization and modeling of integrated circuits and interconnects and high-speed VLSI circuit packaging.
William R. Eisenstadt (S’78–M’84–SM’92) received the B.S., M.S., and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1979, 1981, and 1986, respectively. In 1984, he joined the Faculty of the University of Florida, Gainesville, where he is now an Associate Professor. His research is concerned with highfrequency characterization, simulation, and modeling of integrated circuit devices, packages, and interconnect. In addition, he is interested in large-signal microwave-circuit and analog-circuit design. Dr. Eisenstadt received the NSF Presidential Young Investigator Award in 1985.
Jongin Shim was born in Kangreung, Korea, in 1960. He received the B.S. and M.S. degrees in electronics from Seoul National University, Seoul, Korea, in 1983 and 1985, respectively, and the Ph.D. degree from the Department of Physical Electronics, Tokyo Institute of Technology, Tokyo, Japan, in 1992. His Ph.D. dissertation was mainly concerned with static and dynamic properties of single-mode lasers such as DR distributed Bragg reflector and distributed feedback lasers. From 1985 to 1988, he was with the Electronics and Telecommunications Research Institute (ETRI), Taejon, Korea, where he worked on InGaAsP-InP optoelectronics lasers. In 1992, he joined the Optoelectronics Research Laboratory of NEC, Tsukuba, Japan, where he conducted research on tunability and coherence of semiconductor lasers and their fabrication technology by selective MOVPE growth. He has since joined the Department of Electrical and Computer Engineering, Hanyang University, Ansan, Korea, as an Associate Professor. His primary interests are optoelectronic semiconductor device modeling and optoelectronic packaging. Dr. Shim received a Student Award of Excellence in 1992 from the Tokyo Institute of Technology.
