Gate leakage reduction for scaled devices using ... - Semantic Scholar
716
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
Gate Leakage Reduction for Scaled Devices Using Transistor Stacking Saibal Mukhopadhyay, Student Member, IEEE, Cassondra Neau, Student Member, IEEE, Riza Tamer Cakici, Amit Agarwal, Chris H. Kim, Student Member, IEEE, and Kaushik Roy, Fellow, IEEE
Abstract—In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (Le ) of 25 nm ( oxide thickness = 1 1 nm), 50 nm ( oxide thickness = 1 5 nm) and 90 nm ( oxide thickness = 2 5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are explored for scaled technologies. It is shown that, as the contribution of gate leakage relative to the total leakage increases with technology scaling, traditional techniques become ineffective in reducing overall leakage current in a circuit. A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit. This technique results in 44% savings in total leakage in 50-nm devices compared to the conventional stacking technique. Index Terms—Device simulation, gate direct tunneling, standby-mode, subthreshold leakage, technology scaling, transistor stacking, ultra-thin gate oxide.
I. INTRODUCTION
A
GGRESSIVE scaling of MOS devices requires use of ultra-thin gate oxides to maintain a reasonable shortchannel effect [1]. The International Technology Roadmap for Semiconductors (ITRS) predicts gate-oxide thicknesses of 1.2–1.6 nm for sub-100-nm CMOS [2]. Such thin oxides give rise to high electric fields, resulting in considerable direct tunneling current [3]. For CMOS devices with thicker oxides, the major leakage mechanism is subthreshold current, which increases due to the short channel effect. However, in the ultra-thin gate-oxide regime gate tunneling current between the gate and the source-drain extension (SDE) overlap region, known as edge direct tunneling (EDT) and between the gate and the channel becomes appreciable and dominates the total “off” state leakage current of the transistor [4]. Hence, circuit techniques used to control subthreshold leakage need to be reinvestigated to evaluate their effectiveness in improving the overall leakage current. Although, many researchers have studied the effects of gate tunneling current [5]–[8], very few techniques to reduce gate leakage in a circuit have been reported.
Manuscript received October 17, 2002; revised January 18, 2003. This work is supported in part by the Semiconductor Research Corporation, and in part by the Defense Advanced Research Program Agency, Intel, and IBM. The authors are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-1285 USA (e-mail: sm@ecn. purdue.edu; [email protected]; [email protected]; amita@ecn. purdue.edu; [email protected]; [email protected]). Digital Object Identifier 10.1109/TVLSI.2003.816145
Fig. 1. Direct tunneling of electron.
The “transistor stacking” technique is proven to be extremely effective in lowering subthreshold leakage in the standby-mode of operation of a circuit [9], [10]. In this paper, the effect of gate leakage in a transistor is modeled, the effects on gate leakage of different biasing conditions and variations of the terminal voltages of a device are studied, and the opportunities for overall leakage reduction using transistor stacking are explored. It was observed that as the gate leakage becomes dominant in scaled technologies, the traditional way of using stacking fails to reduce leakage and in the worst case might increase the overall leakage. A novel methodology of transistor stacking is proposed and its effectiveness in reducing the overall leakage in a stack of transistors and in simple logic gates is analyzed. II. GATE DIRECT TUNNELING Gate direct tunneling current is due to the tunneling of an electron (or hole) from the bulk silicon through the gate-oxide potential barrier into the gate [3]. Fig. 1 explains the direct poly-silicon gate and a tunneling phenomenon between an p-type substrate (when a positive gate bias is applied). In Fig. 1, is the height of the oxide potential barrier, is the potenand are the electron tial drop across the gate oxide, quasi-Fermi levels in the substrate and the poly-silicon, respecand are the conduction band edges in the subtively, strate and the poly-silicon, respectively. There are three major mechanisms for direct tunneling in MOS devices: 1) electrons tunneling from the conduction band of the substrate to the conduction band of the gate (or vice versa) known as the conduction band electron tunneling (CBET); 2) electrons tunneling from the valence band of the substrate to the conduction band of the gate (with generation of free holes in the substrate) known as the valence band electron tunneling (VBET); and 3) holes tunneling from the valence band of the substrate to the valence band of the
1063-8210/03$17.00 © 2003 IEEE
MUKHOPADHYAY et al.: GATE LEAKAGE REDUCTION FOR SCALED DEVICES USING TRANSISTOR STACKING
(a)
717
(b)
Fig. 2. Variation of tunneling current density with potential drop across oxide. (a) In different oxide thickness and (b) in a single oxide thickness.
Fig. 3.
Components of tunneling current [7].
gate (or vice versa) known as the valence band hole tunneling (VBHT) [7] (see Fig. 1). Direct tunneling is modeled as [5]
(1)
is the direct tunneling current density, is the where is the barrier height for potential drop across the thin oxide, is the oxide the tunneling particle (electron or hole), and thickness. A and B are physical parameters given by [5] and where is the effective mass of the tunneling particle, is the electronic charge, and is the reduced Plank’s constant [5]. Fig. 2 shows the variation of tunneling current density with based on (1). The tunneling current increases exponentially with a decrease in the oxide thickness. It depends on both the device structure and the biasing condition [8]. Fig. 3 describes the various components of gate tunneling in a scaled nMOSFET device [7]: 1) EDT components between the gate and the SDE region and ); (
2) gate-to-channel current , part of which goes to the and the rest goes to the drain ; source . 3) gate-to-substrate leakage current EDT is more significant when the device is in accumulation , where, is the flatband (i.e., for NMOS voltage). however, the gate-to-channel current is dominant for [8]. Considering the tunneling currents collected at the can be divided into three major electrodes, the gate current components: ; 1) gate-to-source ; 2) gate-to-drain . 3) gate-to-substrate (if is high) or Depending on the biasing condition, (if is high) dominates the total gate leakage current. The different direct tunneling mechanisms described in Fig. 1 are dominant or important in different regions of operations of NMOS and PMOS devices as shown in Table I [7]. Mechanisms governing the gate tunneling current in NMOS are CBET and VBET. CBET controls the gate-to-channel current. The gate to body current is controlled by CBET in accumulation and VBET in the depletion-inversion region of operation. In PMOS, VBHT dominates the gate-to-channel direct tunneling current, whereas the gate-to-body tunneling is controlled by CBET in accumulation and by VBET in the depletion-inversion region. Edge direct tunneling is governed by CBET under all bias conditions [7]. Since the barrier height for VBHT (4.5 eV) is considerably higher than the barrier height for CBET (3.1 eV), the tunneling current associated with VBHT is much less than the current associated with CBET. This results in lower gate leakage current in PMOS than NMOS [11]. Because direct tunneling leakage is significantly larger in NMOS than in PMOS, efforts to reduce gate leakage focus on NMOS gate leakage. III. STANDBY LEAKAGE CONTROL USING TRANSISTOR STACK (SELF-REVERSE BIAS) The leakage current flowing through a stack of series connected transistors depends on the number of “off” transistors in
718
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
TABLE I DOMINANT MECHANISMS FOR CURRENT COMPONENTS IN NMOS AND PMOS AT DIFFERENT REGION OF OPERATIONS. EDGE DIRECT TUNNELING AND I ) ARE ALWAYS DOMINATED BY CBET (I
an increase in the body effect (negative ), and a reduction in (less DIBL) reduce the subthreshold current exponentially. To analyze the effect of transistor stacking on the gate current, the variation of gate current with source voltage is investigated based on the gate current model in (1) for gate to channel ( and ) tunneling and EDT ( and ). From (1) and Fig. 2, tunneling current increases with an increase in the voltage drop . can be defined by the following across the gate oxide equations in different regions: a) channel region (3a) b) gate-source overlap region (3b) c) gate-to-drain overlap region Fig. 4. Two-input NAND gate. Turning “off” M1 and M2 raises V value causing the “stacking effect” [9].
to positive
the stack. In the two-input NAND gate shown in Fig. 4, turning and raises the intermediate node voltage “off” both to a positive value due to a small drain current [9]. Positive potential at the intermediate node has three effects: becomes negative; 1) gate-to-source voltage of M1 of causes 2) negative body-to-source potential more body effect; of decreases, re3) drain-to-source potential sulting in less drain-induced barrier lowering (DIBL). This phenomenon is known as the “stacking effect.” From the BSIM2 MOS transistor model [12], subthreshold current flowing through “off” transistor is given by (2) . , and are where the gate-to source, the drain-to-source, and the bulk-to-source voltages, respectively. The bulk is connected to ground. and are the body effect and DIBL coefficients, respectively. is the zero-bias threshold voltage. is the gate-oxide capacis the zero-bias mobility, and is the subthreshold itance. , swing coefficient. From (2) it is observed that a negative
(3c) is the gate-to-source voltage, is the gate-to-drain where is the surface potential, and is the potential voltage, and drop across the poly-silicon depletion region. are the flat-band voltages in the channel (between n -poly and V ) and in the SDE (between n -poly and p substrate source drain V). With the gate voltage at “ ”, n “ ”, an increase the gate current is dominated by EDT. At increases . From (1) and (3b), an in the source voltage results in an increase in the tunneling through increase in the gate-to-source overlap region. Hence, the total gate current “ ”, an increase in reduces increases. However, with . The reduction the gate-to-source tunneling by reducing also reduces the gate-to-channel tunneling. In addition, in “ ” with a high drain voltage , is also high. at results in an increase in From (1) and (3c) an increase in the tunneling in the gate-drain overlap region, resulting in an increase in the gate current. A. Modeling Total Leakage in a Transistor Stack In order to evaluate the effect of stacking on the leakage reduction, it is necessary to model leakage current through a stack of transistors. Modeling the total leakage through a stack of transistors is possible by solving Kirchoff’s current law (KCL) at
MUKHOPADHYAY et al.: GATE LEAKAGE REDUCTION FOR SCALED DEVICES USING TRANSISTOR STACKING
719
the ground (either though the gate or through the transistor in a previous stage that drives that gate). Techniques for the selection of proper input vectors (“input vector control”) and for the addition of an extra series connected transistor (“forced stacking”) are investigated to evaluate their effectiveness in reducing the overall leakage for scaled technologies. B. Leakage Control Using Transistor Stack
Fig. 5. Current distribution at the intermediate node of a two-transistor stack. The direction of currents shown is taken as the default directions in the model.
each intermediate node of the stack. The current equation at the intermediate node in Fig. 4 is given by (4) is the drain-to-source current. Depending on the where is governed by the region of operation of the transistor, drain-to-source current equation in subthreshold region, the linear region, or the saturation region. Default directions of , , , and are taken as shown in Fig. 5. currents Different components of the gate current are calculated using (3) and the BSIM4 model of the gate currents [7]. A numerical intermediate solver is used to solve the simultaneous node equations with different input vectors for the “off” state of in a stack an n-transistor stack. The total gate current of n transistors is calculated using following definition:
(5) is the gate current through the kth transistor (default where direction is flowing into the gate as shown in Fig. 5). The total leakage is modeled by adding all of the currents going to the ground (or by adding all of the currents coming out of supply ). Using this definition the total leakage through a stack of transistor is calculated using following equation:
1) Input Vector Control: Due to the stacking effect, leakage through a logic gate depends on the applied input vector. To evaluate the effect of input vector selection in controlling leakage, the pull-down network of the two-input NAND gate (a two-transistor stack) in Fig. 4 is considered under all input conditions for which the output is high (gate is “off”). Those “ ”, “ '' “ ”), ( “ ”, conditions are ( “ ” “ ”) and ( “ ”, “ ” “ ”). With both of the gates at logic “0”, the intermediate node voltage is positive, resulting in a negative value of . This reduces the subthreshold current in M1. With all other input of M1 and M2 are either positive or zero. Thus, vectors, “00” gives the minimum subthreshold current flowing through a stack of two transistors. It has been shown that subthreshold current flowing through a stack of transistor decreases with an increase in the number of the “off” transistors. Hence, the “input vector control” technique can be effective in reducing the total subthreshold leakage of a circuit in the standby-mode of operation [13]. However, the input vectors have a different effect on the gate leakage than the subthreshold leakage. Since EDT dominates the gate current of a transistor with the gate at “0”, the gate current of the transistors in Fig. 4 with input “00” is given by
(7) is the width and is the length of SDE region where , of the transistor. With “00” as the input vector, , and . Since is small , is the dominant component of the total compared to gate current (Fig. 6). Hence, the total gate current can be written as
(6) is the source current of the th transistor and is the where gate voltage of the th transistor ( “0” or “1”). If gate is at “0” , current is flowing out of gate (i.e., the direction is the reverse of its default direction in Fig. 5) and into of
(8)
720
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
Fig. 6. Two-transistor stack with input vector “00” and “10”.
With the gate at “1” gate-to-channel tunneling is the major component of gate tunneling and the total gate current is given by
Fig. 7. Variation of gate current in a two-transistor stack with input vector in different gate leakage to total leakage ratio. “10” is the minimum gate current vector.
(9)
in ((1) and Fig. 2). From (8) and (11), the total gate current in a stack with input “10” is less than that with input “00” since reduces the tunneling current (Fig. 2). a decrease in The total leakage given by (6) depends on both gate current and subthreshold current. With input state “00”, the total leakage is
is the gate-to-channel current and is the where and are controlled by gate-to-bulk component. in the channel. With “01” as input vector , , and . Since both and are at , , , and are high, resulting in high total gate current. The input state “10” is of the intermediate voltage particular interest. With , where is the threshold voltage of the top rises to transistor (modulated by the body effect and DIBL). Under this , , and condition . This results in to be negligible. Therefore, the total gate current can be expressed as (10) is much less than , Since (Fig. 6). With the the dominant component is difference between the valence band edge at the substrate-oxide interface and the conduction band edge at the polysilicon-oxide interface is very small. Consequently, the VBET from the valence band of the substrate to the conduction band of the polysilvery small compared to the icon is negligible. This makes is other components since the major mechanism resulting in VBET (Table I). Hence, the total gate current is given by
(11)
, whereas with “00” With “10” as the input . Hence, the gate-to-source as the input and gate-to-channel currents of M1 overlap with “10” are higher than and with “00”. However, this increase is much less than the decrease in gate-to-drain tunneling in M2 with “10” from the gate-to-drain tunneling in M1 . This is due to the fact that the rate of with “00” change of tunneling current density increases with an increase
(12) is the subthreshold current and is where the gate-to-drain overlap current of the top transistor with “00” as the input vector. With “10”as the input state, the total leakage is (13) is the subthreshold current and is where the gate-drain overlap current of the bottom transistor with “10” as input. Hence, the change in the total leakage from input state ) is given by of “00” to “10” (
(14) is less than , whereas is greater . Hence, the minimum leakage condition dethan pends on the ratio of gate leakage to subthreshold leakage. For larger devices with thicker gate oxides where subthreshold current dominates over gate leakage, the input vector with all zeros gives the minimum subthreshold current and, therefore, the minimum overall leakage. However, with the decrease in oxide thickness with device scaling, gate leakage can become a dominant component of leakage. Hence, turning on the top transistor will give the minimum leakage condition in scaled devices. To evaluate the correctness of the model, a two-transistor stack was solved using the numerical solver for 70-nm nMOS transistors provided by BPTM [14] with oxide thicknesses of 1.2, 1.4, and 1.6 nm. The decrease in oxide thickness resulted in an increase in the gate leakage to total leakage ratio (0.95, 0.68, and nm, respectively). Figs. 7 and 0.25 for and 8 show the variation of gate current and total leakage with
MUKHOPADHYAY et al.: GATE LEAKAGE REDUCTION FOR SCALED DEVICES USING TRANSISTOR STACKING
Fig. 8. Variation of total leakage current in a two-transistor stack with input vector in different gate leakage to total leakage ratio. The “00” is the lowest leakage for lower gate leakage to total leakage ratio but with increased ratio “10” is the best case.
different input vectors for different gate leakage to total leakage ratios. As predicted from the model, the application of “10” produces the minimum gate current in all cases. However, the total leakage is minimized with the input condition “00” in the case where the ratio is least. With an increase in the contribution of the gate leakage relative to the total leakage, the input condition “10” provides the lowest total leakage. Modeling the total leakage in a stack of transistors shows that “input vector control” can be very effective in controlling the overall leakage in the standby-mode of operation. However, the optimal input vector changes with technology generation. The described model provides a new method of input vector selection based on the contributions of the gate current and the subthreshold current to the total leakage. In devices where the subthreshold current is more significant, the input vector should be chosen to maximize the number of the “off” transistors in the stack. However, in scaled devices with more gate current, turning “on” the top transistor in the stack results in the minimum gate current and the minimum overall leakage through the stack. 2) Forced Stacking: “Input vector control” takes advantage of the transistor stacks inherently present in logic design to minimize leakage. Further leakage reduction can be achieved by adding more stacking transistors although this additional leakage savings is accompanied by an area penalty. The technique of inserting an extra series connected transistor in the pull-down path of a gate and turning it “off” in the standby-mode of operation is known as “forced stacking” [15]. During regular mode of operation, the extra transistor is turned on. Forced stacking can provide additional savings in leakage current during standby mode of operation. When the extra transistor is turned “off”, the intermediate source voltage increases, as described earlier. This results in a decrease in the subthreshold current through the top transistor. Hence, the total subthreshold leakage through a two-transistor stack is reduced. It has been shown that the subthreshold leakage of a two-transistor stack is an order of magnitude less than the leakage in a single transistor [10]. However, an increase in the source voltage increases the gate leakage of the top transistor. Hence, the total gate leakage through the stack increases. Using the model of total leakage described in (6),
721
(a)
(b) Fig. 9. Effectiveness of forced stacking in saving overall leakage. (a) Normal forced stacking. (b) New forced stacking. Normal forced stacking does not have significant effect in devices with more gate current contribution. New forced stacking is more effective in leakage saving in all devices with considerable gate current.
the total leakage through a single transistor is given by two-transistor stack
and a (15) (16)
and are the subthreshold current of a single where and transistor and a two-transistor stack, respectively. are almost zero in both cases since . and remain the same since in both cases . Therefore, the change in the total leakage is given by
(17) In devices where the subthreshold leakage is large compared to the gate leakage, the reduction in the subthreshold leakage offsets the increase in the gate leakage considerably, thereby producing the overall leakage improvement with “forced stacking”. However, in scaled devices with a considerably larger gate leakage contribution, the saving in the subthreshold leakage does not have a strong effect on the overall leakage. Hence, the technique fails to provide significant leakage reduction [see Fig. 9(a)].
722
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
(a)
(b)
(c) Fig. 10.
I
0V
characteristics of the transistors. (a) L
= 25 nm. (b) L
A new technique of forced stacking is proposed where, along with turning “off” the extra transistor, the gate of the top tranin sistor is raised to “1” in the standby mode. This reduces a two-transistor stack. As described earlier, the increase in and is much less than the reduction in . Hence, (17) changes to
= 50 nm. (c) L
= 90 nm.
simulator MEDICI [17]. To model the effect of direct tunneling in NMOS, the tunneling mechanisms CBET and VBET were considered in MEDICI. The net direct tunneling current was calculated using the independent electron approximation and for CBET it is given by [17]
(19) (18) is large compared to In devices with high gate leakage, and . Hence, this results in significant savings in total leakage. Fig. 9(b) shows the variation of total leakage with an increase in the transistor stack length based on the model described above. Significant reduction in total leakage is observed with an increase in the stack length. IV. DEVICE SIMULATIONS WITH DIRECT TUNNELING A. Gate Current Model To observe the effect of gate direct tunneling in the behavior of a transistor, NMOS transistors were designed based on the doping profiles given in [16] and the design guidelines given in the 2001 ITRS Roadmap [2] for effective gate lengths of 90, 50, and 25 nm. The devices were simulated using the device
where the integral is over the vertical kinetic energy, E, of the , , and are the electron quasiincident electrons. Fermi level, the conduction band edge, and the electron effective tunneling mass, respectively, in silicon region at the insuand are the corresponding electron lator interface. quasi-Fermi level and conduction band edge in poly-silicon region. The endpoint of the integration is determined by the bar. The electron charge is given by q, his Planck’s rier height, is the thermal energy. TC is the tunneling coconstant, and efficient of an electron with energy E. For VBET, (19) is computed for electrons in both the heavy and light hole bands with replaced by , the valence band in silicon region; replaced by , the hole quasi-Fermi level in region 1; and the tunneling masses in silicon region are set by the light and heavy hole effective masses [17]. The tunneling coefficient was
MUKHOPADHYAY et al.: GATE LEAKAGE REDUCTION FOR SCALED DEVICES USING TRANSISTOR STACKING
(a)
723
(b)
(c) Fig. 11. Variation of gate current with gate voltage. V (c) L = 90 nm, V = 1:2 V .
=V ,V
= 0, V
calculated using the Gundlach method for the exact tunneling coefficient of a trapezoidal barrier described in [17]. Quantum mechanical effects in the inversion layer and band-to-band tunneling were included in the device model. B.
–
Characteristics of the Transistor
– characteristics for the Fig.10(a)–(c) shows the 25-, 50-, and 90-nm devices, respectively. It was observed that in scaled technologies, the gate direct tunneling coupled with the subthreshold current, increases the overall “off” current of the devices. However, high for nm for nm for nm ratios indicate reasonable transistor characteristics. At a high , a large increase in occurs for drain bias smaller devices due to increases in drain-to-gate leakage current and band-to-band tunneling at the reverse biased n drain and p-substrate junction. C. Simulation of Gate Tunneling Current Fig. 11(a)-(c) shows the variation of gate current with gate voltage for 25-, 50-, and 90-nm devices, respectively, for different oxide thicknesses. In all cases the drain-to-source
= 0; (a) L
= 25 nm, V
= 0:7 V , (b) L
= 50 nm, V
= 1 :0 V ,
voltage was kept at for the corresponding technology [2] . As the gate voltage and the gate bias was varied from 0 to , starts decreasing since is increased from 0 to decreases. On the other hand an increase in cause and to increase. It was observed that, with a decrease in the oxide thickness for a particular technology, gate current increases exponentially. Large increases in gate current are observed as the technology is scaled down. Fig. 12 shows the ratio of gate leakage to overall leakage for the “off” state of the devices . The ratio increases as the oxide thickness is with scaled down. However, it was observed that the ratio decreases as we go down to 25-nm devices from 50-nm devices. This is due to the increase in the band-to-band tunneling (BTBT) current at the reverse bias drain n -substrate (p) junction, resulting in high substrate current. An increase in BTBT causes the total leakage to increase resulting in a decrease in the gate leakage to the total leakage ratio. In smaller technologies, BTBT current is expected to be a major leakage component due to the increased doping concentration of the substrate, the application of halo doping to reduce short channel effects, and an increased abruptness of the doping profile [3]. However, if double gate MOSFETS are used, significant BTBT leakage will not be present.
724
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
Fig. 12. Ratio of gate leakage to overall leakage in different technology generation. Ratio increases with decrease in oxide thickness in a generation. Ratio increases from 90 to 50 nm are due to increase in gate current. However, decreases from 50 to 25 nm are due to increase in BTBT.
(a)
(b)
(a)
(b) Variation of gate current with source voltage (Le = 50 nm) with ,V = 0 and (a) V = 0, (b) V = 1. With V = 0, gate current increases with increase in source voltage. However, with V =1 it decrases with source voltage. Fig. 13.
V
=V
D. Effect of Source Bias on Gate Current In order to estimate the effect of transistor stacking on gate tunneling current, the variation of gate current with an increase was simulated for NMOS transistors. It in the source bias
Fig. 14. Variation of: (a) gate current and (b) total leakage with source voltage for L = 25; ; 50; and 90 nm. For the 90-nm device, overall leakage decreases with source voltage. However, the effect is reverse for scaled devices. (V =V ,V = 0 and V = 0).
was observed that for a low gate bias “ ” , increasing the source bias increases , thereby increasing the overall gate , leakage [see Fig. 13(a)]. This is due to the fact that, for and dominate the overall leakage current [8]. With increases due to an increase an increase in source bias, (the difference between the conduction band edge at in the SDE and the poly-silicon increases causing the potential at the SDE to increase), thereby indrop across oxide creasing . CBET from the gate to the channel also increases level at the surface ( due to the increase in the also increases), resulting in increases in ( and ) and . An increase in the gate leakage with an increase in the source voltage is the reverse of the effect of increasing the source voltage on the subthreshold leakage. On the other hand, having makes the gate current to go down with the increase in [see Fig. 13(b)]. the source voltage due to the reduction of With an increase in , the conduction band edge at the surface and ( goes down, decreasing the difference between at the channel reduces). also goes down and eventually . Hence, CBET decreases, causing ( and goes below ) to reduce. An increase in causes at the channel to and . go down reducing the difference between also goes down decreasing . Hence, VBET de. Higher also reduces the differcreases thereby reducing
MUKHOPADHYAY et al.: GATE LEAKAGE REDUCTION FOR SCALED DEVICES USING TRANSISTOR STACKING
Fig. 15.
Three-transistor stack.
Fig. 16. Variation of subthreshold current with input vector for a stack of 2T transistors, not including modeling of gate leakage. “00” is the lowest leakage vector.
ence between and at the SDE region ( at the SDE decreases. It was observed that, for region reduces). Hence, 90-nm devices, overall leakage reduces with positive source bias in an “off” transistor due to the reduction in subthreshold current. However, for 25- and 50-nm devices with larger gate current, the total leakage increases with an increase in source bias (Fig. 14). V. VERIFICATION WITH DEVICE SIMULATION The “pull-down” networks of stacks of NMOS transistors were simulated for 90-, 50-, and 25-nm devices with oxide thickness of 2.5, 1.5, and 1.1 nm, respectively, in MEDICI at room K to verify the trends predicted by the temperature analytical model derived in Section III regarding total leakage in a transistor stack. The “Input Vector Control” and “Forced Stacking” techniques were investigated based on the simulation results, to evaluate their effectiveness in saving overall leakage in different technology generations. A. “Transistor Stack” Pull-Down Network 1) Input Vector Control: Two and three transistor stacks with different input vectors were simulated to observe the effect of input vector selection on overall leakage reduction. Fig. 15 of a “pull-down” netshows a normal “off” state work of three-transistor stack with input vector “100” ( “ ”, “ ”, “ ”). As described in Section III, with an increase in number of “off” transistors, the subthreshold leakage flowing through the stack reduces. The simulation
725
Fig. 17. Variation of subthreshold current with input vector for a stack of three transistors, not including modeling of gate leakage. “000” is the lowest leakage vector.
shows that “00” and “000” are lowest leakage input vectors (ignoring gate current) for the two and three transistor stacks respectively, with savings of over 70% compared to the worst cases (input vector “01” and “011”) for 50-nm devices (Figs. 16 and 17). Table II shows the savings in the subthreshold leakage with application of different input vectors based on the MEDICI simulation results. Simulations of transistor stacks including the gate direct tunneling current model show that application of the input vectors “10” and “100” results in the minimum total gate current in a stack of two and three transistors, respectively for 25-, 50-, and 90-nm devices (see Figs. 18 and 19). This conforms to the trend obtained from the analytical model (see (8) and (11) in Section III and Fig. 7). Simulation of the two-transistor stack verifies the prediction that with input “00”, the dominant component of current of top tranthe gate current is the gate-to-drain sistor whereas with “10” as the input, the gate-to-drain current is dominant. For example, simuof the bottom transistor nA m lating 50-nm devices, it is observed that, is approximately 97% of the total gate leakage current. Howis reduced to nearly zero and ever, with “10” as input, nA m is the dominant component (87% of total with “10” input state is considerably less than gate current). with “00” (57% in 50-nm devices), because with is much less than with “00” . “10” increases from input state “00” to input state “10” (from 0.1 to 0.69 nA m in 50-nm device). However, the contriburelative to total leakage is less in both cases (1.2% tion of with “00” and 12.8% with “10” for 50-nm device). Hence, the application of “10” results in lower gate leakage than “00” (37% saving in 50-nm devices). This verifies the prediction made in Section III. Table III gives the percentage savings in total gate current for two- and three-transistor stacks with different input vectors for 25-, 50-, and 90-nm devices. Figs. 20 and 21 show the variation of overall leakage with different input vectors for 25-, 50-, and 90-nm devices in twoand three-transistor stacks, respectively, based on the simulation results. It was observed that for 90-nm devices, where the contribution of subhreshold leakage is much greater than that of gate leakage, “00” and “000” are the lowest leakage input vectors, reducing 62% and 77% of the total leakage from worst cases, respectively. However, “10” and “100” are the best-input vectors for 25- and 50-nm devices, where the contribution of gate
726
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
TABLE II PERCENTAGE SAVINGS IN SUB-THRESHOLD LEAKAGE IN TRANSISTOR STACK WITH DIFFERENT INPUT VECTOR WITHOUT GATE TUNNELING EFFECT
Fig. 18. Variation of gate tunneling current with input vector for two-transistor stack. “10” is the minimum gate current vector.
Fig. 20. Variation of total standby power for two-transistor stack. The “00” is the lowest leakage for 90-nm node but with increased gate tunneling current “10” is the best case in 25- and 50-nm devices.
Fig. 21. Variation of total standby power for three-transistor stack. “000” is the best case in 90-nm case but “100” is the lowest leakage power case in 25and 50-nm devices. Fig. 19. Variation of gate tunneling current with input vector for three-transistor stack. “100” is minimum condition.
leakage is greater. This verifies the trends predicted by the analytical model [see (14)] in Section III and Fig. 8. Table IV shows the percentage savings in overall leakage for these three technology generations. Leakage saving using “10” and “100” over “00” and “000” is 42% and 44% for 50-nm devices, whereas it is 36% and 37% for 25-nm devices. This decrease in leakage savings is caused by an increase in BTBT current resulting in an increase in overall leakage. BTBT increases with increased . In Fig. 6, reverse bias across the drain–substrate junction for M1 (top transistor) is and with “00” as the input, for M2 (bottom transistor) is almost zero. However, with of M2 increases to resulting “10” as the input,
in an increase in BTBT leakage in M2. This results in an increase in total leakage. Hence, the overall leakage savings using “10” (or “100”) reduces from 50-nm devices. Table V summarizes the minimum, maximum and average leakage (averaged over all input vectors for which the stack is “off”) of two- and three-transistor stacks for 25-, 50-, and 90-nm devices. 2) Forced Stacking Technique: Simulation of a stack of NMOS transistors, neglecting the gate direct tunneling current, shows that subthreshold leakage reduces with an increase in the number of transistor (or “length”) in the stack for all devices (Fig. 22). Increasing the length of a stack from 1 to 2 saves the subthreshold current by 78%, 70%, and 61% for 25-, 50-, and 90-nm devices, respectively. Simulation of transistor stacks including gate current shows that gate leakage
MUKHOPADHYAY et al.: GATE LEAKAGE REDUCTION FOR SCALED DEVICES USING TRANSISTOR STACKING
727
TABLE III PERCENTAGE SAVINGS IN TOTAL GATE CURRENT ((5)) IN TRANSISTOR STACK WITH DIFFERENT INPUT VECTOR
TABLE IV PERCENTAGE SAVINGS IN OVERALL LEAKAGE IN TRANSISTOR STACK WITH DIFFERENT INPUT VECTOR
MINIMUM, MAXIMUM
AND
TABLE V AVERAGE LEAKAGE IN TWO-TRANSISTOR STACK, THREE-TRANSISTOR STACK DIFFERENT TECHNOLOGY GENERATIONS
increases with an increase in the stack length for all devices (Fig. 23). It is observed that in 90-nm devices, due to the small contribution of gate leakage, total leakage decreases with an increase in stack length. For 50- and 25-nm devices, where the contribution of gate leakage is large, forced stacking does not have a significant effect on total leakage (Fig. 23). This follows the same trend predicted by the analytical equations in Section III [see Fig. 9(a)]. Simulation of transistor stacks with the new forced stacking method, described in Section III, shows that, overall leakage for 25- and 50-nm devices reduces with increase in stack length (Fig. 24). The addition of an extra transistor and keeping the gate of the top transistor at “1” saves 35% and 46% of leakage
AND AND-OR
NETWORK
FOR
in 25- and 50-nm devices, respectively. This verifies the result predicted by the analytical model in Section III [see Fig. 9(b)]. B.
AND-OR
Pull-Down Network
In order to evaluate the effect of gate leakage on more complex logic gates, a three-input AND-OR pull-down network was simulated for 25-, 50-, and 90-nm devices. The logic “A AND (B OR C)” can be implemented using the configurations shown in Fig. 25, namely, with parallel transistors implementing “B OR C” (MB and MC) connected to (single transistor implementing “A” (MA) connected to ground) and with parallel transistors MB and MC connected to ground (MA connected to
728
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
Fig. 22. Leakage saving by forced stacking, not including the effect of gate tunneling current in the model. stacking is saving overall leakage by over 61% in 90 nm, 70% in 50 nm, and 78% in 25 nm.
Fig. 23. Leakage saving by forced stacking in the presence of gate tunneling current. The forced stacking is saving overall leakage in 90-nm node where gate leakage is less. With more gate leakage the effectiveness is absent.
Fig. 24. Leakage saving by new forced stacking. Application of “1” at the gate of top transistor saves overall leakage by 35% in 25 nm and 46% in 50-nm node.
). Both configurations were simulated for the input condi, tions for which the network is in the “off” state, namely ( , ), ( , , ), ( , , or , , ) and ( , , ). The overall leakage of the network for the 25-, 50-, and 90–nm devices are shown in Fig. 26. In 90-nm devices, where , , ) subhreshold leakage is dominant, input ( , gives the minimum leakage with MB and MC connected to condition (76% savings compared to worst case). For 50-nm de, , ) with MB and MC convices, input (
Fig. 25.
AND-OR
pull-down network.
nected to , results in minimum overall leakage with 85% and , reduces savings from the worst case. Having the dominant drain-to-gate current of both of the parallel tran, sistors MB and MC. For 25-nm devices, application of ( , ) as the input with MB and MC connected to provides a 60% savings compared to the worst case. Table V summarizes the minimum, maximum and average leakage of the AND-OR pull down network for 25-, 50-, and 90-nm devices.
MUKHOPADHYAY et al.: GATE LEAKAGE REDUCTION FOR SCALED DEVICES USING TRANSISTOR STACKING
729
Fig. 26. Overall leakage in AND-OR pull-down network. For 90-nm devices “000” with parallel transistors at the top gives minimum leakage. However, for 50 nm and 25-nm devices parallel transistors on top with “1” at gate of both of them gives minimum overall leakage.
(a) Fig. 27.
Variation of gate leakage and subthreshold leakage with temperature.
VI. EFFECT OF TEMPERATURE ON SUBTHRESHOLD LEAKAGE AND GATE LEAKAGE The basic physical mechanisms governing subthreshold and gate leakage have different temperature dependencies. Subthreshold current is governed by the carrier diffusion which increases with an increase in temperature. Subthreshold current increases exponentially with temperature due to: 1) the reduction in threshold voltage and 2) an increase in thermal . Gate tunneling current is almost insensitive voltage to temperature since the electric field across the oxide and the tunneling probability of an electron do not strongly depend on temperature. Hence, at elevated temperature subthreshold current dominates over gate leakage. Fig. 27 shows the variation of the total gate current and the subthreshold current nm and with the temperature for a device with nm. At K the gate current is considerably higher than the subthreshold current. However, at an elevated K) the subthreshold current dominates temperature ( the gate current. Hence, based on the model developed in the Section III, the input vector that minimizes the subthreshold leakage is more effective in reducing the overall leakage at elevated temperature. Fig. 28 shows the subthreshold, gate and total leakage in a two-transistor stack with different input vecK) and high ( K) temperature tors at room ( based on the model developed in Section III. It is observed that at for 25- and 50-nm devices at room temperature “10” is the minimum leakage vector. At an elevated temperature
(b) Fig. 28. Variation of gate and subthreshold leakage with input vector at diferent temperature. (a) Room temperature (T = 300 K). (b) Elevated temperature (t = 400 K). At room temperature, for 25- and 50-nm devices “10” is the best input vector. However, at elevated temperature, due to higher subthreshold leakage “00” is the minimum leakage vector in 25 and 50 nm.
( K), due to higher subthreshold leakage, application of “00” results in the minimum leakage. However, stacking is used mostly to reduce the total leakage in the standby-mode of operations. In standby-mode, the operating temperature is near room temperature where gate leakage is dominant in scaled technologies. VII. CONCLUSION It is demonstrated that with technology scaling the contribution of gate leakage and subthreshold leakage relative to the total leakage in an “off” transistor varies. The effect of gate leakage in a device and circuit is modeled using simple equations and we investigated the opportunities for reducing gate leakage using
730
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
device simulations. It is observed that as the gate leakage becomes a significant component of total leakage, the traditional stacking technique to reduce subthreshold leakage fails to minimize the overall leakage in a circuit. A methodology of input vector selection based on the ratio of gate-leakage to the subthreshold leakage is proposed for reducing the overall leakage of a circuit in the standby-mode of operation. The analysis was verified using device simulations on transistor stacks. REFERENCES [1] K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design. New York: Wiley, 2000, ch. 5, pp. 224–226. [2] (2001) International Technology Roadmap for Semiconductors, 2001 Edition. Semiconductor Industry Assoc. [Online]. Available: http://public.itrs.net/Files/2001ITRS/Home.htm [3] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998, ch. 2, pp. 94–97. [4] N. Yang, W. K. Henson, and J. Wortman, “A comparative study of gate direct tunneling and drain leakage currents in N-MOSFETs with sub-2100-nm gate oxides,” IEEE Trans. Electron Devices, vol. 47, pp. 1636–1644, Aug. 2000. [5] K. Schuegraf and C. Hu, “Hole injection SiO breakdown model for very low voltage lifetime extrapolation,” IEEE Trans. Electron Devices, vol. 41, pp. 761–767, May 1994. [6] N. Yang, W. Henson, and J. Hauser, “Modeling study of ultrathin gate oxides using tunneling current and capacitance-voltage measurement in MOS devices,” IEEE Trans. Electron Devices, vol. 46, pp. 1464–1471, July 1999. [7] K. Cao, W.-C. Lee, W. Liu, X. Jin, P. Su, S. Fung, J. An, B. Yu, and C. Hu, “BSIM4 gate leakage model including source drain partition,” in IEDM Tech. Dig., 2000, pp. 815–818. [8] C. Choi, K. Nam, Z. Yu, and R. W Dutton, “Impact of gate direct tunneling current on circuit performance: a simulation study,” IEEE Trans. Electron Devices, vol. 48, pp. 2823–2829, Dec. 2001. [9] V. De et al., “Techniques for leakage power reduction,” in Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. J. Bowhill, and F. Fox, Eds. Piscataway, NJ: IEEE Press, 2001, ch. 3, pp. 52–55. [10] Y. Ye, S. Borkar, and V. De, “New technique for standby leakage reduction in high-performance circuits,” in Symp. VLSI Circuits Dig. Tech.Papers , 1998, pp. 40–41. [11] F. Hamzaoglu and M. Stan, “Circuit-level techniques to control gate leakage for sub-100 nm CMOS,” in Proc. Int. Symp. Low Power Design, Aug. 2002, pp. 60–63. [12] B. J. Sheu, D. L. Scharfetter, P. Ko, and M. Jeng, “BSIM: Berkeley short-channel IGFET model for MOS transistors,” IEEE J. Solid-State Circuits, vol. 22, pp. 558–566, Aug. 1987. [13] Z. Chen, L. Wei, A. Keshavarzi, and K. Roy, “IDDQ testing for deep submicron ICs: challenges and solutions,” IEEE Design Test. Comput., pp. 24–33, Mar.–Apr. 2002. [14] Berkeley Predictive Technology Model (BPTM). Device Group, Univ. California at Berkeley. [Online] Available: http://www-device.eecs.berkeley.edu/~ptm/ [15] M. C. Johnson, D. Somasekhar, and K. Roy, “Leakage control with efficient use of transistor stacks in single threshold CMOS,” in Proc. ACM/IEEE Design Automation Conf., 1999, pp. 442–445. [16] Well-Tempered, Bulk-Si NMOSFET Device Home Page. Microsystems Technology Laboratory, MIT. [Online] Available: http://www-mtl.mit.edu/Well/ [17] MEDICI: Two-Dimensional Semiconductor Device Simulation Program, AVANT! Corp., Fremont, CA, 2000.
Saibal Mukhopadhyay (S’99) was born in Calcutta, India. He received the B.E. degree in electronics and telecommunication electrical engineering from the Jadavpur University, Calcutta, India, in 2000, and the M.S. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in 2001. He is currently working toward the Ph.D. degree at Purdue University.
Cassondra Neau (S’00) received the B.S.E. degree in electrical engineering from Duke University, Durham, NC, in 1998, and the M.S.E.E. degree from Purdue University in West Lafayette, IN in 2000. She is currently working toward the Ph.D. degree at Purdue University. Her research interests include low-power circuit design and design techniques for nanoscale devices. Ms. Neau was the recipient of graduate fellowships from Intel and the Semiconductor Research Corporation. Riza Tamer Cakici received the B.S. degree in electrical engineering and physics from Bogazici University, Istanbul, Turkey, in 2000. He is currently working toward the Ph.D. degree in electrical and computer engineering at Purdue University, West Lafayette, IN. Amit Agarwal was born in Ghazipur, India. He received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Kanpur, India, in 2000, and the the M.S. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in 2001. He is currently working toward the Ph.D. degree in electrical and computer engineering at Purdue University. In summer 2001, he was with SGI microprocessor design center, Boston, MA, working on signal integrity. His research interests include low-power and high-performance cache design, low-power integrated circuits and architecture, and reconfigurable architecture design with unreliable components. Mr. Agarwal received the Certificate of Academic Excellence in 1997, 1998, and 1999. In 2000, he received a Fellowship from Purdue University. Chris H. Kim received the B.S. degree in electrical engineering and the M.S. degree in biomedical engineering, from Seoul National University, Seoul, Korea, in 1998 and 2000, respectively. He is currently working toward the Ph.D. degree in electrical and computer engineering at Purdue University, West Lafayette, IN. In summer 2002, he was with Circuit Research Labs, Intel Corporation, Hillsboro, OR, where he was involved in research on variation-tolerant dynamic circuits. His current research interests include leakage reduction/tolerant circuit design for low-power and high-performance VLSI systems in scaled technologies. Kaushik Roy (S’83–M’83–SM’95–F’02) received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and lowpower circuit design. In 1993, he joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, where he is currently a Faculty Scholar Professor. His research interests include VLSI design/computer-aided design (CAD) with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. He has published more than 200 papers in refereed journals and conferences, holds five patents, and is a coauthor of a Low-Power CMOS VLSI Circuit Design (New York: Wiley, 2000). Dr. Roy received the National Science Foundation Career Development Award in 1995, the IBM Faculty Partnership Award, the ATT/Lucent Foundation Award, and the Best Paper Awards at the 1997 International Test Conference and 2000 International Symposium on Quality of IC Design. He is on the editorial board of IEEE Design and Test, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS and IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. He was Guest Editor for the Special Issue on Low-Power VLSI in the IEEE Design and Test in 1994 and IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS in June 2000.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
Gate Leakage Reduction for Scaled Devices Using Transistor Stacking Saibal Mukhopadhyay, Student Member, IEEE, Cassondra Neau, Student Member, IEEE, Riza Tamer Cakici, Amit Agarwal, Chris H. Kim, Student Member, IEEE, and Kaushik Roy, Fellow, IEEE
Abstract—In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (Le ) of 25 nm ( oxide thickness = 1 1 nm), 50 nm ( oxide thickness = 1 5 nm) and 90 nm ( oxide thickness = 2 5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are explored for scaled technologies. It is shown that, as the contribution of gate leakage relative to the total leakage increases with technology scaling, traditional techniques become ineffective in reducing overall leakage current in a circuit. A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit. This technique results in 44% savings in total leakage in 50-nm devices compared to the conventional stacking technique. Index Terms—Device simulation, gate direct tunneling, standby-mode, subthreshold leakage, technology scaling, transistor stacking, ultra-thin gate oxide.
I. INTRODUCTION
A
GGRESSIVE scaling of MOS devices requires use of ultra-thin gate oxides to maintain a reasonable shortchannel effect [1]. The International Technology Roadmap for Semiconductors (ITRS) predicts gate-oxide thicknesses of 1.2–1.6 nm for sub-100-nm CMOS [2]. Such thin oxides give rise to high electric fields, resulting in considerable direct tunneling current [3]. For CMOS devices with thicker oxides, the major leakage mechanism is subthreshold current, which increases due to the short channel effect. However, in the ultra-thin gate-oxide regime gate tunneling current between the gate and the source-drain extension (SDE) overlap region, known as edge direct tunneling (EDT) and between the gate and the channel becomes appreciable and dominates the total “off” state leakage current of the transistor [4]. Hence, circuit techniques used to control subthreshold leakage need to be reinvestigated to evaluate their effectiveness in improving the overall leakage current. Although, many researchers have studied the effects of gate tunneling current [5]–[8], very few techniques to reduce gate leakage in a circuit have been reported.
Manuscript received October 17, 2002; revised January 18, 2003. This work is supported in part by the Semiconductor Research Corporation, and in part by the Defense Advanced Research Program Agency, Intel, and IBM. The authors are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-1285 USA (e-mail: sm@ecn. purdue.edu; [email protected]; [email protected]; amita@ecn. purdue.edu; [email protected]; [email protected]). Digital Object Identifier 10.1109/TVLSI.2003.816145
Fig. 1. Direct tunneling of electron.
The “transistor stacking” technique is proven to be extremely effective in lowering subthreshold leakage in the standby-mode of operation of a circuit [9], [10]. In this paper, the effect of gate leakage in a transistor is modeled, the effects on gate leakage of different biasing conditions and variations of the terminal voltages of a device are studied, and the opportunities for overall leakage reduction using transistor stacking are explored. It was observed that as the gate leakage becomes dominant in scaled technologies, the traditional way of using stacking fails to reduce leakage and in the worst case might increase the overall leakage. A novel methodology of transistor stacking is proposed and its effectiveness in reducing the overall leakage in a stack of transistors and in simple logic gates is analyzed. II. GATE DIRECT TUNNELING Gate direct tunneling current is due to the tunneling of an electron (or hole) from the bulk silicon through the gate-oxide potential barrier into the gate [3]. Fig. 1 explains the direct poly-silicon gate and a tunneling phenomenon between an p-type substrate (when a positive gate bias is applied). In Fig. 1, is the height of the oxide potential barrier, is the potenand are the electron tial drop across the gate oxide, quasi-Fermi levels in the substrate and the poly-silicon, respecand are the conduction band edges in the subtively, strate and the poly-silicon, respectively. There are three major mechanisms for direct tunneling in MOS devices: 1) electrons tunneling from the conduction band of the substrate to the conduction band of the gate (or vice versa) known as the conduction band electron tunneling (CBET); 2) electrons tunneling from the valence band of the substrate to the conduction band of the gate (with generation of free holes in the substrate) known as the valence band electron tunneling (VBET); and 3) holes tunneling from the valence band of the substrate to the valence band of the
1063-8210/03$17.00 © 2003 IEEE
MUKHOPADHYAY et al.: GATE LEAKAGE REDUCTION FOR SCALED DEVICES USING TRANSISTOR STACKING
(a)
717
(b)
Fig. 2. Variation of tunneling current density with potential drop across oxide. (a) In different oxide thickness and (b) in a single oxide thickness.
Fig. 3.
Components of tunneling current [7].
gate (or vice versa) known as the valence band hole tunneling (VBHT) [7] (see Fig. 1). Direct tunneling is modeled as [5]
(1)
is the direct tunneling current density, is the where is the barrier height for potential drop across the thin oxide, is the oxide the tunneling particle (electron or hole), and thickness. A and B are physical parameters given by [5] and where is the effective mass of the tunneling particle, is the electronic charge, and is the reduced Plank’s constant [5]. Fig. 2 shows the variation of tunneling current density with based on (1). The tunneling current increases exponentially with a decrease in the oxide thickness. It depends on both the device structure and the biasing condition [8]. Fig. 3 describes the various components of gate tunneling in a scaled nMOSFET device [7]: 1) EDT components between the gate and the SDE region and ); (
2) gate-to-channel current , part of which goes to the and the rest goes to the drain ; source . 3) gate-to-substrate leakage current EDT is more significant when the device is in accumulation , where, is the flatband (i.e., for NMOS voltage). however, the gate-to-channel current is dominant for [8]. Considering the tunneling currents collected at the can be divided into three major electrodes, the gate current components: ; 1) gate-to-source ; 2) gate-to-drain . 3) gate-to-substrate (if is high) or Depending on the biasing condition, (if is high) dominates the total gate leakage current. The different direct tunneling mechanisms described in Fig. 1 are dominant or important in different regions of operations of NMOS and PMOS devices as shown in Table I [7]. Mechanisms governing the gate tunneling current in NMOS are CBET and VBET. CBET controls the gate-to-channel current. The gate to body current is controlled by CBET in accumulation and VBET in the depletion-inversion region of operation. In PMOS, VBHT dominates the gate-to-channel direct tunneling current, whereas the gate-to-body tunneling is controlled by CBET in accumulation and by VBET in the depletion-inversion region. Edge direct tunneling is governed by CBET under all bias conditions [7]. Since the barrier height for VBHT (4.5 eV) is considerably higher than the barrier height for CBET (3.1 eV), the tunneling current associated with VBHT is much less than the current associated with CBET. This results in lower gate leakage current in PMOS than NMOS [11]. Because direct tunneling leakage is significantly larger in NMOS than in PMOS, efforts to reduce gate leakage focus on NMOS gate leakage. III. STANDBY LEAKAGE CONTROL USING TRANSISTOR STACK (SELF-REVERSE BIAS) The leakage current flowing through a stack of series connected transistors depends on the number of “off” transistors in
718
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
TABLE I DOMINANT MECHANISMS FOR CURRENT COMPONENTS IN NMOS AND PMOS AT DIFFERENT REGION OF OPERATIONS. EDGE DIRECT TUNNELING AND I ) ARE ALWAYS DOMINATED BY CBET (I
an increase in the body effect (negative ), and a reduction in (less DIBL) reduce the subthreshold current exponentially. To analyze the effect of transistor stacking on the gate current, the variation of gate current with source voltage is investigated based on the gate current model in (1) for gate to channel ( and ) tunneling and EDT ( and ). From (1) and Fig. 2, tunneling current increases with an increase in the voltage drop . can be defined by the following across the gate oxide equations in different regions: a) channel region (3a) b) gate-source overlap region (3b) c) gate-to-drain overlap region Fig. 4. Two-input NAND gate. Turning “off” M1 and M2 raises V value causing the “stacking effect” [9].
to positive
the stack. In the two-input NAND gate shown in Fig. 4, turning and raises the intermediate node voltage “off” both to a positive value due to a small drain current [9]. Positive potential at the intermediate node has three effects: becomes negative; 1) gate-to-source voltage of M1 of causes 2) negative body-to-source potential more body effect; of decreases, re3) drain-to-source potential sulting in less drain-induced barrier lowering (DIBL). This phenomenon is known as the “stacking effect.” From the BSIM2 MOS transistor model [12], subthreshold current flowing through “off” transistor is given by (2) . , and are where the gate-to source, the drain-to-source, and the bulk-to-source voltages, respectively. The bulk is connected to ground. and are the body effect and DIBL coefficients, respectively. is the zero-bias threshold voltage. is the gate-oxide capacis the zero-bias mobility, and is the subthreshold itance. , swing coefficient. From (2) it is observed that a negative
(3c) is the gate-to-source voltage, is the gate-to-drain where is the surface potential, and is the potential voltage, and drop across the poly-silicon depletion region. are the flat-band voltages in the channel (between n -poly and V ) and in the SDE (between n -poly and p substrate source drain V). With the gate voltage at “ ”, n “ ”, an increase the gate current is dominated by EDT. At increases . From (1) and (3b), an in the source voltage results in an increase in the tunneling through increase in the gate-to-source overlap region. Hence, the total gate current “ ”, an increase in reduces increases. However, with . The reduction the gate-to-source tunneling by reducing also reduces the gate-to-channel tunneling. In addition, in “ ” with a high drain voltage , is also high. at results in an increase in From (1) and (3c) an increase in the tunneling in the gate-drain overlap region, resulting in an increase in the gate current. A. Modeling Total Leakage in a Transistor Stack In order to evaluate the effect of stacking on the leakage reduction, it is necessary to model leakage current through a stack of transistors. Modeling the total leakage through a stack of transistors is possible by solving Kirchoff’s current law (KCL) at
MUKHOPADHYAY et al.: GATE LEAKAGE REDUCTION FOR SCALED DEVICES USING TRANSISTOR STACKING
719
the ground (either though the gate or through the transistor in a previous stage that drives that gate). Techniques for the selection of proper input vectors (“input vector control”) and for the addition of an extra series connected transistor (“forced stacking”) are investigated to evaluate their effectiveness in reducing the overall leakage for scaled technologies. B. Leakage Control Using Transistor Stack
Fig. 5. Current distribution at the intermediate node of a two-transistor stack. The direction of currents shown is taken as the default directions in the model.
each intermediate node of the stack. The current equation at the intermediate node in Fig. 4 is given by (4) is the drain-to-source current. Depending on the where is governed by the region of operation of the transistor, drain-to-source current equation in subthreshold region, the linear region, or the saturation region. Default directions of , , , and are taken as shown in Fig. 5. currents Different components of the gate current are calculated using (3) and the BSIM4 model of the gate currents [7]. A numerical intermediate solver is used to solve the simultaneous node equations with different input vectors for the “off” state of in a stack an n-transistor stack. The total gate current of n transistors is calculated using following definition:
(5) is the gate current through the kth transistor (default where direction is flowing into the gate as shown in Fig. 5). The total leakage is modeled by adding all of the currents going to the ground (or by adding all of the currents coming out of supply ). Using this definition the total leakage through a stack of transistor is calculated using following equation:
1) Input Vector Control: Due to the stacking effect, leakage through a logic gate depends on the applied input vector. To evaluate the effect of input vector selection in controlling leakage, the pull-down network of the two-input NAND gate (a two-transistor stack) in Fig. 4 is considered under all input conditions for which the output is high (gate is “off”). Those “ ”, “ '' “ ”), ( “ ”, conditions are ( “ ” “ ”) and ( “ ”, “ ” “ ”). With both of the gates at logic “0”, the intermediate node voltage is positive, resulting in a negative value of . This reduces the subthreshold current in M1. With all other input of M1 and M2 are either positive or zero. Thus, vectors, “00” gives the minimum subthreshold current flowing through a stack of two transistors. It has been shown that subthreshold current flowing through a stack of transistor decreases with an increase in the number of the “off” transistors. Hence, the “input vector control” technique can be effective in reducing the total subthreshold leakage of a circuit in the standby-mode of operation [13]. However, the input vectors have a different effect on the gate leakage than the subthreshold leakage. Since EDT dominates the gate current of a transistor with the gate at “0”, the gate current of the transistors in Fig. 4 with input “00” is given by
(7) is the width and is the length of SDE region where , of the transistor. With “00” as the input vector, , and . Since is small , is the dominant component of the total compared to gate current (Fig. 6). Hence, the total gate current can be written as
(6) is the source current of the th transistor and is the where gate voltage of the th transistor ( “0” or “1”). If gate is at “0” , current is flowing out of gate (i.e., the direction is the reverse of its default direction in Fig. 5) and into of
(8)
720
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
Fig. 6. Two-transistor stack with input vector “00” and “10”.
With the gate at “1” gate-to-channel tunneling is the major component of gate tunneling and the total gate current is given by
Fig. 7. Variation of gate current in a two-transistor stack with input vector in different gate leakage to total leakage ratio. “10” is the minimum gate current vector.
(9)
in ((1) and Fig. 2). From (8) and (11), the total gate current in a stack with input “10” is less than that with input “00” since reduces the tunneling current (Fig. 2). a decrease in The total leakage given by (6) depends on both gate current and subthreshold current. With input state “00”, the total leakage is
is the gate-to-channel current and is the where and are controlled by gate-to-bulk component. in the channel. With “01” as input vector , , and . Since both and are at , , , and are high, resulting in high total gate current. The input state “10” is of the intermediate voltage particular interest. With , where is the threshold voltage of the top rises to transistor (modulated by the body effect and DIBL). Under this , , and condition . This results in to be negligible. Therefore, the total gate current can be expressed as (10) is much less than , Since (Fig. 6). With the the dominant component is difference between the valence band edge at the substrate-oxide interface and the conduction band edge at the polysilicon-oxide interface is very small. Consequently, the VBET from the valence band of the substrate to the conduction band of the polysilvery small compared to the icon is negligible. This makes is other components since the major mechanism resulting in VBET (Table I). Hence, the total gate current is given by
(11)
, whereas with “00” With “10” as the input . Hence, the gate-to-source as the input and gate-to-channel currents of M1 overlap with “10” are higher than and with “00”. However, this increase is much less than the decrease in gate-to-drain tunneling in M2 with “10” from the gate-to-drain tunneling in M1 . This is due to the fact that the rate of with “00” change of tunneling current density increases with an increase
(12) is the subthreshold current and is where the gate-to-drain overlap current of the top transistor with “00” as the input vector. With “10”as the input state, the total leakage is (13) is the subthreshold current and is where the gate-drain overlap current of the bottom transistor with “10” as input. Hence, the change in the total leakage from input state ) is given by of “00” to “10” (
(14) is less than , whereas is greater . Hence, the minimum leakage condition dethan pends on the ratio of gate leakage to subthreshold leakage. For larger devices with thicker gate oxides where subthreshold current dominates over gate leakage, the input vector with all zeros gives the minimum subthreshold current and, therefore, the minimum overall leakage. However, with the decrease in oxide thickness with device scaling, gate leakage can become a dominant component of leakage. Hence, turning on the top transistor will give the minimum leakage condition in scaled devices. To evaluate the correctness of the model, a two-transistor stack was solved using the numerical solver for 70-nm nMOS transistors provided by BPTM [14] with oxide thicknesses of 1.2, 1.4, and 1.6 nm. The decrease in oxide thickness resulted in an increase in the gate leakage to total leakage ratio (0.95, 0.68, and nm, respectively). Figs. 7 and 0.25 for and 8 show the variation of gate current and total leakage with
MUKHOPADHYAY et al.: GATE LEAKAGE REDUCTION FOR SCALED DEVICES USING TRANSISTOR STACKING
Fig. 8. Variation of total leakage current in a two-transistor stack with input vector in different gate leakage to total leakage ratio. The “00” is the lowest leakage for lower gate leakage to total leakage ratio but with increased ratio “10” is the best case.
different input vectors for different gate leakage to total leakage ratios. As predicted from the model, the application of “10” produces the minimum gate current in all cases. However, the total leakage is minimized with the input condition “00” in the case where the ratio is least. With an increase in the contribution of the gate leakage relative to the total leakage, the input condition “10” provides the lowest total leakage. Modeling the total leakage in a stack of transistors shows that “input vector control” can be very effective in controlling the overall leakage in the standby-mode of operation. However, the optimal input vector changes with technology generation. The described model provides a new method of input vector selection based on the contributions of the gate current and the subthreshold current to the total leakage. In devices where the subthreshold current is more significant, the input vector should be chosen to maximize the number of the “off” transistors in the stack. However, in scaled devices with more gate current, turning “on” the top transistor in the stack results in the minimum gate current and the minimum overall leakage through the stack. 2) Forced Stacking: “Input vector control” takes advantage of the transistor stacks inherently present in logic design to minimize leakage. Further leakage reduction can be achieved by adding more stacking transistors although this additional leakage savings is accompanied by an area penalty. The technique of inserting an extra series connected transistor in the pull-down path of a gate and turning it “off” in the standby-mode of operation is known as “forced stacking” [15]. During regular mode of operation, the extra transistor is turned on. Forced stacking can provide additional savings in leakage current during standby mode of operation. When the extra transistor is turned “off”, the intermediate source voltage increases, as described earlier. This results in a decrease in the subthreshold current through the top transistor. Hence, the total subthreshold leakage through a two-transistor stack is reduced. It has been shown that the subthreshold leakage of a two-transistor stack is an order of magnitude less than the leakage in a single transistor [10]. However, an increase in the source voltage increases the gate leakage of the top transistor. Hence, the total gate leakage through the stack increases. Using the model of total leakage described in (6),
721
(a)
(b) Fig. 9. Effectiveness of forced stacking in saving overall leakage. (a) Normal forced stacking. (b) New forced stacking. Normal forced stacking does not have significant effect in devices with more gate current contribution. New forced stacking is more effective in leakage saving in all devices with considerable gate current.
the total leakage through a single transistor is given by two-transistor stack
and a (15) (16)
and are the subthreshold current of a single where and transistor and a two-transistor stack, respectively. are almost zero in both cases since . and remain the same since in both cases . Therefore, the change in the total leakage is given by
(17) In devices where the subthreshold leakage is large compared to the gate leakage, the reduction in the subthreshold leakage offsets the increase in the gate leakage considerably, thereby producing the overall leakage improvement with “forced stacking”. However, in scaled devices with a considerably larger gate leakage contribution, the saving in the subthreshold leakage does not have a strong effect on the overall leakage. Hence, the technique fails to provide significant leakage reduction [see Fig. 9(a)].
722
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
(a)
(b)
(c) Fig. 10.
I
0V
characteristics of the transistors. (a) L
= 25 nm. (b) L
A new technique of forced stacking is proposed where, along with turning “off” the extra transistor, the gate of the top tranin sistor is raised to “1” in the standby mode. This reduces a two-transistor stack. As described earlier, the increase in and is much less than the reduction in . Hence, (17) changes to
= 50 nm. (c) L
= 90 nm.
simulator MEDICI [17]. To model the effect of direct tunneling in NMOS, the tunneling mechanisms CBET and VBET were considered in MEDICI. The net direct tunneling current was calculated using the independent electron approximation and for CBET it is given by [17]
(19) (18) is large compared to In devices with high gate leakage, and . Hence, this results in significant savings in total leakage. Fig. 9(b) shows the variation of total leakage with an increase in the transistor stack length based on the model described above. Significant reduction in total leakage is observed with an increase in the stack length. IV. DEVICE SIMULATIONS WITH DIRECT TUNNELING A. Gate Current Model To observe the effect of gate direct tunneling in the behavior of a transistor, NMOS transistors were designed based on the doping profiles given in [16] and the design guidelines given in the 2001 ITRS Roadmap [2] for effective gate lengths of 90, 50, and 25 nm. The devices were simulated using the device
where the integral is over the vertical kinetic energy, E, of the , , and are the electron quasiincident electrons. Fermi level, the conduction band edge, and the electron effective tunneling mass, respectively, in silicon region at the insuand are the corresponding electron lator interface. quasi-Fermi level and conduction band edge in poly-silicon region. The endpoint of the integration is determined by the bar. The electron charge is given by q, his Planck’s rier height, is the thermal energy. TC is the tunneling coconstant, and efficient of an electron with energy E. For VBET, (19) is computed for electrons in both the heavy and light hole bands with replaced by , the valence band in silicon region; replaced by , the hole quasi-Fermi level in region 1; and the tunneling masses in silicon region are set by the light and heavy hole effective masses [17]. The tunneling coefficient was
MUKHOPADHYAY et al.: GATE LEAKAGE REDUCTION FOR SCALED DEVICES USING TRANSISTOR STACKING
(a)
723
(b)
(c) Fig. 11. Variation of gate current with gate voltage. V (c) L = 90 nm, V = 1:2 V .
=V ,V
= 0, V
calculated using the Gundlach method for the exact tunneling coefficient of a trapezoidal barrier described in [17]. Quantum mechanical effects in the inversion layer and band-to-band tunneling were included in the device model. B.
–
Characteristics of the Transistor
– characteristics for the Fig.10(a)–(c) shows the 25-, 50-, and 90-nm devices, respectively. It was observed that in scaled technologies, the gate direct tunneling coupled with the subthreshold current, increases the overall “off” current of the devices. However, high for nm for nm for nm ratios indicate reasonable transistor characteristics. At a high , a large increase in occurs for drain bias smaller devices due to increases in drain-to-gate leakage current and band-to-band tunneling at the reverse biased n drain and p-substrate junction. C. Simulation of Gate Tunneling Current Fig. 11(a)-(c) shows the variation of gate current with gate voltage for 25-, 50-, and 90-nm devices, respectively, for different oxide thicknesses. In all cases the drain-to-source
= 0; (a) L
= 25 nm, V
= 0:7 V , (b) L
= 50 nm, V
= 1 :0 V ,
voltage was kept at for the corresponding technology [2] . As the gate voltage and the gate bias was varied from 0 to , starts decreasing since is increased from 0 to decreases. On the other hand an increase in cause and to increase. It was observed that, with a decrease in the oxide thickness for a particular technology, gate current increases exponentially. Large increases in gate current are observed as the technology is scaled down. Fig. 12 shows the ratio of gate leakage to overall leakage for the “off” state of the devices . The ratio increases as the oxide thickness is with scaled down. However, it was observed that the ratio decreases as we go down to 25-nm devices from 50-nm devices. This is due to the increase in the band-to-band tunneling (BTBT) current at the reverse bias drain n -substrate (p) junction, resulting in high substrate current. An increase in BTBT causes the total leakage to increase resulting in a decrease in the gate leakage to the total leakage ratio. In smaller technologies, BTBT current is expected to be a major leakage component due to the increased doping concentration of the substrate, the application of halo doping to reduce short channel effects, and an increased abruptness of the doping profile [3]. However, if double gate MOSFETS are used, significant BTBT leakage will not be present.
724
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
Fig. 12. Ratio of gate leakage to overall leakage in different technology generation. Ratio increases with decrease in oxide thickness in a generation. Ratio increases from 90 to 50 nm are due to increase in gate current. However, decreases from 50 to 25 nm are due to increase in BTBT.
(a)
(b)
(a)
(b) Variation of gate current with source voltage (Le = 50 nm) with ,V = 0 and (a) V = 0, (b) V = 1. With V = 0, gate current increases with increase in source voltage. However, with V =1 it decrases with source voltage. Fig. 13.
V
=V
D. Effect of Source Bias on Gate Current In order to estimate the effect of transistor stacking on gate tunneling current, the variation of gate current with an increase was simulated for NMOS transistors. It in the source bias
Fig. 14. Variation of: (a) gate current and (b) total leakage with source voltage for L = 25; ; 50; and 90 nm. For the 90-nm device, overall leakage decreases with source voltage. However, the effect is reverse for scaled devices. (V =V ,V = 0 and V = 0).
was observed that for a low gate bias “ ” , increasing the source bias increases , thereby increasing the overall gate , leakage [see Fig. 13(a)]. This is due to the fact that, for and dominate the overall leakage current [8]. With increases due to an increase an increase in source bias, (the difference between the conduction band edge at in the SDE and the poly-silicon increases causing the potential at the SDE to increase), thereby indrop across oxide creasing . CBET from the gate to the channel also increases level at the surface ( due to the increase in the also increases), resulting in increases in ( and ) and . An increase in the gate leakage with an increase in the source voltage is the reverse of the effect of increasing the source voltage on the subthreshold leakage. On the other hand, having makes the gate current to go down with the increase in [see Fig. 13(b)]. the source voltage due to the reduction of With an increase in , the conduction band edge at the surface and ( goes down, decreasing the difference between at the channel reduces). also goes down and eventually . Hence, CBET decreases, causing ( and goes below ) to reduce. An increase in causes at the channel to and . go down reducing the difference between also goes down decreasing . Hence, VBET de. Higher also reduces the differcreases thereby reducing
MUKHOPADHYAY et al.: GATE LEAKAGE REDUCTION FOR SCALED DEVICES USING TRANSISTOR STACKING
Fig. 15.
Three-transistor stack.
Fig. 16. Variation of subthreshold current with input vector for a stack of 2T transistors, not including modeling of gate leakage. “00” is the lowest leakage vector.
ence between and at the SDE region ( at the SDE decreases. It was observed that, for region reduces). Hence, 90-nm devices, overall leakage reduces with positive source bias in an “off” transistor due to the reduction in subthreshold current. However, for 25- and 50-nm devices with larger gate current, the total leakage increases with an increase in source bias (Fig. 14). V. VERIFICATION WITH DEVICE SIMULATION The “pull-down” networks of stacks of NMOS transistors were simulated for 90-, 50-, and 25-nm devices with oxide thickness of 2.5, 1.5, and 1.1 nm, respectively, in MEDICI at room K to verify the trends predicted by the temperature analytical model derived in Section III regarding total leakage in a transistor stack. The “Input Vector Control” and “Forced Stacking” techniques were investigated based on the simulation results, to evaluate their effectiveness in saving overall leakage in different technology generations. A. “Transistor Stack” Pull-Down Network 1) Input Vector Control: Two and three transistor stacks with different input vectors were simulated to observe the effect of input vector selection on overall leakage reduction. Fig. 15 of a “pull-down” netshows a normal “off” state work of three-transistor stack with input vector “100” ( “ ”, “ ”, “ ”). As described in Section III, with an increase in number of “off” transistors, the subthreshold leakage flowing through the stack reduces. The simulation
725
Fig. 17. Variation of subthreshold current with input vector for a stack of three transistors, not including modeling of gate leakage. “000” is the lowest leakage vector.
shows that “00” and “000” are lowest leakage input vectors (ignoring gate current) for the two and three transistor stacks respectively, with savings of over 70% compared to the worst cases (input vector “01” and “011”) for 50-nm devices (Figs. 16 and 17). Table II shows the savings in the subthreshold leakage with application of different input vectors based on the MEDICI simulation results. Simulations of transistor stacks including the gate direct tunneling current model show that application of the input vectors “10” and “100” results in the minimum total gate current in a stack of two and three transistors, respectively for 25-, 50-, and 90-nm devices (see Figs. 18 and 19). This conforms to the trend obtained from the analytical model (see (8) and (11) in Section III and Fig. 7). Simulation of the two-transistor stack verifies the prediction that with input “00”, the dominant component of current of top tranthe gate current is the gate-to-drain sistor whereas with “10” as the input, the gate-to-drain current is dominant. For example, simuof the bottom transistor nA m lating 50-nm devices, it is observed that, is approximately 97% of the total gate leakage current. Howis reduced to nearly zero and ever, with “10” as input, nA m is the dominant component (87% of total with “10” input state is considerably less than gate current). with “00” (57% in 50-nm devices), because with is much less than with “00” . “10” increases from input state “00” to input state “10” (from 0.1 to 0.69 nA m in 50-nm device). However, the contriburelative to total leakage is less in both cases (1.2% tion of with “00” and 12.8% with “10” for 50-nm device). Hence, the application of “10” results in lower gate leakage than “00” (37% saving in 50-nm devices). This verifies the prediction made in Section III. Table III gives the percentage savings in total gate current for two- and three-transistor stacks with different input vectors for 25-, 50-, and 90-nm devices. Figs. 20 and 21 show the variation of overall leakage with different input vectors for 25-, 50-, and 90-nm devices in twoand three-transistor stacks, respectively, based on the simulation results. It was observed that for 90-nm devices, where the contribution of subhreshold leakage is much greater than that of gate leakage, “00” and “000” are the lowest leakage input vectors, reducing 62% and 77% of the total leakage from worst cases, respectively. However, “10” and “100” are the best-input vectors for 25- and 50-nm devices, where the contribution of gate
726
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
TABLE II PERCENTAGE SAVINGS IN SUB-THRESHOLD LEAKAGE IN TRANSISTOR STACK WITH DIFFERENT INPUT VECTOR WITHOUT GATE TUNNELING EFFECT
Fig. 18. Variation of gate tunneling current with input vector for two-transistor stack. “10” is the minimum gate current vector.
Fig. 20. Variation of total standby power for two-transistor stack. The “00” is the lowest leakage for 90-nm node but with increased gate tunneling current “10” is the best case in 25- and 50-nm devices.
Fig. 21. Variation of total standby power for three-transistor stack. “000” is the best case in 90-nm case but “100” is the lowest leakage power case in 25and 50-nm devices. Fig. 19. Variation of gate tunneling current with input vector for three-transistor stack. “100” is minimum condition.
leakage is greater. This verifies the trends predicted by the analytical model [see (14)] in Section III and Fig. 8. Table IV shows the percentage savings in overall leakage for these three technology generations. Leakage saving using “10” and “100” over “00” and “000” is 42% and 44% for 50-nm devices, whereas it is 36% and 37% for 25-nm devices. This decrease in leakage savings is caused by an increase in BTBT current resulting in an increase in overall leakage. BTBT increases with increased . In Fig. 6, reverse bias across the drain–substrate junction for M1 (top transistor) is and with “00” as the input, for M2 (bottom transistor) is almost zero. However, with of M2 increases to resulting “10” as the input,
in an increase in BTBT leakage in M2. This results in an increase in total leakage. Hence, the overall leakage savings using “10” (or “100”) reduces from 50-nm devices. Table V summarizes the minimum, maximum and average leakage (averaged over all input vectors for which the stack is “off”) of two- and three-transistor stacks for 25-, 50-, and 90-nm devices. 2) Forced Stacking Technique: Simulation of a stack of NMOS transistors, neglecting the gate direct tunneling current, shows that subthreshold leakage reduces with an increase in the number of transistor (or “length”) in the stack for all devices (Fig. 22). Increasing the length of a stack from 1 to 2 saves the subthreshold current by 78%, 70%, and 61% for 25-, 50-, and 90-nm devices, respectively. Simulation of transistor stacks including gate current shows that gate leakage
MUKHOPADHYAY et al.: GATE LEAKAGE REDUCTION FOR SCALED DEVICES USING TRANSISTOR STACKING
727
TABLE III PERCENTAGE SAVINGS IN TOTAL GATE CURRENT ((5)) IN TRANSISTOR STACK WITH DIFFERENT INPUT VECTOR
TABLE IV PERCENTAGE SAVINGS IN OVERALL LEAKAGE IN TRANSISTOR STACK WITH DIFFERENT INPUT VECTOR
MINIMUM, MAXIMUM
AND
TABLE V AVERAGE LEAKAGE IN TWO-TRANSISTOR STACK, THREE-TRANSISTOR STACK DIFFERENT TECHNOLOGY GENERATIONS
increases with an increase in the stack length for all devices (Fig. 23). It is observed that in 90-nm devices, due to the small contribution of gate leakage, total leakage decreases with an increase in stack length. For 50- and 25-nm devices, where the contribution of gate leakage is large, forced stacking does not have a significant effect on total leakage (Fig. 23). This follows the same trend predicted by the analytical equations in Section III [see Fig. 9(a)]. Simulation of transistor stacks with the new forced stacking method, described in Section III, shows that, overall leakage for 25- and 50-nm devices reduces with increase in stack length (Fig. 24). The addition of an extra transistor and keeping the gate of the top transistor at “1” saves 35% and 46% of leakage
AND AND-OR
NETWORK
FOR
in 25- and 50-nm devices, respectively. This verifies the result predicted by the analytical model in Section III [see Fig. 9(b)]. B.
AND-OR
Pull-Down Network
In order to evaluate the effect of gate leakage on more complex logic gates, a three-input AND-OR pull-down network was simulated for 25-, 50-, and 90-nm devices. The logic “A AND (B OR C)” can be implemented using the configurations shown in Fig. 25, namely, with parallel transistors implementing “B OR C” (MB and MC) connected to (single transistor implementing “A” (MA) connected to ground) and with parallel transistors MB and MC connected to ground (MA connected to
728
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
Fig. 22. Leakage saving by forced stacking, not including the effect of gate tunneling current in the model. stacking is saving overall leakage by over 61% in 90 nm, 70% in 50 nm, and 78% in 25 nm.
Fig. 23. Leakage saving by forced stacking in the presence of gate tunneling current. The forced stacking is saving overall leakage in 90-nm node where gate leakage is less. With more gate leakage the effectiveness is absent.
Fig. 24. Leakage saving by new forced stacking. Application of “1” at the gate of top transistor saves overall leakage by 35% in 25 nm and 46% in 50-nm node.
). Both configurations were simulated for the input condi, tions for which the network is in the “off” state, namely ( , ), ( , , ), ( , , or , , ) and ( , , ). The overall leakage of the network for the 25-, 50-, and 90–nm devices are shown in Fig. 26. In 90-nm devices, where , , ) subhreshold leakage is dominant, input ( , gives the minimum leakage with MB and MC connected to condition (76% savings compared to worst case). For 50-nm de, , ) with MB and MC convices, input (
Fig. 25.
AND-OR
pull-down network.
nected to , results in minimum overall leakage with 85% and , reduces savings from the worst case. Having the dominant drain-to-gate current of both of the parallel tran, sistors MB and MC. For 25-nm devices, application of ( , ) as the input with MB and MC connected to provides a 60% savings compared to the worst case. Table V summarizes the minimum, maximum and average leakage of the AND-OR pull down network for 25-, 50-, and 90-nm devices.
MUKHOPADHYAY et al.: GATE LEAKAGE REDUCTION FOR SCALED DEVICES USING TRANSISTOR STACKING
729
Fig. 26. Overall leakage in AND-OR pull-down network. For 90-nm devices “000” with parallel transistors at the top gives minimum leakage. However, for 50 nm and 25-nm devices parallel transistors on top with “1” at gate of both of them gives minimum overall leakage.
(a) Fig. 27.
Variation of gate leakage and subthreshold leakage with temperature.
VI. EFFECT OF TEMPERATURE ON SUBTHRESHOLD LEAKAGE AND GATE LEAKAGE The basic physical mechanisms governing subthreshold and gate leakage have different temperature dependencies. Subthreshold current is governed by the carrier diffusion which increases with an increase in temperature. Subthreshold current increases exponentially with temperature due to: 1) the reduction in threshold voltage and 2) an increase in thermal . Gate tunneling current is almost insensitive voltage to temperature since the electric field across the oxide and the tunneling probability of an electron do not strongly depend on temperature. Hence, at elevated temperature subthreshold current dominates over gate leakage. Fig. 27 shows the variation of the total gate current and the subthreshold current nm and with the temperature for a device with nm. At K the gate current is considerably higher than the subthreshold current. However, at an elevated K) the subthreshold current dominates temperature ( the gate current. Hence, based on the model developed in the Section III, the input vector that minimizes the subthreshold leakage is more effective in reducing the overall leakage at elevated temperature. Fig. 28 shows the subthreshold, gate and total leakage in a two-transistor stack with different input vecK) and high ( K) temperature tors at room ( based on the model developed in Section III. It is observed that at for 25- and 50-nm devices at room temperature “10” is the minimum leakage vector. At an elevated temperature
(b) Fig. 28. Variation of gate and subthreshold leakage with input vector at diferent temperature. (a) Room temperature (T = 300 K). (b) Elevated temperature (t = 400 K). At room temperature, for 25- and 50-nm devices “10” is the best input vector. However, at elevated temperature, due to higher subthreshold leakage “00” is the minimum leakage vector in 25 and 50 nm.
( K), due to higher subthreshold leakage, application of “00” results in the minimum leakage. However, stacking is used mostly to reduce the total leakage in the standby-mode of operations. In standby-mode, the operating temperature is near room temperature where gate leakage is dominant in scaled technologies. VII. CONCLUSION It is demonstrated that with technology scaling the contribution of gate leakage and subthreshold leakage relative to the total leakage in an “off” transistor varies. The effect of gate leakage in a device and circuit is modeled using simple equations and we investigated the opportunities for reducing gate leakage using
730
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003
device simulations. It is observed that as the gate leakage becomes a significant component of total leakage, the traditional stacking technique to reduce subthreshold leakage fails to minimize the overall leakage in a circuit. A methodology of input vector selection based on the ratio of gate-leakage to the subthreshold leakage is proposed for reducing the overall leakage of a circuit in the standby-mode of operation. The analysis was verified using device simulations on transistor stacks. REFERENCES [1] K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design. New York: Wiley, 2000, ch. 5, pp. 224–226. [2] (2001) International Technology Roadmap for Semiconductors, 2001 Edition. Semiconductor Industry Assoc. [Online]. Available: http://public.itrs.net/Files/2001ITRS/Home.htm [3] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998, ch. 2, pp. 94–97. [4] N. Yang, W. K. Henson, and J. Wortman, “A comparative study of gate direct tunneling and drain leakage currents in N-MOSFETs with sub-2100-nm gate oxides,” IEEE Trans. Electron Devices, vol. 47, pp. 1636–1644, Aug. 2000. [5] K. Schuegraf and C. Hu, “Hole injection SiO breakdown model for very low voltage lifetime extrapolation,” IEEE Trans. Electron Devices, vol. 41, pp. 761–767, May 1994. [6] N. Yang, W. Henson, and J. Hauser, “Modeling study of ultrathin gate oxides using tunneling current and capacitance-voltage measurement in MOS devices,” IEEE Trans. Electron Devices, vol. 46, pp. 1464–1471, July 1999. [7] K. Cao, W.-C. Lee, W. Liu, X. Jin, P. Su, S. Fung, J. An, B. Yu, and C. Hu, “BSIM4 gate leakage model including source drain partition,” in IEDM Tech. Dig., 2000, pp. 815–818. [8] C. Choi, K. Nam, Z. Yu, and R. W Dutton, “Impact of gate direct tunneling current on circuit performance: a simulation study,” IEEE Trans. Electron Devices, vol. 48, pp. 2823–2829, Dec. 2001. [9] V. De et al., “Techniques for leakage power reduction,” in Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. J. Bowhill, and F. Fox, Eds. Piscataway, NJ: IEEE Press, 2001, ch. 3, pp. 52–55. [10] Y. Ye, S. Borkar, and V. De, “New technique for standby leakage reduction in high-performance circuits,” in Symp. VLSI Circuits Dig. Tech.Papers , 1998, pp. 40–41. [11] F. Hamzaoglu and M. Stan, “Circuit-level techniques to control gate leakage for sub-100 nm CMOS,” in Proc. Int. Symp. Low Power Design, Aug. 2002, pp. 60–63. [12] B. J. Sheu, D. L. Scharfetter, P. Ko, and M. Jeng, “BSIM: Berkeley short-channel IGFET model for MOS transistors,” IEEE J. Solid-State Circuits, vol. 22, pp. 558–566, Aug. 1987. [13] Z. Chen, L. Wei, A. Keshavarzi, and K. Roy, “IDDQ testing for deep submicron ICs: challenges and solutions,” IEEE Design Test. Comput., pp. 24–33, Mar.–Apr. 2002. [14] Berkeley Predictive Technology Model (BPTM). Device Group, Univ. California at Berkeley. [Online] Available: http://www-device.eecs.berkeley.edu/~ptm/ [15] M. C. Johnson, D. Somasekhar, and K. Roy, “Leakage control with efficient use of transistor stacks in single threshold CMOS,” in Proc. ACM/IEEE Design Automation Conf., 1999, pp. 442–445. [16] Well-Tempered, Bulk-Si NMOSFET Device Home Page. Microsystems Technology Laboratory, MIT. [Online] Available: http://www-mtl.mit.edu/Well/ [17] MEDICI: Two-Dimensional Semiconductor Device Simulation Program, AVANT! Corp., Fremont, CA, 2000.
Saibal Mukhopadhyay (S’99) was born in Calcutta, India. He received the B.E. degree in electronics and telecommunication electrical engineering from the Jadavpur University, Calcutta, India, in 2000, and the M.S. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in 2001. He is currently working toward the Ph.D. degree at Purdue University.
Cassondra Neau (S’00) received the B.S.E. degree in electrical engineering from Duke University, Durham, NC, in 1998, and the M.S.E.E. degree from Purdue University in West Lafayette, IN in 2000. She is currently working toward the Ph.D. degree at Purdue University. Her research interests include low-power circuit design and design techniques for nanoscale devices. Ms. Neau was the recipient of graduate fellowships from Intel and the Semiconductor Research Corporation. Riza Tamer Cakici received the B.S. degree in electrical engineering and physics from Bogazici University, Istanbul, Turkey, in 2000. He is currently working toward the Ph.D. degree in electrical and computer engineering at Purdue University, West Lafayette, IN. Amit Agarwal was born in Ghazipur, India. He received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Kanpur, India, in 2000, and the the M.S. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in 2001. He is currently working toward the Ph.D. degree in electrical and computer engineering at Purdue University. In summer 2001, he was with SGI microprocessor design center, Boston, MA, working on signal integrity. His research interests include low-power and high-performance cache design, low-power integrated circuits and architecture, and reconfigurable architecture design with unreliable components. Mr. Agarwal received the Certificate of Academic Excellence in 1997, 1998, and 1999. In 2000, he received a Fellowship from Purdue University. Chris H. Kim received the B.S. degree in electrical engineering and the M.S. degree in biomedical engineering, from Seoul National University, Seoul, Korea, in 1998 and 2000, respectively. He is currently working toward the Ph.D. degree in electrical and computer engineering at Purdue University, West Lafayette, IN. In summer 2002, he was with Circuit Research Labs, Intel Corporation, Hillsboro, OR, where he was involved in research on variation-tolerant dynamic circuits. His current research interests include leakage reduction/tolerant circuit design for low-power and high-performance VLSI systems in scaled technologies. Kaushik Roy (S’83–M’83–SM’95–F’02) received the B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and lowpower circuit design. In 1993, he joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, where he is currently a Faculty Scholar Professor. His research interests include VLSI design/computer-aided design (CAD) with particular emphasis in low-power electronics for portable computing and wireless communications, VLSI testing and verification, and reconfigurable computing. He has published more than 200 papers in refereed journals and conferences, holds five patents, and is a coauthor of a Low-Power CMOS VLSI Circuit Design (New York: Wiley, 2000). Dr. Roy received the National Science Foundation Career Development Award in 1995, the IBM Faculty Partnership Award, the ATT/Lucent Foundation Award, and the Best Paper Awards at the 1997 International Test Conference and 2000 International Symposium on Quality of IC Design. He is on the editorial board of IEEE Design and Test, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS and IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. He was Guest Editor for the Special Issue on Low-Power VLSI in the IEEE Design and Test in 1994 and IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS in June 2000.
