i #111 | 955
US 20010006479A1
(19) United States (12) Patent Application Publication (10) Pub. No.: US 2001/0006479 A1 (43) Pub. Date:
Ikchashi ct al.
(54)
READ CIRCUIT OF NONVOLATILE SEMICONDUCTOR MEMORY
(76)
Inventors: Tamio Ikehashi, Kamakura-shi (JP);
Jul. 5, 2001
Publication Classi?cation (51)
Int. Cl.7 ................................................... .. G11C 11/34
(52)
US. Cl. ...................................................... .. 365/185.24
Kenichi Imamiya, Tokyo (JP); J unichiro Noda, Yokohama-shi (JP)
(57)
ABSTRACT
Correspondence Address: l?ltllllngio?zrwltco?’ LtdI
An INVSRC node and a SAREF node are previously
1001 G Street N W
precharged. After a potential on a bit line is reset, the bit line
-
’
I
I
_
(BLS node) is precharged. In this event, a clamp MOS
Washmgmn’ DC 20001 4597 (Us)
(21) APPL N0. (22)
transistor in a sense ampli?er is in ON state, and an SA node
09/745’666
is also precharged simultaneously. Aprecharge level~is set to
Dec_ 26, 2000
Subsequently, When SAEN transitions to “H,” a sense opera
a value loWer than a threshold voltage of an mverter.
Filed;
tion is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node sloWly approaches to Vss. Achange in the potential at the SA
Foreign Application Priority Data
(30)
Dec. 28, 1999
(JP) ......................................... .. 11-373069
12
—>|
node is detected by the inverter.
CONTROL omcun
S
l
BLRST,SAENd,
INPUT/
OUTPUT DATA SIGNAL
I
BI-RST
I
INVSRC
Y
I
I
I
v
82
|
COLUMN
ADDRESS
SIGNAL
ADDRESS ( SIGNAL
S/A
___
SIA
I
___
',_,B|_S
E;
|I
1
I
BLRST—> ROW ADDRESS“
I,
SIGNAL
0
i
g
COLUMN GATE
: ___ i I
i
15 I
: W" i N I
PAGE BUFFER
21
S
18
S
S
Q00’) _
9-00:
902
5g“
2;"
Ego
~17
N
‘$4 OC: glg *’
19
S/A
I
co
SAEN,SAENn,EN
ATD3,AFD3n
31
I
%'
5
E
Q
‘T’
6’
I
I
BLSFIEi VCLAMP
I
/3_6/B|_REF
4/16
Y
37
ICI:II\IEGNERAT
BULAIIIAMN GATE ~22
MEMORY CELL ARRAY
5
VCLAMP
CIRCUIT
#111 REFER |
13 N 8 m
ENCE CELL
II
a
|
23
955 :n
2g —G“E15efEHATING
—'> 5
CIRCUIT
G) I
24
I
25
Patent Application Publication
Jul. 5, 2001
Sheet 4 0f 16 US 2001/0006479 A1
SELECT GATE LINE (SGDi) —
WORD LINE (Wi)—|
/—-/ M2
SELECT GATE LINE (SGSi) —--— ,__/ M3 Vss ~ BL]
F|G.4
_| A, M4
Vcgref_____H ,_/M5 (REFERENCE CELL) Vsg=3.5V—-—| M M6
Vss
F|G.5
Patent Application Publication
Jul. 5, 2001
Sheet 6 0f 16 US 2001/0006479 A1
17
5 1s; INVSRC GENERATING
INVSRCL 81A
cmc _____________ ‘i
I
SABER Icel
(=Iref OR 05 l
1?
COLUMN GATE
BLRS_T|¥_, Tn VSS HBLJ' SGDi
(35v) '1 -
FJ
M1
/ SELECTED
W|(0GV) 4! (CELL) 5 $1 _| ~|v|3 (3.5V)
Vss
Vcgref 5 :Ms Vsg=3.5V E I AiFMB w; CHANNEL WIDTH
i LY?)
23
Patent Application Publication
Jul. 5, 2001
Sheet 7 0f 16 US 2001/0006479 Al
N
ra‘qg? Vdd
Vdd
Vdd
Vdd
Ehiv“Eh,IV“ Eh/MPHVHI F1)1ISAREF SAEN _|: ~MP2IW=2XMXWp1 MP7 I —----
Vss
FMPi :F\MP1‘“" :F l lref/2
:
i
i
E W: CHANNEL WIDTH L: CHANNEL LENGTH
= p
n
32
M
L=Lp1
}
MXIref
Patent Application Publication
Jul. 5, 2001
Ns
Sheet 8 0f 16 US 2001/0006479 A1
VCLAMP
M14 »/
BLREF MN1 ~
EN A ~ MN9
Vss
VBGR
Patent Application Publication
Jul. 5, 2001
—
;’
— - - - q n _ _
INVSRC :31 \ I
_ _\
Vdd
E118: II\IvsRC
MP5 I E f
81A
I 3
I
I
I
i
I
‘
'
GENERATING CIRCUIT
21: SAREF PRECRARCE CIRCuIT (“NAT'VHEI‘I
I
EN '
I
SAENn:
E
I
II 19
Sheet 9 0f 16 US 2001/0006479 A1
,?I/MPIO I
a: MPH
E I
II
EI I I
I
:LMI5
ISAENH ~wE/MN10 CIRCUIT
I
36 lISAENn-l ~IPMN11
22 /\_,
___________ _-'
23 N. REFERENCE
All MI4
CELL
\ 20: GENERATING CIRuCIT
Patent Application Publication
Jul. 5, 2001
Sheet 10 0f 16 US 2001/0006479 A1
- VBGR=1.23V - VBGR2=0.5V
- Vcgref=1.0V~2.5V
(REGULATE AT
0.1V INTERVALS)
\R3 (VARIABLE RESISTOR) XR4 Vss
FIG. 12 Na
T1
JRS
Na
fRa =
1;? ‘fRe
Nb
2 T16 1R6 .L
\
N‘E Y
J
Patent Application Publication
Jul. 5, 2001
Sheet 11 0f 16 US 2001/0006479 A1
9;E5 Ni
3.01
Eg
9::
E
92
No.2 8?
uzmEw
/55m
Patent Application Publication
Jul. 5, 2001
Sheet 12 0f 16 US 2001/0006479 A1
m Q o / E m g >QmOoEzM
(19) United States (12) Patent Application Publication (10) Pub. No.: US 2001/0006479 A1 (43) Pub. Date:
Ikchashi ct al.
(54)
READ CIRCUIT OF NONVOLATILE SEMICONDUCTOR MEMORY
(76)
Inventors: Tamio Ikehashi, Kamakura-shi (JP);
Jul. 5, 2001
Publication Classi?cation (51)
Int. Cl.7 ................................................... .. G11C 11/34
(52)
US. Cl. ...................................................... .. 365/185.24
Kenichi Imamiya, Tokyo (JP); J unichiro Noda, Yokohama-shi (JP)
(57)
ABSTRACT
Correspondence Address: l?ltllllngio?zrwltco?’ LtdI
An INVSRC node and a SAREF node are previously
1001 G Street N W
precharged. After a potential on a bit line is reset, the bit line
-
’
I
I
_
(BLS node) is precharged. In this event, a clamp MOS
Washmgmn’ DC 20001 4597 (Us)
(21) APPL N0. (22)
transistor in a sense ampli?er is in ON state, and an SA node
09/745’666
is also precharged simultaneously. Aprecharge level~is set to
Dec_ 26, 2000
Subsequently, When SAEN transitions to “H,” a sense opera
a value loWer than a threshold voltage of an mverter.
Filed;
tion is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node sloWly approaches to Vss. Achange in the potential at the SA
Foreign Application Priority Data
(30)
Dec. 28, 1999
(JP) ......................................... .. 11-373069
12
—>|
node is detected by the inverter.
CONTROL omcun
S
l
BLRST,SAENd,
INPUT/
OUTPUT DATA SIGNAL
I
BI-RST
I
INVSRC
Y
I
I
I
v
82
|
COLUMN
ADDRESS
SIGNAL
ADDRESS ( SIGNAL
S/A
___
SIA
I
___
',_,B|_S
E;
|I
1
I
BLRST—> ROW ADDRESS“
I,
SIGNAL
0
i
g
COLUMN GATE
: ___ i I
i
15 I
: W" i N I
PAGE BUFFER
21
S
18
S
S
Q00’) _
9-00:
902
5g“
2;"
Ego
~17
N
‘$4 OC: glg *’
19
S/A
I
co
SAEN,SAENn,EN
ATD3,AFD3n
31
I
%'
5
E
Q
‘T’
6’
I
I
BLSFIEi VCLAMP
I
/3_6/B|_REF
4/16
Y
37
ICI:II\IEGNERAT
BULAIIIAMN GATE ~22
MEMORY CELL ARRAY
5
VCLAMP
CIRCUIT
#111 REFER |
13 N 8 m
ENCE CELL
II
a
|
23
955 :n
2g —G“E15efEHATING
—'> 5
CIRCUIT
G) I
24
I
25
Patent Application Publication
Jul. 5, 2001
Sheet 4 0f 16 US 2001/0006479 A1
SELECT GATE LINE (SGDi) —
WORD LINE (Wi)—|
/—-/ M2
SELECT GATE LINE (SGSi) —--— ,__/ M3 Vss ~ BL]
F|G.4
_| A, M4
Vcgref_____H ,_/M5 (REFERENCE CELL) Vsg=3.5V—-—| M M6
Vss
F|G.5
Patent Application Publication
Jul. 5, 2001
Sheet 6 0f 16 US 2001/0006479 A1
17
5 1s; INVSRC GENERATING
INVSRCL 81A
cmc _____________ ‘i
I
SABER Icel
(=Iref OR 05 l
1?
COLUMN GATE
BLRS_T|¥_, Tn VSS HBLJ' SGDi
(35v) '1 -
FJ
M1
/ SELECTED
W|(0GV) 4! (CELL) 5 $1 _| ~|v|3 (3.5V)
Vss
Vcgref 5 :Ms Vsg=3.5V E I AiFMB w; CHANNEL WIDTH
i LY?)
23
Patent Application Publication
Jul. 5, 2001
Sheet 7 0f 16 US 2001/0006479 Al
N
ra‘qg? Vdd
Vdd
Vdd
Vdd
Ehiv“Eh,IV“ Eh/MPHVHI F1)1ISAREF SAEN _|: ~MP2IW=2XMXWp1 MP7 I —----
Vss
FMPi :F\MP1‘“" :F l lref/2
:
i
i
E W: CHANNEL WIDTH L: CHANNEL LENGTH
= p
n
32
M
L=Lp1
}
MXIref
Patent Application Publication
Jul. 5, 2001
Ns
Sheet 8 0f 16 US 2001/0006479 A1
VCLAMP
M14 »/
BLREF MN1 ~
EN A ~ MN9
Vss
VBGR
Patent Application Publication
Jul. 5, 2001
—
;’
— - - - q n _ _
INVSRC :31 \ I
_ _\
Vdd
E118: II\IvsRC
MP5 I E f
81A
I 3
I
I
I
i
I
‘
'
GENERATING CIRCUIT
21: SAREF PRECRARCE CIRCuIT (“NAT'VHEI‘I
I
EN '
I
SAENn:
E
I
II 19
Sheet 9 0f 16 US 2001/0006479 A1
,?I/MPIO I
a: MPH
E I
II
EI I I
I
:LMI5
ISAENH ~wE/MN10 CIRCUIT
I
36 lISAENn-l ~IPMN11
22 /\_,
___________ _-'
23 N. REFERENCE
All MI4
CELL
\ 20: GENERATING CIRuCIT
Patent Application Publication
Jul. 5, 2001
Sheet 10 0f 16 US 2001/0006479 A1
- VBGR=1.23V - VBGR2=0.5V
- Vcgref=1.0V~2.5V
(REGULATE AT
0.1V INTERVALS)
\R3 (VARIABLE RESISTOR) XR4 Vss
FIG. 12 Na
T1
JRS
Na
fRa =
1;? ‘fRe
Nb
2 T16 1R6 .L
\
N‘E Y
J
Patent Application Publication
Jul. 5, 2001
Sheet 11 0f 16 US 2001/0006479 A1
9;E5 Ni
3.01
Eg
9::
E
92
No.2 8?
uzmEw
/55m
Patent Application Publication
Jul. 5, 2001
Sheet 12 0f 16 US 2001/0006479 A1
m Q o / E m g >QmOoEzM
