INTEL INTEL INTEL - Arduino
5
4
3
2
1
D
D
C
C EE:M.KASHI,S.VANGENT
B
B
Intel® Curie™ Module Design Document This Intel® Curie™ module design document is licensed by Intel under the terms of the Creative Commons Attribution Share-Alike License (ver. 3), subject to the following terms and conditions. The Intel Curie module design document IS PROVIDED "AS IS" AND "WITH ALL FAULTS." Intel DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED REGARDING THE INTEL CURIE MODULE DESIGN OR THIS INTEL CURIE MODULE DESIGN DOCUMENT INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Intel may make changes to the specifications, schematics, and product descriptions at any time, without notice. The customer must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. ENJOY!
A
A
INTEL
New Devices Group ARDUINO 101
EE:M.KASHI,S.VANGENT
Size
CAGE Code
Custom Monday, January 25, 2016
Scale
DWG NO
Rev
SCHEM FOR TA=H94227 Sheet
1 1
5
4
3
2
1
of
4
5
4
3
2
Power Input SEL
USB Power Input USB_5P00_PWR USB_5P00_PWR
1 2
USBDN_CONN
3 4
3
USBDP_CONN
ESD11 CLAMP 2
4.7uF 28V
DC_IN_5V_20V
DC_IN_5V_20V
ONB
A2 B2
C18
ISET
GND1 GND2
4.7uF 28V
A1 B1
VOUT1 VOUT2
OC_FLAG
R81 3K 1%
R83 1.5K 1%
C2
TRIG_TRUE_D D
U202
C1 R74 698 1%
FPF2496
C39 0.1uF 6.3V
R57 10K
1 2 3
10UF C49 10V
VDD C_DLY GND1 GND2 DOUT
5 4
R3119N050A
1
C42
3
VIN1 VIN2
C3
R31
1
S1 DAT+ S2 GND
R32 22
1
5 6
22
ESD10
D
A3 B3
R12
SH10 Short_pad
2
VBUS DAT-
V_5P00SRC_VDD1 U13
CURIE_VBUS 22
J17
TRIG_TRUE_D
CURRENT LIMITS RESISTOR VALUES 2100=500mA; 698 = 1.5A; 1100 = 1A Short for 1.5A
R82 10K 1%
R73 402 1%
2
AU-Y1007-2-R USB
1
C55 0.1uF 25V
R75 1000 1%
C54 0.1uF 25V
Trip set to 5.75V
Barrel Power Input TRIG_TRUE_D 20V tolerant 7-17VDC IN
DC_IN_JACK
DC_IN_5V_20V
DC_IN_5V_20V_FIL
V_5P00SRC_VDD1 V_5P00SRC_VDD1
C
V_3P3SRC_VDD1 C
RSX501L-20TE25 2DC-0005D200 D17
J16
TPS62153RGT U10
11 12 10 13
GND2
GND1
LM1117DTX-3.3 NOPB
1
C36 0.1uF 25V
3
2
300Ohm_100M L13 2
1
DC+
RSX501L-20TE25 D18
C50 4.7uF 28V
C12 4.7uF 28V
C16 4.7uF 28V
PVIN1 PVIN2 AVIN ENA
1 2 3 14 4
R70 10K
R77 10K
NS_A93550-116
8 9 7 R71 10K
DEF SS/TR FSW
U17
L10
SW1 SW2 SW3 VOS PG
FB AGND PGND1 PGND2 THERM
5 6 15 16 17
1
2
3
2.2uH
IN
OUT GND
C14 6.3V 22uF
2 1
C11 4.7uF 10V
10UF C13 10V
C15 0.033uF
B
B
DC_IN_5V_20V V_3P3SRC_VDD1
GENW BOARD SPECIFIC
V_5P00SRC_VDD1 J10
1 2 3 4 5 6 7 8
3,4 IO14_NEW 2,3,4,5
RST_SKETCH
N/A IOREF RESET 3V3 5V0 GND1 GND2 VIN
VDD_PLAT_3P3 R15 330
R16 330
PTS645-S-M-43-SMTR92-LFS
3 4
RESET SKETCH
U16
FaultD15
3,4,5
1 2
ATPSCK/IO2_3V_IO13
2,3,4,5 R10
330
NC VCC A GND Y
5 1K 4
D13 GREEN R14 MARK "L"
SN74AUP1G34DBVR R65 200K
RXLED 3 RST_SKETCH
1 2 3
SML-P11UTT86
100 R23 C41 33pF 25V
A
VDD_PLAT_3P3 GREEN TXLED 3
8 PIN SOCKET
SW12
Com D14
Power D10 GREEN A
PTS645-S-M-43-SMTR92-LFS SW10
1 2
100 R13
3 4
INTEL
M_RESET 3 C19 33pF 25V
Master reset-
New Devices Group ARDUINO 101
EE:M.KASHI,S.VANGENT
Size
CAGE Code
Custom Monday, January 25, 2016
Scale
DWG NO
Rev
SCHEM FOR TA=H94227 Sheet
1 2
5
4
3
2
1
of
4
5
4
3
VDD_PLAT_3P3
GPIO/AIN_10 GPIO/AIN_11 GPIO/AIN_12 GPIO/AIN_13 GPIO/AIN_14 UART1_RTS/AN09
U12D
K23 M23 M21 L24 L23
DBG_AP_JTAG_TRST_N DBG_AP_JTAG_TDO 3 DBG_AP_JTAG_TDI 3 DBG_AP_JTAG_TMS 3 DBG_AP_JTAG_TCK 3
3
PWM0_OUT PWM1_OUT PWM2_OUT PWM3_OUT
R30 10K
MRESET_B ATP_RST_B POR_B PLT_CLK_0
VDD_BLE_SEN BLE_DEC2
D23 B4 E23
M_RESET 2
BLE_RF
E3
Antenna
U12B
COMP_AREF AON_IO_VCC ADC_3P3_VCC CMP_3P3_VCC BUCK_VSEL
ATP_TRST_B ATP_TDO ATP_TDI ATP_TMS ATP_TCK
1
I/O
Power and reset
D
2
MISO1/IO9_3V_IO8
BLE_SDA BLE_SCL
3,4,5
BLE_SWDIO BLE_SW_CLK BT_GPIO
CURIE_V3
VDD_PLAT_3P3
G22 E21 H23 H22 K2
J18
1 22
J2 H21 H2 L2 C24 K21
AD10/SS2_3V_AD0 AD11/SS3_3V_AD1 AD12/SS4_3V_AD2 AD13/SS5_3V_AD3 AD14/SS6_3V_AD4 AD09/SS1_3V_AD5
H1 G2 G1 F2
PWM0/SS10_3V_IO3 PWM1/SS11_3V_IO5 PWM2/SS12_3V_IO6 PWM3/SS13_3V_IO9
C20
C21
C22
10UF
10UF
0.1uF
NS_A93552-004 R18 0R
D
3 BT_ANT_50
3,4,5 3,4,5 4,5 4,5
C38 NP
C47 NP
C46 NP
C
USB_DM USB_DP VIN_1 VIN_2 BATT_TEMP SW_FG_VBATT PV_BATT CHG_STATUS BATT_ISET VSYS AVD_OPM_2P6 AGND GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8
0R
K4
R59
J23 J24
JTAG 1
NOR_SWD_SDA NOR_SWD_SCL
3 3
3 5
USBDN_CONN USBDP_CONN
K24 N21
2,3 2,3
I2C1_SS_SCL I2C1_SS_SDA
C17 4.7uF 28V
N22 P21
VSYS
I2C0_SCL I2C0_SDA
PV_BATT
I2C1_SCL I2C1_SDA
M1 M22 L22 L4 J1
ATP_SPI_S_MOSI ATP_SPI_S_MISO ATP_SPI_S_SCK ATP_SPI_S_CS
L21 P1 A2 P22 C23 G24 G21 A24 P24
C25 4.7uF
C26
C23
0.1uF
UART1_TX UART1_RX UART1_CTS
R24 NP
6AXIS_SDA 6AXIS_SCL 6AXIS_INT2 I2S_RXD I2S_RSCK I2S_RWS I2S_TSCK I2S_TWS I2S_TXD
VSYS U12A
3V Buck not used
P2 N2
ESR2_LX
N1
A
BUCK_VOUT VDD_HOST_1P8 ESR3_LX
C45
C31
C32
0.1uF
4.7uF
0.1uF
SPI0_M_MOSI SPI0_M_MISO SPI0_M_SCK SPI0_M_CS0 SPI0_M_CS1 SPI0_M_CS2
N4 M2
SPI1_M_MOSI SPI1_M_MISO SPI1_M_SCK SPI1_M_CS0 SPI1_M_CS1 SPI1_M_CS2 SPI1_M_CS3
1.8V Buck not used
M4 C33
C28 0.1uF
L1
SPI0_SS_MOSI SPI0_SS_MISO SPI0_SS_SCK SPI0_SS_CS0 SPI0_SS_CS1 SPI0_SS_CS2 SPI0_SS_CS3
K1 P3
V_1P8_ESR3
P4
CURIE_V3
GND1 GND2
GND3
2 C35
C48
0.1uF
0.1uF
1 22uH L12 C29 4.7uF
ATP_INT0 ATP_INT1 ATP_INT2 ATP_INT3
C30 0.1uF
DBG_AP_JTAG_TCK
6
TDO
RTCK/KEY
DBG_AP_JTAG_TMS 3
4
TCLK
DBG_AP_JTAG_TDO
8
TDI
DBG_AP_JTAG_TDI
10
RESET
3 3 3
DBG_AP_JTAG_TRST_N
3 C
20021111-00010T4LF
F1 E2 M24 P23
V_3P3SRC_VDD1
VDD_PLAT_3P3 0R
E1 D2
R58
A93552-004 VSYS
F4 G3 E4 F3
ATPMOSI/IO3_3V_IO11 3,4,5 ATPMISO/IO1_3V_IO12 3,4,5 ATPSCK/IO2_3V_IO13 2,3,4,5 ATPSS/IO0_3V_IO10 3,4,5
0R
J21 K22 J22
Test Points
TXD1/SS8_3V_IO1 4,5 RXD1/SS9_3V_IO0 4,5 ATPCTS/IO9_3V_IO14 2,4
3 NOR_SWD_SDA
A21 A22 A23 A3 B2 B1 C2 C1 D1
E22 B22 C21 D22 D21 B21 C22
PWM1/SS11_3V_IO5 3,4,5 MISO1/IO9_3V_IO8 3,4,5 PWM0/SS10_3V_IO3 3,4,5 I2S_TSCK/IO18_3V_IO2 4,5 I2S_TWS/IO19_3V_IO4 4,5 I2S_TXD/IO20_3V_IO7 4,5
3 DBG_AP_JTAG_TCK
TPB10
1
TPB11
SP0_MOSI_MEM SP0_MISO_MEM SP0_CLK_MEM SP0_CS0_MEM SP0_WP_MEM~ RXLED 2
TPB12
1
TPB13
1
3 DBG_AP_JTAG_TDI
4,5 4,5 4,5 4,5 4,5
1
1
3 DBG_AP_JTAG_TDO
1
3 DBG_AP_JTAG_TRST_N
1 1
B
TPB14 TPB15 TPB16 TPB17 TPB18
USB_5P00_PWR
1
TPB19
DC_IN_JACK
1
ATPMOSI/IO3_3V_IO11 3,4,5 ATPMISO/IO1_3V_IO12 3,4,5 ATPSCK/IO2_3V_IO13 2,3,4,5 ATPSS/IO0_3V_IO10 3,4,5 TXLED 2
TPB20
VDD_PLAT_3P3
1 1
M3 J3 J4 H4 H3 K3 G4 F22 N3 L3 F21
1
Test JTAG 3 DBG_AP_JTAG_TMS
2,3 USBDN_CONN 2,3 USBDP_CONN
D3 D4 C4 B3 A4 C3
R63
A93552-004
U12E
4.7uF
LDO1P8_VOUT
4,5 4,5
CURIE_V3
VDD_PLAT_1P8
ESR2_VBATT VDD_PLAT_1P8
SCL0_SS_3V_AD5 SDA0_SS_3V_AD4
2
TMS
3 NOR_SWD_SCL
B
ESR1_LX
N24 N23
VCC
C24
10UF 0.1uF 10V
CURIE_V3
ESR1_VBATT VDD_PLAT_3P3
9
U12F
I2C0_SS_SCL I2C0_SS_SDA
Internal ANT
J15
7
USB DIFF SIGNALS
RLC11 NP
VDD_PLAT_3P3
CURIE_V3 U12C
C37 4.7nH
BT_ANT_50 3 BT_AOUT_50
CURIE_VBUS
VDD_USB
1.2pF RLC10
0R R19
B23 F23 E24 D24 B24
MHF4 NS_G42632-002
10pF RLC12
H24 G23 F24
4,5 4,5 4,5 4,5 4,5 4,5
4 3 2
R35
1
TPB21 TPB22 TPB23 A
RST_SKETCH_3V
2,4,5
INTEL
New Devices Group ARDUINO 101
EE:M.KASHI,S.VANGENT
CURIE_V3
Size
CAGE Code
Custom Monday, January 25, 2016
Scale
DWG NO
Rev
SCHEM FOR TA=H94227 Sheet
A 3
5
4
3
2
1
of
4
5
4
3
2
1
VDD_PLAT_3P3 VDD_PLAT_3P3
V_3P5_VREFA
V_5P00SRC_VDD1
U201 1.8K
10K R33
R34
1
3,5 SP0_CS0_MEM 3,5 SP0_MISO_MEM
C51 0.1uF
D
V_3P5_VREFA U15
3,5 SCL0_SS_3V_AD5 3,5 SDA0_SS_3V_AD4 3,5 3,5 3,5 3,5 3,5 3,5
AD09/SS1_3V_AD5 AD14/SS6_3V_AD4 AD13/SS5_3V_AD3 AD12/SS4_3V_AD2 AD11/SS3_3V_AD1 AD10/SS2_3V_AD0
1 2 3 4 5 6 7 8 9 10
GND VREF_A A1 A2 A3 A4 A5 A6 A7 A8
LSF0108
EN VREF_B B1 B2 B3 B4 B5 B6 B7 B8
V_5P00SRC_VDD1 200K R27
20 19 18 17 16 15 14 13 12 11
C44 0.1uF
MOSI
6
3,5 SP0_CLK_MEM
7
HOLD
WP
5
3,5 SP0_MOSI_MEM
8
VCC
MISO
3
3,5 SP0_WP_MEM~
C43 0.1uF
CS
2
D
SCK
4
VSS
W25Q16DVSSIG R62 10K
AD5_SCL 3,4,5 AD4_SDA 3,4,5 AD3 3,4,5 AD2 3,4,5 AD1 3,4,5 AD0 3,4,5
J14 3,4,5 3,4,5 3,4,5 3,4,5 3,4,5 3,4,5
6 5 4 3 2 1
AD5_SCL AD4_SDA AD3 AD2 AD1 AD0
AD5/SCL AD4/SDA AD3 AD2 AD1 AD0 6 PIN SOCKET
C
C
C52 0.1uF
V_3P5_VREFA
2,3,5 2,3 2,3,5 3,5 3,5 3,5 3,5 3,5
RST_SKETCH_3V ATPCTS/IO9_3V_IO14 ATPSCK/IO2_3V_IO13 ATPMISO/IO1_3V_IO12 ATPMOSI/IO3_3V_IO11 ATPSS/IO0_3V_IO10 PWM3/SS13_3V_IO9 MISO1/IO9_3V_IO8
1 2 3 4 5 6 7 8 9 10
U14
GND VREF_A A1 A2 A3 A4 A5 A6 A7 A8
LSF0108
EN VREF_B B1 B2 B3 B4 B5 B6 B7 B8
20 19 18 17 16 15 14 13 12 11
V_5P00SRC_VDD1 J12
V_5P00SRC_VDD1 200K R28
RST_SKETCH 2,3,4,5 IO14_NEW 2,3 IO13/SCK 2,3,4,5 IO12/MISO 3,4,5 IO11/MOSI 3,4,5 IO10/SS 3,4,5 IO9/PWM3 3,4,5 IO8 3,4,5
3,4,5 2,3,4,5 2,3,4,5
1 3 5
IO12/MISO IO13/SCK RST_SKETCH
MISO SCK RESET
5V0 MOSI GND
2 4 6
IO11/MOSI
3,4,5
2X3 PIN HEADER AREF J11 3,4,5 3,4,5 2,3,4,5 3,4,5 3,4,5 3,4,5 3,4,5 3,4,5
AD5_SCL AD4_SDA IO13/SCK IO12/MISO IO11/MOSI IO10/SS IO9/PWM3 IO8
10 9 8 7 6 5 4 3 2 1
AD5/SCL AD4/SDA AREF GND SCK MISO MOSI/PWM SS/PWM IO9/PWM IO8 10 PIN SOCKET
B
B
Intel® Curie™ Design Document C53 0.1uF
V_3P5_VREFA
3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5
I2S_TXD/IO20_3V_IO7 PWM2/SS12_3V_IO6 PWM1/SS11_3V_IO5 I2S_TWS/IO19_3V_IO4 PWM0/SS10_3V_IO3 I2S_TSCK/IO18_3V_IO2 TXD1/SS8_3V_IO1 RXD1/SS9_3V_IO0
1 2 3 4 5 6 7 8 9 10
U11
GND VREF_A A1 A2 A3 A4 A5 A6 A7 A8
LSF0108
EN VREF_B B1 B2 B3 B4 B5 B6 B7 B8
20 19 18 17 16 15 14 13 12 11
V_5P00SRC_VDD1 200K R29 J13 IO7 3,4,5 IO6/PWM2 3,4,5 IO5/PWM1 3,4,5 IO4 3,4,5 IO3/PWM0 3,4,5 IO2 3,4,5 IO1/TXD 3,4,5 IO0/RXD 3,4,5
3,4,5 3,4,5 3,4,5 3,4,5 3,4,5 3,4,5 3,4,5 3,4,5
8 7 6 5 4 3 2 1
IO7 IO6/PWM2 IO5/PWM1 IO4 IO3/PWM0 IO2 IO1/TXD IO0/RXD
A
IO7 IO6/PWM IO5/PWM IO4 IO3/PWM IO2 IO1/TXD IO0/RXD
This Intel® Curie™ design document is licensed by Intel under the terms of the Creative Commons Attribution Share-Alike License (ver. 3), subject to the following terms and conditions. The Intel® Curie™ design document IS PROVIDED "AS IS" AND "WITH ALL FAULTS." Intel DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED REGARDING THE CURIE DESIGN OR THIS CURIE DESIGN DOCUMENT INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Intel® may make changes to the specifications, schematics and product descriptions at any time, without notice. The Customer must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel® reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. ENJOY!
A
8 PIN SOCKET
INTEL
New Devices Group ARDUINO 101
EE:M.KASHI,S.VANGENT
Size
CAGE Code
Custom Monday, January 25, 2016
Scale
DWG NO
Rev 1
SCHEM FOR TA=H94227 Sheet 4
5
4
3
2
1
of
4
4
3
2
1
D
D
C
C EE:M.KASHI,S.VANGENT
B
B
Intel® Curie™ Module Design Document This Intel® Curie™ module design document is licensed by Intel under the terms of the Creative Commons Attribution Share-Alike License (ver. 3), subject to the following terms and conditions. The Intel Curie module design document IS PROVIDED "AS IS" AND "WITH ALL FAULTS." Intel DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED REGARDING THE INTEL CURIE MODULE DESIGN OR THIS INTEL CURIE MODULE DESIGN DOCUMENT INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Intel may make changes to the specifications, schematics, and product descriptions at any time, without notice. The customer must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. ENJOY!
A
A
INTEL
New Devices Group ARDUINO 101
EE:M.KASHI,S.VANGENT
Size
CAGE Code
Custom Monday, January 25, 2016
Scale
DWG NO
Rev
SCHEM FOR TA=H94227 Sheet
1 1
5
4
3
2
1
of
4
5
4
3
2
Power Input SEL
USB Power Input USB_5P00_PWR USB_5P00_PWR
1 2
USBDN_CONN
3 4
3
USBDP_CONN
ESD11 CLAMP 2
4.7uF 28V
DC_IN_5V_20V
DC_IN_5V_20V
ONB
A2 B2
C18
ISET
GND1 GND2
4.7uF 28V
A1 B1
VOUT1 VOUT2
OC_FLAG
R81 3K 1%
R83 1.5K 1%
C2
TRIG_TRUE_D D
U202
C1 R74 698 1%
FPF2496
C39 0.1uF 6.3V
R57 10K
1 2 3
10UF C49 10V
VDD C_DLY GND1 GND2 DOUT
5 4
R3119N050A
1
C42
3
VIN1 VIN2
C3
R31
1
S1 DAT+ S2 GND
R32 22
1
5 6
22
ESD10
D
A3 B3
R12
SH10 Short_pad
2
VBUS DAT-
V_5P00SRC_VDD1 U13
CURIE_VBUS 22
J17
TRIG_TRUE_D
CURRENT LIMITS RESISTOR VALUES 2100=500mA; 698 = 1.5A; 1100 = 1A Short for 1.5A
R82 10K 1%
R73 402 1%
2
AU-Y1007-2-R USB
1
C55 0.1uF 25V
R75 1000 1%
C54 0.1uF 25V
Trip set to 5.75V
Barrel Power Input TRIG_TRUE_D 20V tolerant 7-17VDC IN
DC_IN_JACK
DC_IN_5V_20V
DC_IN_5V_20V_FIL
V_5P00SRC_VDD1 V_5P00SRC_VDD1
C
V_3P3SRC_VDD1 C
RSX501L-20TE25 2DC-0005D200 D17
J16
TPS62153RGT U10
11 12 10 13
GND2
GND1
LM1117DTX-3.3 NOPB
1
C36 0.1uF 25V
3
2
300Ohm_100M L13 2
1
DC+
RSX501L-20TE25 D18
C50 4.7uF 28V
C12 4.7uF 28V
C16 4.7uF 28V
PVIN1 PVIN2 AVIN ENA
1 2 3 14 4
R70 10K
R77 10K
NS_A93550-116
8 9 7 R71 10K
DEF SS/TR FSW
U17
L10
SW1 SW2 SW3 VOS PG
FB AGND PGND1 PGND2 THERM
5 6 15 16 17
1
2
3
2.2uH
IN
OUT GND
C14 6.3V 22uF
2 1
C11 4.7uF 10V
10UF C13 10V
C15 0.033uF
B
B
DC_IN_5V_20V V_3P3SRC_VDD1
GENW BOARD SPECIFIC
V_5P00SRC_VDD1 J10
1 2 3 4 5 6 7 8
3,4 IO14_NEW 2,3,4,5
RST_SKETCH
N/A IOREF RESET 3V3 5V0 GND1 GND2 VIN
VDD_PLAT_3P3 R15 330
R16 330
PTS645-S-M-43-SMTR92-LFS
3 4
RESET SKETCH
U16
FaultD15
3,4,5
1 2
ATPSCK/IO2_3V_IO13
2,3,4,5 R10
330
NC VCC A GND Y
5 1K 4
D13 GREEN R14 MARK "L"
SN74AUP1G34DBVR R65 200K
RXLED 3 RST_SKETCH
1 2 3
SML-P11UTT86
100 R23 C41 33pF 25V
A
VDD_PLAT_3P3 GREEN TXLED 3
8 PIN SOCKET
SW12
Com D14
Power D10 GREEN A
PTS645-S-M-43-SMTR92-LFS SW10
1 2
100 R13
3 4
INTEL
M_RESET 3 C19 33pF 25V
Master reset-
New Devices Group ARDUINO 101
EE:M.KASHI,S.VANGENT
Size
CAGE Code
Custom Monday, January 25, 2016
Scale
DWG NO
Rev
SCHEM FOR TA=H94227 Sheet
1 2
5
4
3
2
1
of
4
5
4
3
VDD_PLAT_3P3
GPIO/AIN_10 GPIO/AIN_11 GPIO/AIN_12 GPIO/AIN_13 GPIO/AIN_14 UART1_RTS/AN09
U12D
K23 M23 M21 L24 L23
DBG_AP_JTAG_TRST_N DBG_AP_JTAG_TDO 3 DBG_AP_JTAG_TDI 3 DBG_AP_JTAG_TMS 3 DBG_AP_JTAG_TCK 3
3
PWM0_OUT PWM1_OUT PWM2_OUT PWM3_OUT
R30 10K
MRESET_B ATP_RST_B POR_B PLT_CLK_0
VDD_BLE_SEN BLE_DEC2
D23 B4 E23
M_RESET 2
BLE_RF
E3
Antenna
U12B
COMP_AREF AON_IO_VCC ADC_3P3_VCC CMP_3P3_VCC BUCK_VSEL
ATP_TRST_B ATP_TDO ATP_TDI ATP_TMS ATP_TCK
1
I/O
Power and reset
D
2
MISO1/IO9_3V_IO8
BLE_SDA BLE_SCL
3,4,5
BLE_SWDIO BLE_SW_CLK BT_GPIO
CURIE_V3
VDD_PLAT_3P3
G22 E21 H23 H22 K2
J18
1 22
J2 H21 H2 L2 C24 K21
AD10/SS2_3V_AD0 AD11/SS3_3V_AD1 AD12/SS4_3V_AD2 AD13/SS5_3V_AD3 AD14/SS6_3V_AD4 AD09/SS1_3V_AD5
H1 G2 G1 F2
PWM0/SS10_3V_IO3 PWM1/SS11_3V_IO5 PWM2/SS12_3V_IO6 PWM3/SS13_3V_IO9
C20
C21
C22
10UF
10UF
0.1uF
NS_A93552-004 R18 0R
D
3 BT_ANT_50
3,4,5 3,4,5 4,5 4,5
C38 NP
C47 NP
C46 NP
C
USB_DM USB_DP VIN_1 VIN_2 BATT_TEMP SW_FG_VBATT PV_BATT CHG_STATUS BATT_ISET VSYS AVD_OPM_2P6 AGND GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8
0R
K4
R59
J23 J24
JTAG 1
NOR_SWD_SDA NOR_SWD_SCL
3 3
3 5
USBDN_CONN USBDP_CONN
K24 N21
2,3 2,3
I2C1_SS_SCL I2C1_SS_SDA
C17 4.7uF 28V
N22 P21
VSYS
I2C0_SCL I2C0_SDA
PV_BATT
I2C1_SCL I2C1_SDA
M1 M22 L22 L4 J1
ATP_SPI_S_MOSI ATP_SPI_S_MISO ATP_SPI_S_SCK ATP_SPI_S_CS
L21 P1 A2 P22 C23 G24 G21 A24 P24
C25 4.7uF
C26
C23
0.1uF
UART1_TX UART1_RX UART1_CTS
R24 NP
6AXIS_SDA 6AXIS_SCL 6AXIS_INT2 I2S_RXD I2S_RSCK I2S_RWS I2S_TSCK I2S_TWS I2S_TXD
VSYS U12A
3V Buck not used
P2 N2
ESR2_LX
N1
A
BUCK_VOUT VDD_HOST_1P8 ESR3_LX
C45
C31
C32
0.1uF
4.7uF
0.1uF
SPI0_M_MOSI SPI0_M_MISO SPI0_M_SCK SPI0_M_CS0 SPI0_M_CS1 SPI0_M_CS2
N4 M2
SPI1_M_MOSI SPI1_M_MISO SPI1_M_SCK SPI1_M_CS0 SPI1_M_CS1 SPI1_M_CS2 SPI1_M_CS3
1.8V Buck not used
M4 C33
C28 0.1uF
L1
SPI0_SS_MOSI SPI0_SS_MISO SPI0_SS_SCK SPI0_SS_CS0 SPI0_SS_CS1 SPI0_SS_CS2 SPI0_SS_CS3
K1 P3
V_1P8_ESR3
P4
CURIE_V3
GND1 GND2
GND3
2 C35
C48
0.1uF
0.1uF
1 22uH L12 C29 4.7uF
ATP_INT0 ATP_INT1 ATP_INT2 ATP_INT3
C30 0.1uF
DBG_AP_JTAG_TCK
6
TDO
RTCK/KEY
DBG_AP_JTAG_TMS 3
4
TCLK
DBG_AP_JTAG_TDO
8
TDI
DBG_AP_JTAG_TDI
10
RESET
3 3 3
DBG_AP_JTAG_TRST_N
3 C
20021111-00010T4LF
F1 E2 M24 P23
V_3P3SRC_VDD1
VDD_PLAT_3P3 0R
E1 D2
R58
A93552-004 VSYS
F4 G3 E4 F3
ATPMOSI/IO3_3V_IO11 3,4,5 ATPMISO/IO1_3V_IO12 3,4,5 ATPSCK/IO2_3V_IO13 2,3,4,5 ATPSS/IO0_3V_IO10 3,4,5
0R
J21 K22 J22
Test Points
TXD1/SS8_3V_IO1 4,5 RXD1/SS9_3V_IO0 4,5 ATPCTS/IO9_3V_IO14 2,4
3 NOR_SWD_SDA
A21 A22 A23 A3 B2 B1 C2 C1 D1
E22 B22 C21 D22 D21 B21 C22
PWM1/SS11_3V_IO5 3,4,5 MISO1/IO9_3V_IO8 3,4,5 PWM0/SS10_3V_IO3 3,4,5 I2S_TSCK/IO18_3V_IO2 4,5 I2S_TWS/IO19_3V_IO4 4,5 I2S_TXD/IO20_3V_IO7 4,5
3 DBG_AP_JTAG_TCK
TPB10
1
TPB11
SP0_MOSI_MEM SP0_MISO_MEM SP0_CLK_MEM SP0_CS0_MEM SP0_WP_MEM~ RXLED 2
TPB12
1
TPB13
1
3 DBG_AP_JTAG_TDI
4,5 4,5 4,5 4,5 4,5
1
1
3 DBG_AP_JTAG_TDO
1
3 DBG_AP_JTAG_TRST_N
1 1
B
TPB14 TPB15 TPB16 TPB17 TPB18
USB_5P00_PWR
1
TPB19
DC_IN_JACK
1
ATPMOSI/IO3_3V_IO11 3,4,5 ATPMISO/IO1_3V_IO12 3,4,5 ATPSCK/IO2_3V_IO13 2,3,4,5 ATPSS/IO0_3V_IO10 3,4,5 TXLED 2
TPB20
VDD_PLAT_3P3
1 1
M3 J3 J4 H4 H3 K3 G4 F22 N3 L3 F21
1
Test JTAG 3 DBG_AP_JTAG_TMS
2,3 USBDN_CONN 2,3 USBDP_CONN
D3 D4 C4 B3 A4 C3
R63
A93552-004
U12E
4.7uF
LDO1P8_VOUT
4,5 4,5
CURIE_V3
VDD_PLAT_1P8
ESR2_VBATT VDD_PLAT_1P8
SCL0_SS_3V_AD5 SDA0_SS_3V_AD4
2
TMS
3 NOR_SWD_SCL
B
ESR1_LX
N24 N23
VCC
C24
10UF 0.1uF 10V
CURIE_V3
ESR1_VBATT VDD_PLAT_3P3
9
U12F
I2C0_SS_SCL I2C0_SS_SDA
Internal ANT
J15
7
USB DIFF SIGNALS
RLC11 NP
VDD_PLAT_3P3
CURIE_V3 U12C
C37 4.7nH
BT_ANT_50 3 BT_AOUT_50
CURIE_VBUS
VDD_USB
1.2pF RLC10
0R R19
B23 F23 E24 D24 B24
MHF4 NS_G42632-002
10pF RLC12
H24 G23 F24
4,5 4,5 4,5 4,5 4,5 4,5
4 3 2
R35
1
TPB21 TPB22 TPB23 A
RST_SKETCH_3V
2,4,5
INTEL
New Devices Group ARDUINO 101
EE:M.KASHI,S.VANGENT
CURIE_V3
Size
CAGE Code
Custom Monday, January 25, 2016
Scale
DWG NO
Rev
SCHEM FOR TA=H94227 Sheet
A 3
5
4
3
2
1
of
4
5
4
3
2
1
VDD_PLAT_3P3 VDD_PLAT_3P3
V_3P5_VREFA
V_5P00SRC_VDD1
U201 1.8K
10K R33
R34
1
3,5 SP0_CS0_MEM 3,5 SP0_MISO_MEM
C51 0.1uF
D
V_3P5_VREFA U15
3,5 SCL0_SS_3V_AD5 3,5 SDA0_SS_3V_AD4 3,5 3,5 3,5 3,5 3,5 3,5
AD09/SS1_3V_AD5 AD14/SS6_3V_AD4 AD13/SS5_3V_AD3 AD12/SS4_3V_AD2 AD11/SS3_3V_AD1 AD10/SS2_3V_AD0
1 2 3 4 5 6 7 8 9 10
GND VREF_A A1 A2 A3 A4 A5 A6 A7 A8
LSF0108
EN VREF_B B1 B2 B3 B4 B5 B6 B7 B8
V_5P00SRC_VDD1 200K R27
20 19 18 17 16 15 14 13 12 11
C44 0.1uF
MOSI
6
3,5 SP0_CLK_MEM
7
HOLD
WP
5
3,5 SP0_MOSI_MEM
8
VCC
MISO
3
3,5 SP0_WP_MEM~
C43 0.1uF
CS
2
D
SCK
4
VSS
W25Q16DVSSIG R62 10K
AD5_SCL 3,4,5 AD4_SDA 3,4,5 AD3 3,4,5 AD2 3,4,5 AD1 3,4,5 AD0 3,4,5
J14 3,4,5 3,4,5 3,4,5 3,4,5 3,4,5 3,4,5
6 5 4 3 2 1
AD5_SCL AD4_SDA AD3 AD2 AD1 AD0
AD5/SCL AD4/SDA AD3 AD2 AD1 AD0 6 PIN SOCKET
C
C
C52 0.1uF
V_3P5_VREFA
2,3,5 2,3 2,3,5 3,5 3,5 3,5 3,5 3,5
RST_SKETCH_3V ATPCTS/IO9_3V_IO14 ATPSCK/IO2_3V_IO13 ATPMISO/IO1_3V_IO12 ATPMOSI/IO3_3V_IO11 ATPSS/IO0_3V_IO10 PWM3/SS13_3V_IO9 MISO1/IO9_3V_IO8
1 2 3 4 5 6 7 8 9 10
U14
GND VREF_A A1 A2 A3 A4 A5 A6 A7 A8
LSF0108
EN VREF_B B1 B2 B3 B4 B5 B6 B7 B8
20 19 18 17 16 15 14 13 12 11
V_5P00SRC_VDD1 J12
V_5P00SRC_VDD1 200K R28
RST_SKETCH 2,3,4,5 IO14_NEW 2,3 IO13/SCK 2,3,4,5 IO12/MISO 3,4,5 IO11/MOSI 3,4,5 IO10/SS 3,4,5 IO9/PWM3 3,4,5 IO8 3,4,5
3,4,5 2,3,4,5 2,3,4,5
1 3 5
IO12/MISO IO13/SCK RST_SKETCH
MISO SCK RESET
5V0 MOSI GND
2 4 6
IO11/MOSI
3,4,5
2X3 PIN HEADER AREF J11 3,4,5 3,4,5 2,3,4,5 3,4,5 3,4,5 3,4,5 3,4,5 3,4,5
AD5_SCL AD4_SDA IO13/SCK IO12/MISO IO11/MOSI IO10/SS IO9/PWM3 IO8
10 9 8 7 6 5 4 3 2 1
AD5/SCL AD4/SDA AREF GND SCK MISO MOSI/PWM SS/PWM IO9/PWM IO8 10 PIN SOCKET
B
B
Intel® Curie™ Design Document C53 0.1uF
V_3P5_VREFA
3,5 3,5 3,5 3,5 3,5 3,5 3,5 3,5
I2S_TXD/IO20_3V_IO7 PWM2/SS12_3V_IO6 PWM1/SS11_3V_IO5 I2S_TWS/IO19_3V_IO4 PWM0/SS10_3V_IO3 I2S_TSCK/IO18_3V_IO2 TXD1/SS8_3V_IO1 RXD1/SS9_3V_IO0
1 2 3 4 5 6 7 8 9 10
U11
GND VREF_A A1 A2 A3 A4 A5 A6 A7 A8
LSF0108
EN VREF_B B1 B2 B3 B4 B5 B6 B7 B8
20 19 18 17 16 15 14 13 12 11
V_5P00SRC_VDD1 200K R29 J13 IO7 3,4,5 IO6/PWM2 3,4,5 IO5/PWM1 3,4,5 IO4 3,4,5 IO3/PWM0 3,4,5 IO2 3,4,5 IO1/TXD 3,4,5 IO0/RXD 3,4,5
3,4,5 3,4,5 3,4,5 3,4,5 3,4,5 3,4,5 3,4,5 3,4,5
8 7 6 5 4 3 2 1
IO7 IO6/PWM2 IO5/PWM1 IO4 IO3/PWM0 IO2 IO1/TXD IO0/RXD
A
IO7 IO6/PWM IO5/PWM IO4 IO3/PWM IO2 IO1/TXD IO0/RXD
This Intel® Curie™ design document is licensed by Intel under the terms of the Creative Commons Attribution Share-Alike License (ver. 3), subject to the following terms and conditions. The Intel® Curie™ design document IS PROVIDED "AS IS" AND "WITH ALL FAULTS." Intel DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED REGARDING THE CURIE DESIGN OR THIS CURIE DESIGN DOCUMENT INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Intel® may make changes to the specifications, schematics and product descriptions at any time, without notice. The Customer must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel® reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. ENJOY!
A
8 PIN SOCKET
INTEL
New Devices Group ARDUINO 101
EE:M.KASHI,S.VANGENT
Size
CAGE Code
Custom Monday, January 25, 2016
Scale
DWG NO
Rev 1
SCHEM FOR TA=H94227 Sheet 4
5
4
3
2
1
of
4
