KU Leuven - Semantic Scholar
Designing reliable analog circuits in an unreliable world Georges Gielen ESAT–MICAS, KU Leuven gielen@esat kuleuven be [email protected]
© G. Gielen, KU Leuven
INESC Jan 2013
1
KU Leuven Rector: M. Waer ± 42000 Students
Faculty of Engineering Dean: M. Steyaert ± 3500 Students
Electrical Engineering: ESAT
Head: G. Gielen PSI P.Suetens P.Wambacq L.Van Eycken L.Van Gool D.Van Compernolle H.Vanhamme F. Maes INESC Jan 2013
± 350 BSc/ 200 MSc/ 350PhD
SCD J.Vandewalle B.De Moor S.Van Huffel M.Moonen A.Barbé J.Engelen B.Preneel I. Verbauwhede Y. Moreau
MICAS
TELEMIC
ELECTA
G. Gielen M. Steyaert R. Puers W. Dehaene P. Reynaert M. Verhelst
A.Van de Cappelle E.Van Lil B.Nauwerlaers G.Vandenbosch D. Schreurs S. Pollin
R.Belmans G.Deconinck J. Driesen D. Van Hertem
© G. Gielen, KU Leuven
2
1
MICAS: the numbers http://www.esat.kuleuven.be/micas/
research focus
on IC design, incl CAD incl.
design methodologies & CAD 13%
6 full-time professors
• 3 are Fellow of IEEE • ~55 Ph.D. students (@ ESAT) • ~25 Ph.D. students (@ IMEC)
biomedical and MEMS 24%
high-speed analog & mm-wave
4 affiliated professors
low-power digital & memories
20% analog & mixed-signal
9.5 tech/admin staff
20%
22%
created 6 spinoffs in last 14 years INESC Jan 2013
© G. Gielen, KU Leuven
3
Contents
Motivation Aging modeling Reliability simulation Reliability-aware Reliability aware or resilient design Conclusions INESC Jan 2013
© G. Gielen, KU Leuven
4
2
Evolution in technology traditional scaling philosophy:
INESC Jan 2013
more for less
© G. Gielen, KU Leuven
5
Result of scaling same function, smaller, faster, less power
INESC Jan 2013
© G. Gielen, KU Leuven
6
3
Good news from Intel & co
CMOS scaling will continue for at least two more technology nodes beyond 32 nm !! INESC Jan 2013
© G. Gielen, KU Leuven
7
Variability line edge roughness (LER)
random dopant fluctuations (RDF)
[Frank, IBM]
INESC Jan 2013
© G. Gielen, KU Leuven
8
4
Analog circuits and matching
mismatch inversely proportional to area :
2 ( VT )
AV2T WL
2 2 P 24 Cox AVT 0 f DR
Speed Accuracy 2 Power [Vittoz AICSP 1994]
techn const
[Kinget CICC 1996]
© G. Gielen, KU Leuven
INESC Jan 2013
9
Benefit from process scaling ?
D
D
A
A
analog does not really become smaller !! no real cost benefit for analog INESC Jan 2013
© G. Gielen, KU Leuven
10
5
Analog design versus scaling supply voltage drops • limits signal range
intrinsic gain drops : Aint INESC Jan 2013
gm g DS © G. Gielen, KU Leuven
11
ITRS
INESC Jan 2013
© G. Gielen, KU Leuven
12
6
Importance of reliability
guarantee product lifetime e.g. safety-critical applications in an increasingly unrealible context technology process environment without huge overdesign
© G. Gielen, KU Leuven
INESC Jan 2013
13
IC reliability spatial unreliability
• manufacturing process variations • random defects
INESC Jan 2013
© G. Gielen, KU Leuven
14
7
IC reliability spatial unreliability
• manufacturing process variations • random defects temporal unreliability
• aging effects » HCI, NBTI/PBTI,
TDDB
© G. Gielen, KU Leuven
INESC Jan 2013
15
IC reliability spatial unreliability
• manufacturing process variations • random d defects d f temporal unreliability
• aging effects dynamic unreliability
• workload dependence • temperature variations • EMC INESC Jan 2013
© G. Gielen, KU Leuven
16
8
Contents
Motivation Aging modeling Reliability simulation Reliability-aware Reliability aware or resilient design Conclusions © G. Gielen, KU Leuven
INESC Jan 2013
17
Device aging effects Hot Carrier Degradation Time Dependent Dielectric
Breakdown Bias Temperature Instability circuit perf degrades with time :
VT β rout
VTH At n A f (V DS , VGS , T , L , W ,...) [Maricau ESREF 2008] INESC Jan 2013
© G. Gielen, KU Leuven
18
9
The effect of CMOS scaling > 65nm CMOS
• ‘large’ transistors • some effects can be considered
deterministic: NBTI, (PBTI), HCI
• some effects are statistical: TDDB, variability
< 65nm CMOS
• PBTI besides NBTI • `atomic’ scale transistor • everything becomes stochastic
[Maricau IEEE JETCAS 2011] [Maricau DATE 2011] INESC Jan 2013
© G. Gielen, KU Leuven
19
What do we need for analog circuits? compact models for all important unreliability effects
• include all important factors
Analog
» e.g. e g W,L, W L Vgs, Vgs Vds, Vds T, T …
• include interaction effects » e.g. Vds-Vgs for HCI
• cover a broad continuous range of values » e.g. g Vgs g = [0V [ … 1.5V], ],
Digital
W=[0.08m-10m]
• model time-varying stress effects » e.g. Vgs(t)= VGS + sin(0.5,1e6) INESC Jan 2013
© G. Gielen, KU Leuven
20
10
Hot Carrier degradation channel hot carrier • a well known phenomenon (>25 years) • interface traps due to impact ionization near drain • dominant for nMOS in saturation » high VDS » high VGS • impact at device level » VTH, , go
n+
n+
[Wang, TDMR 2007]
N IT (t ) C exp(1VGS ) exp( 2VGS )t 0.45 © G. Gielen, KU Leuven
INESC Jan 2013
21
Hot Carrier degradation model
ESAT-MICAS model
• • • •
[Maricau ESREF 2008]
based on Reaction-Diffusion (RD) model includes all important transistor parameters (Vgs, Vds, L, T) DC and AC voltage stress parameter set to be extracted for every process
INESC Jan 2013
© G. Gielen, KU Leuven
22
11
HCI model verification
[Maricau ESREF2008] INESC Jan 2013
© G. Gielen, KU Leuven
23
Negative Bias Temperature Instability recent phenomenon NBTI important for pMOS
• [also PBTI for f nMOS below 65 nm] traps due to electro-chemical reaction with SiH large VGS temperature activated relaxation phenomenon
• interface traps: permanent part • oxide traps: recoverable part impact at device level • VTH, , go INESC Jan 2013
p+
p+
[Wang, TDMR 2007]
N IT C exp(
© G. Gielen, KU Leuven
VGS
)t 0.18 24
12
Bias Temperature Instability model
[Maricau, ESSDERC 2012] INESC Jan 2013
© G. Gielen, KU Leuven
25
NBTI model verification
[Maricau Electronics Letters 2010] INESC Jan 2013
© G. Gielen, KU Leuven
26
13
Transistor aging in sub-65nm CMOS aging effects become worse, even with high-k
• EOT reduces » Eeff increases i
• new materials (high-k) » PBTI • SiO2 Interfacial Layer » NBTI, HC, TDDB remains
© G. Gielen, KU Leuven
INESC Jan 2013
27
Stochastic BTI model • individual charges can change VTH
• Poisson distribution for
number of trapped charges (N=mean number of traps) • exponential distribution for the impact of an individual defect ( = average impact) • VTH=f(Vgs,T) • V VTH)=f(1/(WL)) ) f(1/(WL))
[Maricau DATE 2011] INESC Jan 2013
© G. Gielen, KU Leuven
28
14
Time-Dependent Dielectric Breakdown PMOS and NMOS statistical phenomenon gate t currentt iincreases high VGS soft BD – Ig noise hard BD – k gate
resistance
© G. Gielen, KU Leuven
INESC Jan 2013
29
TDDB model soft breakdown
• example :
65nm technology » 1V gate stress » 10 year stress time • time to SBD follows a Weibull distribution » SBD=1.2 » =-30
F ( t SBD [Maricau DATE 2011] INESC Jan 2013
t ) 1 exp SBD SBD © G. Gielen, KU Leuven
30
15
Soft breakdown example aging
creates spread • 65nm
technology (1.7nm tox) • 0.8V gate stress • PDF after 0,1,10 year stress time [Maricau DATE 2011] INESC Jan 2013
© G. Gielen, KU Leuven
31
Contents
Motivation Aging modeling Reliability simulation Reliability-aware Reliability aware or resilient design Conclusions INESC Jan 2013
© G. Gielen, KU Leuven
32
16
Commercial tools transistor reliability analysis: □ RelXpert (now part of Cadence) □ Mentor Graphics p ELDO Reliabilityy Simulator □ Synopsys HSPICE MOSRA
The backbone of these tools is developed in the nineties and is no longer adequate! INESC Jan 2013
© G. Gielen, KU Leuven
33
Transistor model for aging
[Maricau TCAD2011 & DATE2011] INESC Jan 2013
© G. Gielen, KU Leuven
34
17
Deterministic reliability simulation
VTH
qN IT C ox
g o 1 VTH 0 I DS 0
eff
1 VGS
0 VTH
1 VTH
[Maricau DATE2009 & TCAD2010] INESC Jan 2013
© G. Gielen, KU Leuven
35
Example: LC-VCO 5 GHz and low phase noise
• high g output p swing g • high LC-tank Q-factor • protective gate capacitors (DC-bias not shown) • UMC 90nm
2 FkT L phase 10 log Ps INESC Jan 2013
2 1 / f 3 n 1 1 2 Q
© G. Gielen, KU Leuven
36
18
Nominal simulation
AC simulation shows sudden Vout degradation (due to go degradation) no frequency degradation failure due to Hot Carrier damage INESC Jan 2013
© G. Gielen, KU Leuven
37
Variability awareness process variability introduces
stress variability transistor aging + process variability = yield(t)
[Maricau TCAD2010] INESC Jan 2013
© G. Gielen, KU Leuven
38
19
Variability-aware reliability simulation
factor space exploration
screening linear model detect interactions regression interactions weakly nonlinear effects
polynomial RSM
residual analysis
error estimation
[Maricau TCAD 2010] INESC Jan 2013
© G. Gielen, KU Leuven
39
Example : VCO
[Maricau TCAD 2010] INESC Jan 2013
© G. Gielen, KU Leuven
40
20
Variability-aware reliability simulation
[Maricau TCAD 2010] INESC Jan 2013
© G. Gielen, KU Leuven
41
Example circuit : ADC
[Gielen DATE 2013] INESC Jan 2013
© G. Gielen, KU Leuven
42
21
Impact on analog circuits
INESC Jan 2013
© G. Gielen, KU Leuven
43
Aging-insensitive analog circuits • circuits that are immune to process variations » VTH VDD,nom) » e.g. phase noise of an LC-VCO □ asymmetrical y stress can result in time-dependent p mismatch » e.g. Voffset of a comparator □ time-dependent mismatch in matched transistors due to stochastic aging effects » e.g. MOS resistor in sub-45nm CMOS
INESC Jan 2013
© G. Gielen, KU Leuven
45
Contents
Motivation Aging modeling Reliability simulation Reliability-aware Reliability aware or resilient design Conclusions INESC Jan 2013
© G. Gielen, KU Leuven
46
23
Design for failure resilience intrinsically robust circuits
• worst-case overdesign to account for P/V/T corners plus overdesign p g to account for aging g g effects
• consumes extra power and area self-healing circuits
• adapt circuits at run time to compensate for the degradation » reconfiguration or retuning of the circuit » digital g calibration • required performance is maintained, though degradation is present
fully redundant circuits
INESC Jan 2013
© G. Gielen, KU Leuven
47
Self-healing (sense & react) circuits run-time monitoring and run-time adaptability
• add monitors or “canary” circuits to watch the degradation of the circuit performance p • feed information to controller • real-time reconfigure circuit (e.g. extra components) or update circuit parameters (e.g. bias) to maintain the performance KNOBS & MONITORS for analog : this is compatible with evolution towards digitallyassisted analog INESC Jan 2013
© G. Gielen, KU Leuven
48
24
Example: high-voltage line driver output driver overview:
equivalent model:
[Serneels ISSCC 2007]
Pload Rl Pload Ploss Rl Ron
INESC Jan 2013
© G. Gielen, KU Leuven
49
Example: high-voltage line driver guarantee minimum
power efficiency over lifetime breakdown monitors extra sub-transistors can be switched in
[De Wit DRVW 2008] INESC Jan 2013
© G. Gielen, KU Leuven
50
25
Self-healing test chip • on-chip power efficiency monitor □ measure output stage on-resistance (Ron=2.25Ω) □ compare p current Ron to reference resistor Rref • on-chip automatic controller • chip measurements 850um confirm real-time self-healing capabilities
1500um
[De Wit ESSCIRC 2011] INESC Jan 2013
© G. Gielen, KU Leuven
51
Failure-resilient implementation □ 90nm CMOS technology □ Pload = 10mW, 90% efficiency □ modifications for failure-resilient failure resilient operation : all included on chip !
INESC Jan 2013
© G. Gielen, KU Leuven
52
26
Measurement results
initial performance (fresh circuit): η=82%
no reconfiguration: ∆η = 5.5%
with reconfiguration: ∆ηmax < 1 %
[De Wit JSSC 2012] © G. Gielen, KU Leuven
INESC Jan 2013
53
Conclusions handling uncertainty, spatial and temporal reliability
are a big issue in nanometer CMOS design
•
more degradation effects and becoming stochastic
accurate modeling and efficient CAD tools are needed to
assist the designer
• support design for reliability • less need for guardbanding – lower design margins results have been proposed in this presentation • accurate transistor aging models for BTI, HCI and TDDB effects • efficient circuit reliability simulator methods » both nominal and stochastic effects • resilient design solutions with limited overhead » self-healing circuits through run-time adaptive sense&react principle INESC Jan 2013
© G. Gielen, KU Leuven
54
27
On-going PhD projects CAD : • reliability modeling and simulation • high-frequency high frequency circuit synthesis • automated analog behavioral modeling design :
• • • • • •
ultra-low-power wireless sensor networks autonomous sensor interfaces i imager readout d t circuits i it biomedical interface circuits digitally assisted analog resilient self-healing analog circuits
INESC Jan 2013
© G. Gielen, KU Leuven
55
28
© G. Gielen, KU Leuven
INESC Jan 2013
1
KU Leuven Rector: M. Waer ± 42000 Students
Faculty of Engineering Dean: M. Steyaert ± 3500 Students
Electrical Engineering: ESAT
Head: G. Gielen PSI P.Suetens P.Wambacq L.Van Eycken L.Van Gool D.Van Compernolle H.Vanhamme F. Maes INESC Jan 2013
± 350 BSc/ 200 MSc/ 350PhD
SCD J.Vandewalle B.De Moor S.Van Huffel M.Moonen A.Barbé J.Engelen B.Preneel I. Verbauwhede Y. Moreau
MICAS
TELEMIC
ELECTA
G. Gielen M. Steyaert R. Puers W. Dehaene P. Reynaert M. Verhelst
A.Van de Cappelle E.Van Lil B.Nauwerlaers G.Vandenbosch D. Schreurs S. Pollin
R.Belmans G.Deconinck J. Driesen D. Van Hertem
© G. Gielen, KU Leuven
2
1
MICAS: the numbers http://www.esat.kuleuven.be/micas/
research focus
on IC design, incl CAD incl.
design methodologies & CAD 13%
6 full-time professors
• 3 are Fellow of IEEE • ~55 Ph.D. students (@ ESAT) • ~25 Ph.D. students (@ IMEC)
biomedical and MEMS 24%
high-speed analog & mm-wave
4 affiliated professors
low-power digital & memories
20% analog & mixed-signal
9.5 tech/admin staff
20%
22%
created 6 spinoffs in last 14 years INESC Jan 2013
© G. Gielen, KU Leuven
3
Contents
Motivation Aging modeling Reliability simulation Reliability-aware Reliability aware or resilient design Conclusions INESC Jan 2013
© G. Gielen, KU Leuven
4
2
Evolution in technology traditional scaling philosophy:
INESC Jan 2013
more for less
© G. Gielen, KU Leuven
5
Result of scaling same function, smaller, faster, less power
INESC Jan 2013
© G. Gielen, KU Leuven
6
3
Good news from Intel & co
CMOS scaling will continue for at least two more technology nodes beyond 32 nm !! INESC Jan 2013
© G. Gielen, KU Leuven
7
Variability line edge roughness (LER)
random dopant fluctuations (RDF)
[Frank, IBM]
INESC Jan 2013
© G. Gielen, KU Leuven
8
4
Analog circuits and matching
mismatch inversely proportional to area :
2 ( VT )
AV2T WL
2 2 P 24 Cox AVT 0 f DR
Speed Accuracy 2 Power [Vittoz AICSP 1994]
techn const
[Kinget CICC 1996]
© G. Gielen, KU Leuven
INESC Jan 2013
9
Benefit from process scaling ?
D
D
A
A
analog does not really become smaller !! no real cost benefit for analog INESC Jan 2013
© G. Gielen, KU Leuven
10
5
Analog design versus scaling supply voltage drops • limits signal range
intrinsic gain drops : Aint INESC Jan 2013
gm g DS © G. Gielen, KU Leuven
11
ITRS
INESC Jan 2013
© G. Gielen, KU Leuven
12
6
Importance of reliability
guarantee product lifetime e.g. safety-critical applications in an increasingly unrealible context technology process environment without huge overdesign
© G. Gielen, KU Leuven
INESC Jan 2013
13
IC reliability spatial unreliability
• manufacturing process variations • random defects
INESC Jan 2013
© G. Gielen, KU Leuven
14
7
IC reliability spatial unreliability
• manufacturing process variations • random defects temporal unreliability
• aging effects » HCI, NBTI/PBTI,
TDDB
© G. Gielen, KU Leuven
INESC Jan 2013
15
IC reliability spatial unreliability
• manufacturing process variations • random d defects d f temporal unreliability
• aging effects dynamic unreliability
• workload dependence • temperature variations • EMC INESC Jan 2013
© G. Gielen, KU Leuven
16
8
Contents
Motivation Aging modeling Reliability simulation Reliability-aware Reliability aware or resilient design Conclusions © G. Gielen, KU Leuven
INESC Jan 2013
17
Device aging effects Hot Carrier Degradation Time Dependent Dielectric
Breakdown Bias Temperature Instability circuit perf degrades with time :
VT β rout
VTH At n A f (V DS , VGS , T , L , W ,...) [Maricau ESREF 2008] INESC Jan 2013
© G. Gielen, KU Leuven
18
9
The effect of CMOS scaling > 65nm CMOS
• ‘large’ transistors • some effects can be considered
deterministic: NBTI, (PBTI), HCI
• some effects are statistical: TDDB, variability
< 65nm CMOS
• PBTI besides NBTI • `atomic’ scale transistor • everything becomes stochastic
[Maricau IEEE JETCAS 2011] [Maricau DATE 2011] INESC Jan 2013
© G. Gielen, KU Leuven
19
What do we need for analog circuits? compact models for all important unreliability effects
• include all important factors
Analog
» e.g. e g W,L, W L Vgs, Vgs Vds, Vds T, T …
• include interaction effects » e.g. Vds-Vgs for HCI
• cover a broad continuous range of values » e.g. g Vgs g = [0V [ … 1.5V], ],
Digital
W=[0.08m-10m]
• model time-varying stress effects » e.g. Vgs(t)= VGS + sin(0.5,1e6) INESC Jan 2013
© G. Gielen, KU Leuven
20
10
Hot Carrier degradation channel hot carrier • a well known phenomenon (>25 years) • interface traps due to impact ionization near drain • dominant for nMOS in saturation » high VDS » high VGS • impact at device level » VTH, , go
n+
n+
[Wang, TDMR 2007]
N IT (t ) C exp(1VGS ) exp( 2VGS )t 0.45 © G. Gielen, KU Leuven
INESC Jan 2013
21
Hot Carrier degradation model
ESAT-MICAS model
• • • •
[Maricau ESREF 2008]
based on Reaction-Diffusion (RD) model includes all important transistor parameters (Vgs, Vds, L, T) DC and AC voltage stress parameter set to be extracted for every process
INESC Jan 2013
© G. Gielen, KU Leuven
22
11
HCI model verification
[Maricau ESREF2008] INESC Jan 2013
© G. Gielen, KU Leuven
23
Negative Bias Temperature Instability recent phenomenon NBTI important for pMOS
• [also PBTI for f nMOS below 65 nm] traps due to electro-chemical reaction with SiH large VGS temperature activated relaxation phenomenon
• interface traps: permanent part • oxide traps: recoverable part impact at device level • VTH, , go INESC Jan 2013
p+
p+
[Wang, TDMR 2007]
N IT C exp(
© G. Gielen, KU Leuven
VGS
)t 0.18 24
12
Bias Temperature Instability model
[Maricau, ESSDERC 2012] INESC Jan 2013
© G. Gielen, KU Leuven
25
NBTI model verification
[Maricau Electronics Letters 2010] INESC Jan 2013
© G. Gielen, KU Leuven
26
13
Transistor aging in sub-65nm CMOS aging effects become worse, even with high-k
• EOT reduces » Eeff increases i
• new materials (high-k) » PBTI • SiO2 Interfacial Layer » NBTI, HC, TDDB remains
© G. Gielen, KU Leuven
INESC Jan 2013
27
Stochastic BTI model • individual charges can change VTH
• Poisson distribution for
number of trapped charges (N=mean number of traps) • exponential distribution for the impact of an individual defect ( = average impact) • VTH=f(Vgs,T) • V VTH)=f(1/(WL)) ) f(1/(WL))
[Maricau DATE 2011] INESC Jan 2013
© G. Gielen, KU Leuven
28
14
Time-Dependent Dielectric Breakdown PMOS and NMOS statistical phenomenon gate t currentt iincreases high VGS soft BD – Ig noise hard BD – k gate
resistance
© G. Gielen, KU Leuven
INESC Jan 2013
29
TDDB model soft breakdown
• example :
65nm technology » 1V gate stress » 10 year stress time • time to SBD follows a Weibull distribution » SBD=1.2 » =-30
F ( t SBD [Maricau DATE 2011] INESC Jan 2013
t ) 1 exp SBD SBD © G. Gielen, KU Leuven
30
15
Soft breakdown example aging
creates spread • 65nm
technology (1.7nm tox) • 0.8V gate stress • PDF after 0,1,10 year stress time [Maricau DATE 2011] INESC Jan 2013
© G. Gielen, KU Leuven
31
Contents
Motivation Aging modeling Reliability simulation Reliability-aware Reliability aware or resilient design Conclusions INESC Jan 2013
© G. Gielen, KU Leuven
32
16
Commercial tools transistor reliability analysis: □ RelXpert (now part of Cadence) □ Mentor Graphics p ELDO Reliabilityy Simulator □ Synopsys HSPICE MOSRA
The backbone of these tools is developed in the nineties and is no longer adequate! INESC Jan 2013
© G. Gielen, KU Leuven
33
Transistor model for aging
[Maricau TCAD2011 & DATE2011] INESC Jan 2013
© G. Gielen, KU Leuven
34
17
Deterministic reliability simulation
VTH
qN IT C ox
g o 1 VTH 0 I DS 0
eff
1 VGS
0 VTH
1 VTH
[Maricau DATE2009 & TCAD2010] INESC Jan 2013
© G. Gielen, KU Leuven
35
Example: LC-VCO 5 GHz and low phase noise
• high g output p swing g • high LC-tank Q-factor • protective gate capacitors (DC-bias not shown) • UMC 90nm
2 FkT L phase 10 log Ps INESC Jan 2013
2 1 / f 3 n 1 1 2 Q
© G. Gielen, KU Leuven
36
18
Nominal simulation
AC simulation shows sudden Vout degradation (due to go degradation) no frequency degradation failure due to Hot Carrier damage INESC Jan 2013
© G. Gielen, KU Leuven
37
Variability awareness process variability introduces
stress variability transistor aging + process variability = yield(t)
[Maricau TCAD2010] INESC Jan 2013
© G. Gielen, KU Leuven
38
19
Variability-aware reliability simulation
factor space exploration
screening linear model detect interactions regression interactions weakly nonlinear effects
polynomial RSM
residual analysis
error estimation
[Maricau TCAD 2010] INESC Jan 2013
© G. Gielen, KU Leuven
39
Example : VCO
[Maricau TCAD 2010] INESC Jan 2013
© G. Gielen, KU Leuven
40
20
Variability-aware reliability simulation
[Maricau TCAD 2010] INESC Jan 2013
© G. Gielen, KU Leuven
41
Example circuit : ADC
[Gielen DATE 2013] INESC Jan 2013
© G. Gielen, KU Leuven
42
21
Impact on analog circuits
INESC Jan 2013
© G. Gielen, KU Leuven
43
Aging-insensitive analog circuits • circuits that are immune to process variations » VTH VDD,nom) » e.g. phase noise of an LC-VCO □ asymmetrical y stress can result in time-dependent p mismatch » e.g. Voffset of a comparator □ time-dependent mismatch in matched transistors due to stochastic aging effects » e.g. MOS resistor in sub-45nm CMOS
INESC Jan 2013
© G. Gielen, KU Leuven
45
Contents
Motivation Aging modeling Reliability simulation Reliability-aware Reliability aware or resilient design Conclusions INESC Jan 2013
© G. Gielen, KU Leuven
46
23
Design for failure resilience intrinsically robust circuits
• worst-case overdesign to account for P/V/T corners plus overdesign p g to account for aging g g effects
• consumes extra power and area self-healing circuits
• adapt circuits at run time to compensate for the degradation » reconfiguration or retuning of the circuit » digital g calibration • required performance is maintained, though degradation is present
fully redundant circuits
INESC Jan 2013
© G. Gielen, KU Leuven
47
Self-healing (sense & react) circuits run-time monitoring and run-time adaptability
• add monitors or “canary” circuits to watch the degradation of the circuit performance p • feed information to controller • real-time reconfigure circuit (e.g. extra components) or update circuit parameters (e.g. bias) to maintain the performance KNOBS & MONITORS for analog : this is compatible with evolution towards digitallyassisted analog INESC Jan 2013
© G. Gielen, KU Leuven
48
24
Example: high-voltage line driver output driver overview:
equivalent model:
[Serneels ISSCC 2007]
Pload Rl Pload Ploss Rl Ron
INESC Jan 2013
© G. Gielen, KU Leuven
49
Example: high-voltage line driver guarantee minimum
power efficiency over lifetime breakdown monitors extra sub-transistors can be switched in
[De Wit DRVW 2008] INESC Jan 2013
© G. Gielen, KU Leuven
50
25
Self-healing test chip • on-chip power efficiency monitor □ measure output stage on-resistance (Ron=2.25Ω) □ compare p current Ron to reference resistor Rref • on-chip automatic controller • chip measurements 850um confirm real-time self-healing capabilities
1500um
[De Wit ESSCIRC 2011] INESC Jan 2013
© G. Gielen, KU Leuven
51
Failure-resilient implementation □ 90nm CMOS technology □ Pload = 10mW, 90% efficiency □ modifications for failure-resilient failure resilient operation : all included on chip !
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Measurement results
initial performance (fresh circuit): η=82%
no reconfiguration: ∆η = 5.5%
with reconfiguration: ∆ηmax < 1 %
[De Wit JSSC 2012] © G. Gielen, KU Leuven
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Conclusions handling uncertainty, spatial and temporal reliability
are a big issue in nanometer CMOS design
•
more degradation effects and becoming stochastic
accurate modeling and efficient CAD tools are needed to
assist the designer
• support design for reliability • less need for guardbanding – lower design margins results have been proposed in this presentation • accurate transistor aging models for BTI, HCI and TDDB effects • efficient circuit reliability simulator methods » both nominal and stochastic effects • resilient design solutions with limited overhead » self-healing circuits through run-time adaptive sense&react principle INESC Jan 2013
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On-going PhD projects CAD : • reliability modeling and simulation • high-frequency high frequency circuit synthesis • automated analog behavioral modeling design :
• • • • • •
ultra-low-power wireless sensor networks autonomous sensor interfaces i imager readout d t circuits i it biomedical interface circuits digitally assisted analog resilient self-healing analog circuits
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