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United States Patent [19]
[11] Patent Number:
Sharpe-Geisler
[45] Date of Patent:
[54]
0 330 971 9/1989 404348609 12/1992
P-TYPE FLIP-FLOP
[75] Inventor: Bradley A. Sharpe-Geisler, San Jose, Calif.
Jun. 10, 1997
European Pat. O?'. .
405327435 12/1993 406260902
[73] Assignee: Advanced Micro Devices, Inc., Sunnyvale, Calif.
5,638,018
9/1994
OTHER PUBLICATIONS “Circuit Scheme to improve chip data hold time”, Technical Disclosure Bulletin, Dec. 1990, vol. 33, No. 7, pp. 185-189. IBM Technical Disclosure Bulletin, vol. 30, No. 4, Sep.
[21] APP1-N°-1459s786 [51]
Int. Cl.6 ................................................... .. H03K 3/356
Primary Examiner—-Tim0thy P. Callahan
[52]
U.S. Cl. ................ ..
Assistant Examiner-My-Trang Nu Ton
. 327/215; 327/199; 327/225
[58] Field of Search ................................... .. 327/197, 199,
327/201, 202, 203, 203, 212, 214, 215, 218’ 219’ 225 [56]
Attorney, Agent, vrFirm—F1ies1er, Dubb, Meyer & Lovel‘oy
[57]
ABSTRACT
A P-type ?ip-?op, which selectively functions in a D-type ?ip-?op mode or latch mode depending on its clock signal input. The P-type ?ip-?op has an output changing states to follow its data input at a leading edge of its clock input, the
References Cited U_S_ PATENT DOCUMENTS 4,300,060 11/1981 Yu ......................................... .. 327/197
Output then does not change states for a period 5, and then
307/475
the output changing states to match its data input after the period e if a signal is received at its clock input having a period greater than e. With a pulse applied at the clock input having a width_ less than c, the P-type ?ip~?0p is .edge __ _ _ _ .
4,716,312 12/1987 4,820,939 4/1989 4,825,416 4/1989 4,864,161 9/1989
" 327/197
4, 70,407
11/1990
327/203
5,332,741
7,1991
307/279
sensltlve funct1omng similar to a D-type ?ip-?op. W1th a
5,189,315
2/1993 Akata .................................... .. 327/203
Pulse With longer than E applied to the clock input, the
FOREIGN PATENT DOCUMENTS 0 318 163
5/1989 European Pat. 01f. .
640
CLK
DATA?
P-type ?ip-?op appears transparent similar to a latch. 8 Claims, 7 Drawing Sheets
U.S. Patent
DATA
Jun. 10, 1997
5,638,018
Sheet 1 of 7
Date '6
Data 6 —-0 “I02
E__
“I04
> FIG. I Prior Art
OK
DATA
K20PH-g ‘
200 l
Qv
‘—_‘ - DATA- Data 0 J-
300
‘
Data 0 "I02
"I04
__l LATcH/oFF>——-—|
OK
302
jI>e
FIG. 3 Prior Art
US. Patent
Jun. 10, 1997
Sheet 2 of 7
5,638,018
400
402 PULSE CK—-—--
——
GENERATOR *
404
FIG. 4
U.S. Patent
Jun. 10, 1997
Sheet 3 of 7
5,638,018
5O2L ______\ 504/\______
506
\
508
\ FFIG. 5
US. Patent
Jun. 10, 1997
Sheet 4 of 7
5,638,018
___l-_______¢_-___~__
OAU _|_mom
_I
I I I I
I I I I
I I I I I . J
ADE-
United States Patent [19]
[11] Patent Number:
Sharpe-Geisler
[45] Date of Patent:
[54]
0 330 971 9/1989 404348609 12/1992
P-TYPE FLIP-FLOP
[75] Inventor: Bradley A. Sharpe-Geisler, San Jose, Calif.
Jun. 10, 1997
European Pat. O?'. .
405327435 12/1993 406260902
[73] Assignee: Advanced Micro Devices, Inc., Sunnyvale, Calif.
5,638,018
9/1994
OTHER PUBLICATIONS “Circuit Scheme to improve chip data hold time”, Technical Disclosure Bulletin, Dec. 1990, vol. 33, No. 7, pp. 185-189. IBM Technical Disclosure Bulletin, vol. 30, No. 4, Sep.
[21] APP1-N°-1459s786 [51]
Int. Cl.6 ................................................... .. H03K 3/356
Primary Examiner—-Tim0thy P. Callahan
[52]
U.S. Cl. ................ ..
Assistant Examiner-My-Trang Nu Ton
. 327/215; 327/199; 327/225
[58] Field of Search ................................... .. 327/197, 199,
327/201, 202, 203, 203, 212, 214, 215, 218’ 219’ 225 [56]
Attorney, Agent, vrFirm—F1ies1er, Dubb, Meyer & Lovel‘oy
[57]
ABSTRACT
A P-type ?ip-?op, which selectively functions in a D-type ?ip-?op mode or latch mode depending on its clock signal input. The P-type ?ip-?op has an output changing states to follow its data input at a leading edge of its clock input, the
References Cited U_S_ PATENT DOCUMENTS 4,300,060 11/1981 Yu ......................................... .. 327/197
Output then does not change states for a period 5, and then
307/475
the output changing states to match its data input after the period e if a signal is received at its clock input having a period greater than e. With a pulse applied at the clock input having a width_ less than c, the P-type ?ip~?0p is .edge __ _ _ _ .
4,716,312 12/1987 4,820,939 4/1989 4,825,416 4/1989 4,864,161 9/1989
" 327/197
4, 70,407
11/1990
327/203
5,332,741
7,1991
307/279
sensltlve funct1omng similar to a D-type ?ip-?op. W1th a
5,189,315
2/1993 Akata .................................... .. 327/203
Pulse With longer than E applied to the clock input, the
FOREIGN PATENT DOCUMENTS 0 318 163
5/1989 European Pat. 01f. .
640
CLK
DATA?
P-type ?ip-?op appears transparent similar to a latch. 8 Claims, 7 Drawing Sheets
U.S. Patent
DATA
Jun. 10, 1997
5,638,018
Sheet 1 of 7
Date '6
Data 6 —-0 “I02
E__
“I04
> FIG. I Prior Art
OK
DATA
K20PH-g ‘
200 l
Qv
‘—_‘ - DATA- Data 0 J-
300
‘
Data 0 "I02
"I04
__l LATcH/oFF>——-—|
OK
302
jI>e
FIG. 3 Prior Art
US. Patent
Jun. 10, 1997
Sheet 2 of 7
5,638,018
400
402 PULSE CK—-—--
——
GENERATOR *
404
FIG. 4
U.S. Patent
Jun. 10, 1997
Sheet 3 of 7
5,638,018
5O2L ______\ 504/\______
506
\
508
\ FFIG. 5
US. Patent
Jun. 10, 1997
Sheet 4 of 7
5,638,018
___l-_______¢_-___~__
OAU _|_mom
_I
I I I I
I I I I
I I I I I . J
ADE-
