Low-temperature bottom-up integration of carbon nanotubes for ...
Low-temperature bottom-up integration of carbon nanotubes for vertical interconnects in monolithic 3D integrated circuits Sten Vollebregt, Ryoichi Ishihara, Johan van der Cingel and Kees Beenakker Delft University of Technology Delft Institute of Microsystems and Nanotechnology Feldmannweg 17, 2628CT, Delft, The Netherlands Email: [email protected]
Abstract—Carbon nanotubes (CNT) can be an attractive candidate for vertical interconnects in 3D monolithic integration, due to their excellent thermal and electrical properties. In this paper we investigate the use of a true bottom-up approach to fabricate CNT vias, for application in 3D monolithic integration. This circumvents metal deposition in high aspect ratio holes, and also allows the use of bundle densification techniques to increase CNT density. Using this approach we fabricated fourpoint probe electrical measurement structures for both as-grown and densified CNT bundles, and performed I-V measurements. The resulting I-V curves display non-linearities due to a nonOhmic top contact. The measured resistivities of 10-20 mΩ-cm are among the better values found in literature.
I. I NTRODUCTION Three dimensional integration can offer high integration density, shorter routing and increased functionality by combining for instance sensors and logic. Of the different approaches that exist for 3D integration, monolithic (devicelevel) integration offers the highest integration density and shortest interconnect length. In this approach transistor layers are stacked on top of each other on the same die across the entire wafer. Many challenges still remain to be solved in order to achieve monolithic integration. One of the biggest is creating the active silicon layers. Our group has previously been working on monolithic integration using single-grain thin-film transistors (SG-TFTs) [1]. These transistors offer silicon-on-insulator (SOI) level performance, while processing temperature remains below 550 ◦ C. Using two layers of transistors we demonstrated memory circuits and combined image sensor with read-out [2]. Two other major remaining challenges are manufacturing reliable low resistance vertical interconnects and thermal management. Already in modern circuits vertical interconnects (vias) display many reliability issues due to difficulties in filling the small openings. For monolithic integrated circuits we can expect these issues to be worse, as the oxide required to isolate the different active layers is relative thick. Thermal management is an issue as the amount of transistors is increased drastically, while the surface area of the die remains roughly the same.
Carbon nanotubes (CNT) can be an attractive candidate to tackle both issues. It has been shown that CNT can have unrivalled electric properties, allowing ballistic transport over a length of several µm [3], [4]. Moreover, CNT have been demonstrated to have very good reliability properties, allowing a current density up to three order of magnitude higher than copper [5]. Beside good electrical properties CNT can be grown with very high aspect ratios. Finally, CNT have been demonstrated to posses very good thermal properties with thermal conductivities reaching 3500 W/mK [6]. Much interest has already been shown in using CNT as vias for regular 2D integrated circuits [7]–[10]. We propose to use CNT as via material in monolithic integrated 3D circuits. For this a bottom-up approach as suggested by Li et al. [11] should be most suitable. In this approach the CNT are grown before the deposition of the dielectric layer, thus circumventing all the issues involved in filling high aspect ratio holes. As CNT can be grown vertically well aligned integration density can be high. In this paper we created low-temperature and high density multi-walled CNT (MWCNT) using this bottom-up approach and performed electrical resistance measurements. Moreover, we investigated the use of a bundle densification technique in order to reduce via dimensions and resistivity by increasing the CNT tube density. II. E XPERIMENTAL As substrate 4” p-type Si wafers with (100) are used. These wafers are metallized using a Trikon Sigma sputter coater with 500 nm of Ti and 50 nm TiN, which acts as bottom contact to the CNT bundles. TiN is used as this is a standard barrier material in the IC industry, doesn’t oxidise during wafer transfer between machines (for catalyst deposition) and allows the growth of vertically aligned MWCNT at low temperatures in our CNT growth reactor. Next a 5 nm thick Fe catalyst layer is deposited using an CHA Solution e-beam evaporator and patterned using lift-off. For this lift-off process we employ AZ nLOF pure negative resist, which is exposed by an ASML PAS 5500/80 waferstepper. The actual lift-off is performed in n-methyl pyrrolidone
(a) CNT directly after growth
(b) CNT with high aspect ratio
(c) CNT covered by PECVD oxide
(d) Covered CNT after CMP
Fig. 1. Process flow from first metal, including catalyst deposition, LPCVD CNT growth, optional densification, PECVD oxide deposition, CMP and final metallization
at 70 ◦ C. After this CNT are grown using the commercially available AIXTRON BlackMagic Pro CNT reactor. The first phase of the growth process consists of a activation step with 700 sccm of H2 for 3 min. at 500◦ C and 80 mbar. After this 50 sccm of C2 H2 is added to start the CNT growth phase. Total growth time equals 15 minutes. After CNT growth 5 µm of PECVD oxide is deposited using a Novellus Concept One reactor at 400 ◦ C. Before performing this step the CNT of some of the wafers are densified using isopropanol. Oxide depoistion is followed by planarization using chemical mechanical polishing (CMP) with a silica slurry. A total of approximately 1 µm of oxide is removed in this process. Finally, the second electrode consisting of 100 nm of Ti and 2 µm of Al(1% Si) is deposited and patterned using wet etching. Finally, contact holes are etched through the oxide in order to contact the first electrode directly. In fig. 1 an overview is given of the bottom-up process. Samples were characterised using an FEI/Philips XL50 scanning electron microscope (SEM) and Agilent 4156C parameter analyser. III. R ESULTS AND DISCUSSION In fig. 2a a SEM image taken from an array of five by five 2 µm wide CNT bundles with a spacing of 3 µm and height of roughly 5 µm. As can be observed the CNT and bundles display good vertical alignment. Fig. 2b displays a single 2 µm wide bundle with a length of almost 10 µm, demonstrating the ability to grow high aspect ratio (HAR) free standing bundles. The density of the CNT inside the bundles is ∼ 1011 tubes/cm2 , while the average tube diameter is 515 nm. The CNT tube length can be changed by varying the deposition time, which has a linear dependency against length, with a growth rate of 350 nm/minute. We use PECVD oxide as it can be deposited at low temperatures. Previously, we reported that we didn’t observe a major degradation in tube crystallinity due to plasma damage while depositing the oxide [12]. The CNT are uniformly covered by the PECVD oxide, as can be seen in fig. 2c. It can also be clearly seen that CMP is required to be able to contact the top of the CNT bundles. Finally fig. 2d displays the array of CNT after approximately 1 µm of oxide was removed using CMP. As can be seen the CNTs are cut-off at the same height as the oxide. Gaps can
(e) Crack in larger CNT bundle Fig. 2.
SEM images taken from different stages in the bottom-up process
exist between CNT bundles spaced closed to each other, due to a non optimized PECVD oxide deposition process. Decreasing deposition rate likely solves this issue. As shown in fig. 2e in some larger CNT bundles cracks appear with a width of several hundred nm, which are caused by the non-optimized CMP process. It must also be noted that we encountered difficulties in polishing large bundles with widths of 6 µm or wider. Most of these bundles are removed during CMP, which we attribute to mechanical removal during the CMP step as the substrate adhesion of CNT is generally low [13]. The bundles are only covered on the outside by the PECVD oxide. Embedding the CNT in a layer of atomic layer deposited dielectric, as demonstrated by Chiodarelli et al. [14], to increase mechanical stability could circumvent this problem and the formation of cracks in large bundles. Although the density of our bundles is relative high, it is still orders of magnitude lower than ideal tight packing in which case density can be as high as 1013 − 1014 tubes/cm2 . It has been demonstrated that CNT density can be increased by dipping the tubes into isopropanol [15]. This densification is caused by the capillary forces of the liquid combined with strong Van der Waals interaction between the tubes upon liquid
(a) Bundle of initially 2 µm Fig. 3.
(b) Bundle of initially 5 µm
SEM images taken from bundles after densification
evaporation. We employed this technique by simply dipping the full wafers upside-down into an isopropanol bath, followed by drying of the wafers in air. As can be from fig. 3 the width of the resulting bundles are 72 % and 74 % of the initial width for the 2 µm and 5 µm bundle, respectively. This is representative for all bundle sizes over the entire wafer. The resulting area after densification is thus almost 50 % of the initial bundle area, drastically reducing the footprint of the top CNT bundle contact. The bottom contact remains the same, due to the strong enough surface adhesion of the CNT. The tip of the CNT bundle is less densified, but conveniently removed during the CMP process. We created four-point probe measurement structures using this bottom-up process to measure the resistance of the CNT bundles. Using the top and bottom electrode contacts a current could be forced through the bundle, which could be currentless measured using two different top and bottom contacts. Using this structure only the resistance of the CNT bundle, and the contact resistances to the top and bottom electrode are measured. A sketch of the measurement structure can be found in the inset of fig. 4. Fig. 4 displays typical I-V characteristics obtained from several bundles with a width of 1 µm and a length in between 3.8 and 4 µm. As can be seen there exist a non-linear component in the measured I-V curves. This is most likely caused by a non-Ohmic contact. We suspect the top contact, as the bottom contact should still be similar to those used for top-down results reported earlier by our group, which didn’t suffer from any non-linearities [12]. These non-linearites are also visible for bundles with a width of 2 and 4 µm, which have a larger contact areas. Improving the CMP conditions, or removing part of the silicon oxide to expose the CNT tips could improve the top contact. Annealing might also solve the problem, although we found that annealing the wafers in a nitrogen atmosphere at 400 ◦ C actually degraded the resistance. From the five best performing structures we determined the average resistivity and standard deviation using the approximate dimensions of the CNT bundle. The same was done for the densified bundles, assuming a final width of 75 % of that of the initial width (1.5 and 3 µm for, respectively, the initially 2 and 4 µm bundles). The resulting resistivities are plotted in
Fig. 4. I-V characteristics obtained from several CNT bundles with 1 µm width. The inset shows the used 4-point probe structure, the black cilinder indicates the CNT bundle.
fig. 5 together with results obtained by top-down integration performed before in our group and results taken from literature about CNT vias for 2D integrated circuits. As can be seen the results are among the better values reported in literature, although still many orders of magnitude higher than the bulk resistivity of for instance Cu. For small bundle sizes the resistivity increases sharply for the as-grown CNT bundles. We suspect that the top contact is the cause of this deviation for these bottom-up results. This is because the measurement results of the densified 2 µm bundle are much better, which also display hardly any non-linearities in the I-V characteristics indicating better contact. The CMP processed used for the densified and non-densified bundles differ, for the latter it was done with a pH 7 slurry, while the first uses the standard slurry. Making the slurry pH neutral resulted in much longer polish times, likely wearing down the tips of the tube resulting in a higher contact resistance. For the larger 4 µm bundles the resistivity spread is much larger, which could be caused by the before mentioned cracks observed in some of the larger structures. Overall, although a different CMP approach was used, the values between densified and non-densified bundles are not for apart. The obtained values using bottom-up integration are close to those reported before using the same CNT growth recipe, but a topdown approach [12]. For the larger and densified bundles the resulting resistivities are even lower. This confirms that the bottom-up approach does not degrade CNT quality. The higher resistivities measured can be attributed to a higher top-contact resistance, which can be improved by optimizing the CMP parameters. IV. C ONCLUSION Carbon nanotubes can be an attractive candidate for vias in 3D monolithic integration due to their good electrical and thermal properties. We demonstrate, for the first time, that is is possible to use a pure bottom-up approach using carbon
Fig. 5. Calculated average resistivities and standard deviation for normal and densified bundles, compared to literature.
nanotubes to create vias. With this approach it is possible to use bundle densification techniques, which decrease the top area of the via. Four-point probe I-V measurements were performed for both densified and non-densified bundles, displaying a non-linear resistance due to a non-Ohmic top contact. The measured resistivities of 10-20 mΩ-cm are among the better values reported in literature. ACKNOWLEDGMENT The authors want to thank T.M. Michielsen, F.J.H. van der Kruis and O.J.A. Buijk at Philips Innovation Services MiPlaza for performing the CMP. This project is kindly funded by the European ENIAC Joint Undertaking as part of the JEMSiP 3D project. R EFERENCES [1] M. R. T. Mofrad, J. Derakhshandeh, R. Ishihara, A. Baiano, J. van der Cingel, and K. Beenakker, “Stacking of single-grain thin-film transistors,” Japanese Journal of Applied Physics, vol. 48, p. 03B015, 2009. [2] J. Derakhshandeh, N. Golshani, R. Ishihara, M. R. T. Mofrad, M. Robertson, T. Morrison, and C. I. M. Beenakker, “Monolithic 3-D integration of SRAM and image sensor using two layers of single-grain silicon,” IEEE Transactions on Electron Devices, vol. 58, no. 11, pp. 3954–3961, 2011. [3] D. Mann, A. Javey, J. Kong, Q. Wang, and H. Dai, “Ballistic transport in metallic nanotubes with reliable Pd ohmic contacts,” Nano Letters, vol. 3, no. 11, pp. 1541–1544, 2003. [4] H. J. Li, W. G. Lu, J. J. Li, X. D. Bai, and C. Z. Gu, “Multichannel ballistic transport in multiwall carbon nanotubes,” Physical Review Letters, vol. 95, p. 086601, 2005. [5] B. Q. Wei, R. Vajtai, and P. M. Ajayan, “Reliability and current carrying capacity of carbon nanotubes,” Applied Physics Letters, vol. 79, no. 8, pp. 1172–1174, 2001. [6] E. Pop, D. Mann, Q. Wang, K. Goodson, and H. Dai, “Thermal conductance of an individual single-wall carbon nanotube above room temperature,” Nano Letters, vol. 6, no. 1, pp. 96–100, 2006. [7] J. Dijon, H. Okuno, M. Fayolle, T. Vo, J. Pontcharra, D. Acquaviva, D. Bouvet, A. M. Ionescu, C. S. Esconjauregui, B. Capraro, E. Quesnel, and J. Robertson, “Ultra-high density carbon nanotubes on Al-Cu for advanced vias,” in International Electron Devices Meeting, 2010, p. 33.4.1.
[8] D. Yokoyama, T. Iwasaki, K. Ishimaru, S. Sato, T. Hyakushima, M. Nihei, Y. Awano, and H. Kawarada, “Electrical properties of carbon nanotubes grown at a low temperature for use as interconnects,” Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 1985–1990, 2008. [9] Y.-M. Choi, S. Lee, H. S. Yoon, M.-S. Lee, H. Kim, I. Han, Y. Son, I.-S. Yeo, U.-I. Chung, and J.-T. Moon, “Integration and electrical properties of carbon nanotube array for interconnect applications,” in Nanotechnology, 2006. IEEE-NANO 2006. Sixth IEEE Conference on, 2006, pp. 262–265. [10] F. Kreupl, A. P. Graham, G. S. Duesberg, W. Steinh¨ogl, M. Liebau, E. Unger, and W. H¨onlein, “Carbon nanotubes in interconnect applications,” Microelectron. Eng., vol. 64, pp. 399–408, 2002. [11] J. Li, Q. Ye, A. Cassell, H. T. Ng, R. Stevens, J. Han, and M. Meyyappan, “Bottom-up approach for carbon nanotube interconnects,” Applied Physics Letters, vol. 82, no. 15, pp. 2491–2493, 2003. [12] S. Vollebregt, R. Ishihara, J. Derakhshandeh, J. van der Cingel, H. Schellevis, and C. Beenakker, “Integrating low temperature aligned carbon nanotubes as vertical interconnects in si technology,” in Nanotechnology, 2011. IEEE-NANO 2011. 11th IEEE Conference on, 2011, pp. 985–990. [13] H.-C. Su, C.-H. Chen, Y.-C. Chen, D.-J. Yao, H. Chen, Y.-C. Chang, and T.-R. Yew, “Improving the adhesion of carbon nanotubes to a substrate using microwave treatment,” Carbon, vol. 48, pp. 805–812, 2010. [14] N. Chiodarelli, “Integration of carbon nanotubes as future interconnections for sub-32nm technologies,” Ph.D. dissertation, Katholieke Universiteit Leuven, 2011. [15] D. N. Futaba, K. Hata, T. Yamada, T. Hiraoka, Y. Hayamizu, Y. Kakudate, O. Tanaike, H. Hatori, M. Yumura, and S. Iijima, “Shapeengineerable and highly densely packed single-walled carbon nanotubes and their application as super-capacitor electrodes,” Nature Materials, vol. 5, pp. 987–994, 2006.
Abstract—Carbon nanotubes (CNT) can be an attractive candidate for vertical interconnects in 3D monolithic integration, due to their excellent thermal and electrical properties. In this paper we investigate the use of a true bottom-up approach to fabricate CNT vias, for application in 3D monolithic integration. This circumvents metal deposition in high aspect ratio holes, and also allows the use of bundle densification techniques to increase CNT density. Using this approach we fabricated fourpoint probe electrical measurement structures for both as-grown and densified CNT bundles, and performed I-V measurements. The resulting I-V curves display non-linearities due to a nonOhmic top contact. The measured resistivities of 10-20 mΩ-cm are among the better values found in literature.
I. I NTRODUCTION Three dimensional integration can offer high integration density, shorter routing and increased functionality by combining for instance sensors and logic. Of the different approaches that exist for 3D integration, monolithic (devicelevel) integration offers the highest integration density and shortest interconnect length. In this approach transistor layers are stacked on top of each other on the same die across the entire wafer. Many challenges still remain to be solved in order to achieve monolithic integration. One of the biggest is creating the active silicon layers. Our group has previously been working on monolithic integration using single-grain thin-film transistors (SG-TFTs) [1]. These transistors offer silicon-on-insulator (SOI) level performance, while processing temperature remains below 550 ◦ C. Using two layers of transistors we demonstrated memory circuits and combined image sensor with read-out [2]. Two other major remaining challenges are manufacturing reliable low resistance vertical interconnects and thermal management. Already in modern circuits vertical interconnects (vias) display many reliability issues due to difficulties in filling the small openings. For monolithic integrated circuits we can expect these issues to be worse, as the oxide required to isolate the different active layers is relative thick. Thermal management is an issue as the amount of transistors is increased drastically, while the surface area of the die remains roughly the same.
Carbon nanotubes (CNT) can be an attractive candidate to tackle both issues. It has been shown that CNT can have unrivalled electric properties, allowing ballistic transport over a length of several µm [3], [4]. Moreover, CNT have been demonstrated to have very good reliability properties, allowing a current density up to three order of magnitude higher than copper [5]. Beside good electrical properties CNT can be grown with very high aspect ratios. Finally, CNT have been demonstrated to posses very good thermal properties with thermal conductivities reaching 3500 W/mK [6]. Much interest has already been shown in using CNT as vias for regular 2D integrated circuits [7]–[10]. We propose to use CNT as via material in monolithic integrated 3D circuits. For this a bottom-up approach as suggested by Li et al. [11] should be most suitable. In this approach the CNT are grown before the deposition of the dielectric layer, thus circumventing all the issues involved in filling high aspect ratio holes. As CNT can be grown vertically well aligned integration density can be high. In this paper we created low-temperature and high density multi-walled CNT (MWCNT) using this bottom-up approach and performed electrical resistance measurements. Moreover, we investigated the use of a bundle densification technique in order to reduce via dimensions and resistivity by increasing the CNT tube density. II. E XPERIMENTAL As substrate 4” p-type Si wafers with (100) are used. These wafers are metallized using a Trikon Sigma sputter coater with 500 nm of Ti and 50 nm TiN, which acts as bottom contact to the CNT bundles. TiN is used as this is a standard barrier material in the IC industry, doesn’t oxidise during wafer transfer between machines (for catalyst deposition) and allows the growth of vertically aligned MWCNT at low temperatures in our CNT growth reactor. Next a 5 nm thick Fe catalyst layer is deposited using an CHA Solution e-beam evaporator and patterned using lift-off. For this lift-off process we employ AZ nLOF pure negative resist, which is exposed by an ASML PAS 5500/80 waferstepper. The actual lift-off is performed in n-methyl pyrrolidone
(a) CNT directly after growth
(b) CNT with high aspect ratio
(c) CNT covered by PECVD oxide
(d) Covered CNT after CMP
Fig. 1. Process flow from first metal, including catalyst deposition, LPCVD CNT growth, optional densification, PECVD oxide deposition, CMP and final metallization
at 70 ◦ C. After this CNT are grown using the commercially available AIXTRON BlackMagic Pro CNT reactor. The first phase of the growth process consists of a activation step with 700 sccm of H2 for 3 min. at 500◦ C and 80 mbar. After this 50 sccm of C2 H2 is added to start the CNT growth phase. Total growth time equals 15 minutes. After CNT growth 5 µm of PECVD oxide is deposited using a Novellus Concept One reactor at 400 ◦ C. Before performing this step the CNT of some of the wafers are densified using isopropanol. Oxide depoistion is followed by planarization using chemical mechanical polishing (CMP) with a silica slurry. A total of approximately 1 µm of oxide is removed in this process. Finally, the second electrode consisting of 100 nm of Ti and 2 µm of Al(1% Si) is deposited and patterned using wet etching. Finally, contact holes are etched through the oxide in order to contact the first electrode directly. In fig. 1 an overview is given of the bottom-up process. Samples were characterised using an FEI/Philips XL50 scanning electron microscope (SEM) and Agilent 4156C parameter analyser. III. R ESULTS AND DISCUSSION In fig. 2a a SEM image taken from an array of five by five 2 µm wide CNT bundles with a spacing of 3 µm and height of roughly 5 µm. As can be observed the CNT and bundles display good vertical alignment. Fig. 2b displays a single 2 µm wide bundle with a length of almost 10 µm, demonstrating the ability to grow high aspect ratio (HAR) free standing bundles. The density of the CNT inside the bundles is ∼ 1011 tubes/cm2 , while the average tube diameter is 515 nm. The CNT tube length can be changed by varying the deposition time, which has a linear dependency against length, with a growth rate of 350 nm/minute. We use PECVD oxide as it can be deposited at low temperatures. Previously, we reported that we didn’t observe a major degradation in tube crystallinity due to plasma damage while depositing the oxide [12]. The CNT are uniformly covered by the PECVD oxide, as can be seen in fig. 2c. It can also be clearly seen that CMP is required to be able to contact the top of the CNT bundles. Finally fig. 2d displays the array of CNT after approximately 1 µm of oxide was removed using CMP. As can be seen the CNTs are cut-off at the same height as the oxide. Gaps can
(e) Crack in larger CNT bundle Fig. 2.
SEM images taken from different stages in the bottom-up process
exist between CNT bundles spaced closed to each other, due to a non optimized PECVD oxide deposition process. Decreasing deposition rate likely solves this issue. As shown in fig. 2e in some larger CNT bundles cracks appear with a width of several hundred nm, which are caused by the non-optimized CMP process. It must also be noted that we encountered difficulties in polishing large bundles with widths of 6 µm or wider. Most of these bundles are removed during CMP, which we attribute to mechanical removal during the CMP step as the substrate adhesion of CNT is generally low [13]. The bundles are only covered on the outside by the PECVD oxide. Embedding the CNT in a layer of atomic layer deposited dielectric, as demonstrated by Chiodarelli et al. [14], to increase mechanical stability could circumvent this problem and the formation of cracks in large bundles. Although the density of our bundles is relative high, it is still orders of magnitude lower than ideal tight packing in which case density can be as high as 1013 − 1014 tubes/cm2 . It has been demonstrated that CNT density can be increased by dipping the tubes into isopropanol [15]. This densification is caused by the capillary forces of the liquid combined with strong Van der Waals interaction between the tubes upon liquid
(a) Bundle of initially 2 µm Fig. 3.
(b) Bundle of initially 5 µm
SEM images taken from bundles after densification
evaporation. We employed this technique by simply dipping the full wafers upside-down into an isopropanol bath, followed by drying of the wafers in air. As can be from fig. 3 the width of the resulting bundles are 72 % and 74 % of the initial width for the 2 µm and 5 µm bundle, respectively. This is representative for all bundle sizes over the entire wafer. The resulting area after densification is thus almost 50 % of the initial bundle area, drastically reducing the footprint of the top CNT bundle contact. The bottom contact remains the same, due to the strong enough surface adhesion of the CNT. The tip of the CNT bundle is less densified, but conveniently removed during the CMP process. We created four-point probe measurement structures using this bottom-up process to measure the resistance of the CNT bundles. Using the top and bottom electrode contacts a current could be forced through the bundle, which could be currentless measured using two different top and bottom contacts. Using this structure only the resistance of the CNT bundle, and the contact resistances to the top and bottom electrode are measured. A sketch of the measurement structure can be found in the inset of fig. 4. Fig. 4 displays typical I-V characteristics obtained from several bundles with a width of 1 µm and a length in between 3.8 and 4 µm. As can be seen there exist a non-linear component in the measured I-V curves. This is most likely caused by a non-Ohmic contact. We suspect the top contact, as the bottom contact should still be similar to those used for top-down results reported earlier by our group, which didn’t suffer from any non-linearities [12]. These non-linearites are also visible for bundles with a width of 2 and 4 µm, which have a larger contact areas. Improving the CMP conditions, or removing part of the silicon oxide to expose the CNT tips could improve the top contact. Annealing might also solve the problem, although we found that annealing the wafers in a nitrogen atmosphere at 400 ◦ C actually degraded the resistance. From the five best performing structures we determined the average resistivity and standard deviation using the approximate dimensions of the CNT bundle. The same was done for the densified bundles, assuming a final width of 75 % of that of the initial width (1.5 and 3 µm for, respectively, the initially 2 and 4 µm bundles). The resulting resistivities are plotted in
Fig. 4. I-V characteristics obtained from several CNT bundles with 1 µm width. The inset shows the used 4-point probe structure, the black cilinder indicates the CNT bundle.
fig. 5 together with results obtained by top-down integration performed before in our group and results taken from literature about CNT vias for 2D integrated circuits. As can be seen the results are among the better values reported in literature, although still many orders of magnitude higher than the bulk resistivity of for instance Cu. For small bundle sizes the resistivity increases sharply for the as-grown CNT bundles. We suspect that the top contact is the cause of this deviation for these bottom-up results. This is because the measurement results of the densified 2 µm bundle are much better, which also display hardly any non-linearities in the I-V characteristics indicating better contact. The CMP processed used for the densified and non-densified bundles differ, for the latter it was done with a pH 7 slurry, while the first uses the standard slurry. Making the slurry pH neutral resulted in much longer polish times, likely wearing down the tips of the tube resulting in a higher contact resistance. For the larger 4 µm bundles the resistivity spread is much larger, which could be caused by the before mentioned cracks observed in some of the larger structures. Overall, although a different CMP approach was used, the values between densified and non-densified bundles are not for apart. The obtained values using bottom-up integration are close to those reported before using the same CNT growth recipe, but a topdown approach [12]. For the larger and densified bundles the resulting resistivities are even lower. This confirms that the bottom-up approach does not degrade CNT quality. The higher resistivities measured can be attributed to a higher top-contact resistance, which can be improved by optimizing the CMP parameters. IV. C ONCLUSION Carbon nanotubes can be an attractive candidate for vias in 3D monolithic integration due to their good electrical and thermal properties. We demonstrate, for the first time, that is is possible to use a pure bottom-up approach using carbon
Fig. 5. Calculated average resistivities and standard deviation for normal and densified bundles, compared to literature.
nanotubes to create vias. With this approach it is possible to use bundle densification techniques, which decrease the top area of the via. Four-point probe I-V measurements were performed for both densified and non-densified bundles, displaying a non-linear resistance due to a non-Ohmic top contact. The measured resistivities of 10-20 mΩ-cm are among the better values reported in literature. ACKNOWLEDGMENT The authors want to thank T.M. Michielsen, F.J.H. van der Kruis and O.J.A. Buijk at Philips Innovation Services MiPlaza for performing the CMP. This project is kindly funded by the European ENIAC Joint Undertaking as part of the JEMSiP 3D project. R EFERENCES [1] M. R. T. Mofrad, J. Derakhshandeh, R. Ishihara, A. Baiano, J. van der Cingel, and K. Beenakker, “Stacking of single-grain thin-film transistors,” Japanese Journal of Applied Physics, vol. 48, p. 03B015, 2009. [2] J. Derakhshandeh, N. Golshani, R. Ishihara, M. R. T. Mofrad, M. Robertson, T. Morrison, and C. I. M. Beenakker, “Monolithic 3-D integration of SRAM and image sensor using two layers of single-grain silicon,” IEEE Transactions on Electron Devices, vol. 58, no. 11, pp. 3954–3961, 2011. [3] D. Mann, A. Javey, J. Kong, Q. Wang, and H. Dai, “Ballistic transport in metallic nanotubes with reliable Pd ohmic contacts,” Nano Letters, vol. 3, no. 11, pp. 1541–1544, 2003. [4] H. J. Li, W. G. Lu, J. J. Li, X. D. Bai, and C. Z. Gu, “Multichannel ballistic transport in multiwall carbon nanotubes,” Physical Review Letters, vol. 95, p. 086601, 2005. [5] B. Q. Wei, R. Vajtai, and P. M. Ajayan, “Reliability and current carrying capacity of carbon nanotubes,” Applied Physics Letters, vol. 79, no. 8, pp. 1172–1174, 2001. [6] E. Pop, D. Mann, Q. Wang, K. Goodson, and H. Dai, “Thermal conductance of an individual single-wall carbon nanotube above room temperature,” Nano Letters, vol. 6, no. 1, pp. 96–100, 2006. [7] J. Dijon, H. Okuno, M. Fayolle, T. Vo, J. Pontcharra, D. Acquaviva, D. Bouvet, A. M. Ionescu, C. S. Esconjauregui, B. Capraro, E. Quesnel, and J. Robertson, “Ultra-high density carbon nanotubes on Al-Cu for advanced vias,” in International Electron Devices Meeting, 2010, p. 33.4.1.
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