Magnetic Look-Up Table (MLUT) Featuring Radiation ... - Springer Link
Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power Yahya Lakys, Weisheng Zhao, Jacques-Olivier Klein, and Claude Chappert IEF, Univ. Paris-Sud, UMR8622, Orsay, F-91405, France CNRS, Orsay, F-91405, France {yahya.lakys,weisheng.zhao,jacques-olivier.klein, claude.chappert}@u-psud.fr
Abstract. Thanks to its non-volatility, high write/sense speed and small size, Magnetic Tunnel Junction (MTJ) is under investigation to be integrated in the future reconfigurable computing circuits offering higher power efficiency and performance. Another advantage of MTJ is that it provides good radiation hardness compared with other storage technologies used in reconfigurable computing circuits. In this paper, we present a design of Magnetic Look-Up-Table (MLUT) performing radiation hardness and keeping high reconfiguration /computing speed, high reliability and low power. Simulation results using an accurate model of MTJ and CMOS 130nm design kit confirm its expected performances in terms of reliability, power and speed. Keywords: Hybrid Design, High Reliability, MLUT, Radiation Hardness.
1 Introduction Look-Up Table (LUT) is one of the important building blocks for reconfigurable computing devices [1]. This element requires memory points currently based on SRAM or flash technologies [2]. Recently, Magnetic Tunnel Junction (MTJ) [3] has demonstrated a great potential for integration as memory elements into embedded and reconfigurable systems such as FPGA [4-6]. This new memory intends to replace SRAM that need high standby power and relatively slow flash memory. In addition, 3D integration of MTJs is easily achieved because their fabrication is compatible with CMOS process [7]. Their high switching/sensing speed and non-volatility are exploited to overcome the major limitations of conventional devices such as high standby power and long delay for (re)configuration [5]. Moreover, the radiations hardness characteristic of MTJs enables the design of radiation tolerant circuits. Usually, hardening techniques are implemented by either technological solution (i.e. silicon on insulator SOI etc.) or by adding redundant blocks [8-9]. In this paper, we present a new design of Magnetic Look-Up-Table (MLUT). Based on a Pre-Charged Sense Amplifier (PCSA) [10], it features radiation hardness, high computing speed and low power. As MTJs are arranged in cross-point array structure [11], multi-context configuration can be easily implemented providing dynamic reconfiguration capability. A. Koch et al. (Eds.): ARC 2011, LNCS 6578, pp. 275–280, 2011. © Springer-Verlag Berlin Heidelberg 2011
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By using an accurate Thermally Assisted Switching (TAS) MTJ model [12-13] and CMOS 130nm technology [14], simulations have been performed to confirm the behaviour of this MLUT and demonstrate its expected performances.
2 Architecture of Magnetic Look-Up Table (MLUT) Figure 1-a shows a simplified diagram of conventional Magnetic Look-Up-Table (MLUT) [5-6]. A Sense Amplifier (SA) reads the binary information stored is a couple of MTJs [15]. Both play the role of one SRAM/flash memory point to save configuration data.
Fig. 1. Circuit and architecture implementation: (a) Architecture of conventional MLUT (b) New architecture of MLUT (c) Detailed schematic of new MLUT
A simplified diagram of the new MLUT is presented on Fig. 1-b. The SA is shifted to the output of a two branches MUX. Hence, only one SA is shared for all memory points. The detailed schematic is presented on Fig. 1-c, which is composed of three main parts: 1. A Pre-Charged Sense Amplifier (PCSA) shown on Fig. 2, [10]. Formed by transistors P1 to P4 and N3 to N5, it senses the LUT data stored in couples of MTJs by the falling edge of signal “Sense”. The frequency of “Sense” is equal to the frequency of data A and B in normal mode but it could be improved up to the chip clock in highest computing speed mode. As we previously demonstrated, the PCSA features high reliability and low power compared to state-of-the-art SA [10]. 2. A cross-point MTJ array, organized in M contexts addressed by selection signals such as “SEL_X/Y” (see Fig. 1- c). Each context is composed of 2N couples of MTJs (i.e. 2N bits) to implement N-input logic functions. As there is only one additional selection transistor per context, multiple contexts can be easily implemented without any footprint overhead.
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3. A logic block generates the control signals required for the operation of MLUT: “Sense”, “SEL_Context” and “EN_Compute” for logic computation and dynamic reconfiguration; “Bit_0 to 3” and “EN_Heat” generate the signals “EN_H_0 to 3” for context programming through TAS-MTJ switching approach [13].
Fig. 2. Detail circuit of Pre-Charged Sense Amplifier (PCSA). There are four PMOS transistors (P1-P4) and three NMOS transistors (N3-N5). By using the MUX, the couple of MTJs for sensing can be selected, for example, (X, left, 0) and (X, right, 0) refers to the couple of MTJs presenting bit number 0 in the context X.
3 Simulated Performances The functional behaviour of the MLUT is studied through transient simulations by using CMOS 130nm design kit [14] and an accurate TAS-MTJ model [12]. The default MTJ nanopillar is BiFe(10)/IrMn(6)/CoFe(1)/MgO(1.2)/CoFe(3)/PtMn(6). Fig. 3 shows a representative cycle that includes three operations: 1. Logic computation: As contexts X or Y are selected for reading (from 0 to 200ns and from 400ns to 600ns), MLUT begins logic computation (Fig. 3-a). The data stored in the configuration memory of context X/Y is available on the output of the MLUT. This simulates two different logical functions according to the value of inputs A & B (Fig. 3-d & e) and to the data stored in different contexts (X1 = A, ഥ +B, X2 = A ഥ and Y2 = AB ഥ . The whole logic delay for the calculated data to Y1 = A be available on the output is as low as 300ps including a rise time of (~100ps) for “Sense” signal. This corresponds to a maximum operating frequency of 3.3 GHz. 2. Dynamic reconfiguration between different configuration contexts: This operation means that the MLUT changes dynamically its logical function. This occurs when the control signal “Select X/Y” switches from Read X to Read Y (see Fig. 3-c). ഥ +B could The reconfiguration of MLUT between two contexts X1 = A and Y1 = A be very fast, lower than 1ns. 3. Context programming: The two contexts can be dynamically (re)-programmed to ഥ and Y2 = AB ഥ in about 200ns while the previous calculated result logic ‘1’ X2 = A remains latched (see Fig. 3-a).
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Fig. 3. Transient simulation of 2-input MLUT with 2 contexts (X/Y): (a) Output of MLUT (b) Sequence control signal “Sense” (c) Select context X and Y (d) Input data “A” (e) Input data “B” (f) Control signal “EN_Compute”
Fig. 4. Transient simulation TAS Writing operation: (a) State of an MTJ (b) Temperature of the same MTJ (c) Current flowing through MTJ during heating operation (d) Control signal “En_Heat” (e) Switching current, triggered when the MTJ temperature reaches ~150°C
The programming operation is show on Fig. 4. We use the Thermally Assisted Switching (TAS) approach [13]. The programming starts as the control signal “En_Heat” is active; a current passes through the selected MTJ and heats it. when its local temperature reaches up to the blocking temperature (~150°C) of antiferromagnetic IrMn layer associated with the free layer [12-13], a magnetic field is generated to align the magnetization of the free layer of MTJ and thus change its state (Fig. 4-a) from P to AP or vice-versa. The programming is accomplished when the MTJs cool down to about 100°C. Benefiting from a parallel programming architecture [16], the whole operation requires only 27ns to program all the bits of a context.
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The simulation shows also low power dissipation of MLUT. Firstly, its static power is reduced down to nearly zero as MTJ does not require power to keep data in standby mode. Secondly, during logic computation, PCSA consumes only low dynamic energy. It dissipates ~3 fJ/bit in computing mode and ~72 pJ/bit in context programming mode. The latter comes mainly from the heating/switching currents of TAS operation. It is important to note that new switching technologies under investigation such as Spin Transfer Torque (STT) allow the switching power to be minimized in the future [3].
4 Radiation Hardness In microelectronic circuits, the sensitive nodes presenting logic value with charge can be struck by ions or electro-magnetic radiation and this leads to state change from logic ‘0’ to ‘1’ or vice-versa at a relatively low frequency, [8-9]. This effect is called Single Event Upset (SEU) or soft error, which happens more frequently as the altitude increases. In order to resist to radiation, logic circuits need special design with the sacrifice of power, die area or speed. For example, flash and anti-fuse based reconfigurable logic circuits are often used in space applications with lower computing speed and the loss of reconfigurability [9]. Conventional MLUT structure use nearly the same number of sensitive nodes as SRAM based LUT (see Fig. 1-a), which limits its hardness during circuit computing. The new architecture of the MLUT enhances the immunity to radiations thanks to the reduction of sensitive points. The tolerance to radiation could also be improved by increasing the frequency of “Sense” in order to operate more sensing actions. Thus, if a disturbance occurs during the MLUT computing, the correct value is available after another sensing operation.
5 Conclusion In this paper, we presented a new design of MLUT. Its architecture with one sensitive point per logic gate and PCSA allows better radiation hardness, higher reliability and lower power consumption compared with previous MLUT designs while keeping high reconfiguration/computing speed. A cross-point array of MTJ sharing many peripheral circuits is used to store the multi-context configuration. This provides highspeed dynamic reconfiguration, enhances the fault tolerance capacity and increases greatly the embedded logic density. By using an accurate MTJ model and CMOS 130nm design kit, hybrid simulations of this MLUT confirm its functional behaviour and demonstrate its interesting performances in terms of power and computing/reconfiguration speed etc. High-speed performance and high power efficiency make MLUT become one of the most promising candidates to replace conventional LUT in the future and this new design opens the door for MLUT based reconfigurable circuits to be developed for aerospace, security and defense applications.
Acknowledgment The authors wish to acknowledge the support from the French national projects CILOMAG and NANOINNOV SPIN. We thank also G. PRENAT, B. DIENY from
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SPINTEC laboratory for decisive inputs scientific discussions and crucial help, O. REDON from CEA LETI, K. TORKI and G. DIPENDINA from CMP.
References 1. Brown, S., Francis, R., Rose, J., Vranesic, Z.: Field-programmable gate arrays. Kluwer Academic Publishers, Dordrecht (1992) 2. Virtex-III data sheet, http://www.xilinx.com 3. Chappert, C., Fert, A., Nguyen Van Dau, F.: The emergence of spin electronics in data storage. Nature Materials 6, 813–823 (2007) 4. Lakys, Y., Zhao, W.S., Klein, J.O., Chappert, C.: Low Power, High Reliablity Magnetic Flip-Flop. Electronics Letters 46(22), 1493–1494 (2010) 5. Zhao, W.S., Belhaire, E., Chappert, C., Mazoyer, P.: Spin Transfer Torque (STT)-MRAM based Run Time Reconfiguration FPGA circuit. ACM Transactions on Embedded Computing Systems 9(2), article 14 (2009) 6. Guillemenet, Y., et al.: Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories. Computers & Digital Techniques, IET 4(3), 211–226 (2010) 7. Matsunaga, S., et al.: Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions. Appl. Phys. Express (APEX) 1(9), 091301-1–091301-3 (2008) 8. Yu, F.X., Liu, J.R., Huang, Z.L., Luo, H., Lu, Z.M.: Overview of radiation hardening techniques for IC design. Inform. Technol. J. 6, 1068–1080 (2010) 9. Dupont, E., et al.: Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances, http://www.actel.com/documents/RadResultsIROCreport.pdf 10. Zhao, W.S., Chappert, C., Javerliac, V., Noziere, J.P.: High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits. IEEE Transactions on Magnetic 45(10), 3784–3787 (2009) 11. Chaudhuri, S., Zhao, W.S., Klein, J.O., Chappert, C., Mazoyer, P.: Design of TAS-MRAM Prototype for NV Embedded memory Applications. In: Proc. of International Memory Workshop, Korea, pp. 152–155 (2010) 12. Elbaraji, M., Javerliac, V., Guo, W., Prenat, G., Dieny, B.: Dynamic compact model of thermally assisted switching magnetic tunnel junctions. Journal of Applied Physics, 123906 (2010) 13. TAS MRAM technology, http://www.crocus-technology.com 14. STMicroelectronics, Manual of design kit for CMOS 130nm (2006) 15. Zhao, W.S., Belhaire, E., Chappert, C., Jacquet, F., Mazoyer, P.: New non-volatile logic based on Spin-MTJ. Physica Status Solidi-a: Applications and Material Science 205(6), 1373–1377 (2008) 16. Zhao, W.S., Belhaire, E., Dieny, B., Prenat, G., Chappert, C.: TAS-MRAM based Nonvolatile FPGA logic circuit. In: IEEE International Conference on Field-Programmable Technology (IEEE-ICFPT), Kitakyushu, Japan, pp. 153–161 (2007)
Abstract. Thanks to its non-volatility, high write/sense speed and small size, Magnetic Tunnel Junction (MTJ) is under investigation to be integrated in the future reconfigurable computing circuits offering higher power efficiency and performance. Another advantage of MTJ is that it provides good radiation hardness compared with other storage technologies used in reconfigurable computing circuits. In this paper, we present a design of Magnetic Look-Up-Table (MLUT) performing radiation hardness and keeping high reconfiguration /computing speed, high reliability and low power. Simulation results using an accurate model of MTJ and CMOS 130nm design kit confirm its expected performances in terms of reliability, power and speed. Keywords: Hybrid Design, High Reliability, MLUT, Radiation Hardness.
1 Introduction Look-Up Table (LUT) is one of the important building blocks for reconfigurable computing devices [1]. This element requires memory points currently based on SRAM or flash technologies [2]. Recently, Magnetic Tunnel Junction (MTJ) [3] has demonstrated a great potential for integration as memory elements into embedded and reconfigurable systems such as FPGA [4-6]. This new memory intends to replace SRAM that need high standby power and relatively slow flash memory. In addition, 3D integration of MTJs is easily achieved because their fabrication is compatible with CMOS process [7]. Their high switching/sensing speed and non-volatility are exploited to overcome the major limitations of conventional devices such as high standby power and long delay for (re)configuration [5]. Moreover, the radiations hardness characteristic of MTJs enables the design of radiation tolerant circuits. Usually, hardening techniques are implemented by either technological solution (i.e. silicon on insulator SOI etc.) or by adding redundant blocks [8-9]. In this paper, we present a new design of Magnetic Look-Up-Table (MLUT). Based on a Pre-Charged Sense Amplifier (PCSA) [10], it features radiation hardness, high computing speed and low power. As MTJs are arranged in cross-point array structure [11], multi-context configuration can be easily implemented providing dynamic reconfiguration capability. A. Koch et al. (Eds.): ARC 2011, LNCS 6578, pp. 275–280, 2011. © Springer-Verlag Berlin Heidelberg 2011
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By using an accurate Thermally Assisted Switching (TAS) MTJ model [12-13] and CMOS 130nm technology [14], simulations have been performed to confirm the behaviour of this MLUT and demonstrate its expected performances.
2 Architecture of Magnetic Look-Up Table (MLUT) Figure 1-a shows a simplified diagram of conventional Magnetic Look-Up-Table (MLUT) [5-6]. A Sense Amplifier (SA) reads the binary information stored is a couple of MTJs [15]. Both play the role of one SRAM/flash memory point to save configuration data.
Fig. 1. Circuit and architecture implementation: (a) Architecture of conventional MLUT (b) New architecture of MLUT (c) Detailed schematic of new MLUT
A simplified diagram of the new MLUT is presented on Fig. 1-b. The SA is shifted to the output of a two branches MUX. Hence, only one SA is shared for all memory points. The detailed schematic is presented on Fig. 1-c, which is composed of three main parts: 1. A Pre-Charged Sense Amplifier (PCSA) shown on Fig. 2, [10]. Formed by transistors P1 to P4 and N3 to N5, it senses the LUT data stored in couples of MTJs by the falling edge of signal “Sense”. The frequency of “Sense” is equal to the frequency of data A and B in normal mode but it could be improved up to the chip clock in highest computing speed mode. As we previously demonstrated, the PCSA features high reliability and low power compared to state-of-the-art SA [10]. 2. A cross-point MTJ array, organized in M contexts addressed by selection signals such as “SEL_X/Y” (see Fig. 1- c). Each context is composed of 2N couples of MTJs (i.e. 2N bits) to implement N-input logic functions. As there is only one additional selection transistor per context, multiple contexts can be easily implemented without any footprint overhead.
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3. A logic block generates the control signals required for the operation of MLUT: “Sense”, “SEL_Context” and “EN_Compute” for logic computation and dynamic reconfiguration; “Bit_0 to 3” and “EN_Heat” generate the signals “EN_H_0 to 3” for context programming through TAS-MTJ switching approach [13].
Fig. 2. Detail circuit of Pre-Charged Sense Amplifier (PCSA). There are four PMOS transistors (P1-P4) and three NMOS transistors (N3-N5). By using the MUX, the couple of MTJs for sensing can be selected, for example, (X, left, 0) and (X, right, 0) refers to the couple of MTJs presenting bit number 0 in the context X.
3 Simulated Performances The functional behaviour of the MLUT is studied through transient simulations by using CMOS 130nm design kit [14] and an accurate TAS-MTJ model [12]. The default MTJ nanopillar is BiFe(10)/IrMn(6)/CoFe(1)/MgO(1.2)/CoFe(3)/PtMn(6). Fig. 3 shows a representative cycle that includes three operations: 1. Logic computation: As contexts X or Y are selected for reading (from 0 to 200ns and from 400ns to 600ns), MLUT begins logic computation (Fig. 3-a). The data stored in the configuration memory of context X/Y is available on the output of the MLUT. This simulates two different logical functions according to the value of inputs A & B (Fig. 3-d & e) and to the data stored in different contexts (X1 = A, ഥ +B, X2 = A ഥ and Y2 = AB ഥ . The whole logic delay for the calculated data to Y1 = A be available on the output is as low as 300ps including a rise time of (~100ps) for “Sense” signal. This corresponds to a maximum operating frequency of 3.3 GHz. 2. Dynamic reconfiguration between different configuration contexts: This operation means that the MLUT changes dynamically its logical function. This occurs when the control signal “Select X/Y” switches from Read X to Read Y (see Fig. 3-c). ഥ +B could The reconfiguration of MLUT between two contexts X1 = A and Y1 = A be very fast, lower than 1ns. 3. Context programming: The two contexts can be dynamically (re)-programmed to ഥ and Y2 = AB ഥ in about 200ns while the previous calculated result logic ‘1’ X2 = A remains latched (see Fig. 3-a).
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Fig. 3. Transient simulation of 2-input MLUT with 2 contexts (X/Y): (a) Output of MLUT (b) Sequence control signal “Sense” (c) Select context X and Y (d) Input data “A” (e) Input data “B” (f) Control signal “EN_Compute”
Fig. 4. Transient simulation TAS Writing operation: (a) State of an MTJ (b) Temperature of the same MTJ (c) Current flowing through MTJ during heating operation (d) Control signal “En_Heat” (e) Switching current, triggered when the MTJ temperature reaches ~150°C
The programming operation is show on Fig. 4. We use the Thermally Assisted Switching (TAS) approach [13]. The programming starts as the control signal “En_Heat” is active; a current passes through the selected MTJ and heats it. when its local temperature reaches up to the blocking temperature (~150°C) of antiferromagnetic IrMn layer associated with the free layer [12-13], a magnetic field is generated to align the magnetization of the free layer of MTJ and thus change its state (Fig. 4-a) from P to AP or vice-versa. The programming is accomplished when the MTJs cool down to about 100°C. Benefiting from a parallel programming architecture [16], the whole operation requires only 27ns to program all the bits of a context.
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The simulation shows also low power dissipation of MLUT. Firstly, its static power is reduced down to nearly zero as MTJ does not require power to keep data in standby mode. Secondly, during logic computation, PCSA consumes only low dynamic energy. It dissipates ~3 fJ/bit in computing mode and ~72 pJ/bit in context programming mode. The latter comes mainly from the heating/switching currents of TAS operation. It is important to note that new switching technologies under investigation such as Spin Transfer Torque (STT) allow the switching power to be minimized in the future [3].
4 Radiation Hardness In microelectronic circuits, the sensitive nodes presenting logic value with charge can be struck by ions or electro-magnetic radiation and this leads to state change from logic ‘0’ to ‘1’ or vice-versa at a relatively low frequency, [8-9]. This effect is called Single Event Upset (SEU) or soft error, which happens more frequently as the altitude increases. In order to resist to radiation, logic circuits need special design with the sacrifice of power, die area or speed. For example, flash and anti-fuse based reconfigurable logic circuits are often used in space applications with lower computing speed and the loss of reconfigurability [9]. Conventional MLUT structure use nearly the same number of sensitive nodes as SRAM based LUT (see Fig. 1-a), which limits its hardness during circuit computing. The new architecture of the MLUT enhances the immunity to radiations thanks to the reduction of sensitive points. The tolerance to radiation could also be improved by increasing the frequency of “Sense” in order to operate more sensing actions. Thus, if a disturbance occurs during the MLUT computing, the correct value is available after another sensing operation.
5 Conclusion In this paper, we presented a new design of MLUT. Its architecture with one sensitive point per logic gate and PCSA allows better radiation hardness, higher reliability and lower power consumption compared with previous MLUT designs while keeping high reconfiguration/computing speed. A cross-point array of MTJ sharing many peripheral circuits is used to store the multi-context configuration. This provides highspeed dynamic reconfiguration, enhances the fault tolerance capacity and increases greatly the embedded logic density. By using an accurate MTJ model and CMOS 130nm design kit, hybrid simulations of this MLUT confirm its functional behaviour and demonstrate its interesting performances in terms of power and computing/reconfiguration speed etc. High-speed performance and high power efficiency make MLUT become one of the most promising candidates to replace conventional LUT in the future and this new design opens the door for MLUT based reconfigurable circuits to be developed for aerospace, security and defense applications.
Acknowledgment The authors wish to acknowledge the support from the French national projects CILOMAG and NANOINNOV SPIN. We thank also G. PRENAT, B. DIENY from
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Y. Lakys et al.
SPINTEC laboratory for decisive inputs scientific discussions and crucial help, O. REDON from CEA LETI, K. TORKI and G. DIPENDINA from CMP.
References 1. Brown, S., Francis, R., Rose, J., Vranesic, Z.: Field-programmable gate arrays. Kluwer Academic Publishers, Dordrecht (1992) 2. Virtex-III data sheet, http://www.xilinx.com 3. Chappert, C., Fert, A., Nguyen Van Dau, F.: The emergence of spin electronics in data storage. Nature Materials 6, 813–823 (2007) 4. Lakys, Y., Zhao, W.S., Klein, J.O., Chappert, C.: Low Power, High Reliablity Magnetic Flip-Flop. Electronics Letters 46(22), 1493–1494 (2010) 5. Zhao, W.S., Belhaire, E., Chappert, C., Mazoyer, P.: Spin Transfer Torque (STT)-MRAM based Run Time Reconfiguration FPGA circuit. ACM Transactions on Embedded Computing Systems 9(2), article 14 (2009) 6. Guillemenet, Y., et al.: Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories. Computers & Digital Techniques, IET 4(3), 211–226 (2010) 7. Matsunaga, S., et al.: Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions. Appl. Phys. Express (APEX) 1(9), 091301-1–091301-3 (2008) 8. Yu, F.X., Liu, J.R., Huang, Z.L., Luo, H., Lu, Z.M.: Overview of radiation hardening techniques for IC design. Inform. Technol. J. 6, 1068–1080 (2010) 9. Dupont, E., et al.: Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances, http://www.actel.com/documents/RadResultsIROCreport.pdf 10. Zhao, W.S., Chappert, C., Javerliac, V., Noziere, J.P.: High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits. IEEE Transactions on Magnetic 45(10), 3784–3787 (2009) 11. Chaudhuri, S., Zhao, W.S., Klein, J.O., Chappert, C., Mazoyer, P.: Design of TAS-MRAM Prototype for NV Embedded memory Applications. In: Proc. of International Memory Workshop, Korea, pp. 152–155 (2010) 12. Elbaraji, M., Javerliac, V., Guo, W., Prenat, G., Dieny, B.: Dynamic compact model of thermally assisted switching magnetic tunnel junctions. Journal of Applied Physics, 123906 (2010) 13. TAS MRAM technology, http://www.crocus-technology.com 14. STMicroelectronics, Manual of design kit for CMOS 130nm (2006) 15. Zhao, W.S., Belhaire, E., Chappert, C., Jacquet, F., Mazoyer, P.: New non-volatile logic based on Spin-MTJ. Physica Status Solidi-a: Applications and Material Science 205(6), 1373–1377 (2008) 16. Zhao, W.S., Belhaire, E., Dieny, B., Prenat, G., Chappert, C.: TAS-MRAM based Nonvolatile FPGA logic circuit. In: IEEE International Conference on Field-Programmable Technology (IEEE-ICFPT), Kitakyushu, Japan, pp. 153–161 (2007)
