Modeling and stability analysis of a simulation - Semantic Scholar
Simulation Modelling Practice and Theory 15 (2007) 734–746 www.elsevier.com/locate/simpat
Modeling and stability analysis of a simulation– stimulation interface for hardware-in-the-loop applications Saffet Ayasun a
a,*
, Robert Fischl b, Sean Vallieu b, Jack Braun c, Dilek C ¸ adırlı
a
Department of Electrical and Electronics Engineering, Nigde University, 51100 Nigde, Turkey b F&H Applied Science Associates, Inc., 900 Briggs Rd. Mt. Laurel, NJ 08054, USA c Burlington County College, County Route 530, Pemberton, NJ 08068, USA
Received 1 September 2006; received in revised form 18 January 2007; accepted 30 March 2007 Available online 5 April 2007
Abstract This paper presents the stability evaluation of a Simulation–Stimulation (Sim–Stim) interface that integrates hardware to software to perform Hardware-In-the-Loop (HIL) studies for testing and developing electrical equipment. Modeling issues of such an interface are discussed and a practical Sim–Stim interface model whose parameters are sampling rate and time delay is developed for the theoretical evaluation of the stability. The developed Sim–Stim interface model is applied to a low power DC system and closed-loop stability of the resulting HIL system is studied analytically in terms of time delay and sampling rate. A prototype of Sim–Stim interface is designed and realized to validate theoretical stability results using HIL simulation. Ó 2007 Elsevier B.V. All rights reserved. Keywords: Hardware-in-the-loop simulation; Simulation–stimulation interface; Power supply emulator; Load emulator; Modeling; Time delay; Stability
1. Introduction Hardware-in-the-loop (HIL) simulation is an effective method to design, develop and test new hardware and/or systems. Within HIL environment, a real hardware to be tested interacts with a virtual system (i.e., a simulation based mathematical model) that replaces part of a real system or component. The main advantage of using the HIL approach is that the critical equipment can be tested in a variety of scenarios of operation without: (i) The need to build an actual or scale down version of the system in which the equipment will be installed; (ii) the need to develop a validated model of the equipment for inclusion in a computer simulation. Hence, HIL techniques can provide lower cost and faster implementation than the conventional ways of testing equipment. Because of these advantages, the HIL simulation has been extensively used as a design step in a wide range of fields such as: traction control and anti-lock braking system [1], testing the controls for an *
Corresponding author. Tel.: +90 388 225 2301; fax: +90 388 225 0112. E-mail addresses: [email protected], saff[email protected] (S. Ayasun), rfi[email protected] (R. Fischl), svallieu@ fhasa.com (S. Vallieu), [email protected] (J. Braun), [email protected] (D. C ¸ adırlı). 1569-190X/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.simpat.2007.03.002
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electrical locomotive system [2], performance evaluation of a commercial motor used for drive-train of hybrid vehicles [3], automatic synchronization of generators in power systems [4], testing and controlling for power electronics equipment [5,6], designing a real-time test bed for power quality assessment [7], digital control system for magnetic levitation system [8]. The key element of HIL simulation is the interface between the simulation model and hardware. Although the applications may vary, a commonality of HIL approaches is that there is only signal coupling (low-level control signals) between the hardware and the virtual system. In this way, the monitoring and controlling hardware can be easily achieved. In order to take the advantage of virtual prototyping in the design and testing of power hardware, some recent studies have extended the HIL concept to a more interesting and challenging case where a real power must be virtually exchanged between the simulation and the actual hardware [9–11]. We denote this HIL by Power-Hardware-in-the-Loop (PHIL) system to differentiate it from the signal based HIL systems. The PHIL system can evaluate the performance of power hardware components (Hardware-Under-Test, HUT) as if they were operating in an actual power system environment. The objective of the PHIL is to test/diagnose power components (such as RL-load, induction motor, generator, power converter, uninterruptible power supplies, UPS, etc.) as if they were connected to a real system represented by a simulation model. The key to an effective PHIL is the interface called Simulation–Stimulation (Sim–Stim) interface (shown in Fig. 1) that connects the Hardware-Under-Test (HUT) with the Virtual Electrical System (VES). The VES is a computer program that simulates the electrical system in which the HUT will be implemented in an actual operation. The interface consists of sensors plus Analog-to-Digital Converters (ADC) in the feedback part and Digital-to-Analog Converters (DAC) plus a power source/sink in the feedforward part. Since the VES output will be either a current or voltage, the power source must be a current- or voltage-source inverter/converter. It must be noted that the Sim–Stim interface must be able to both deliver and absorb real power depending on the type of the HUT. If the HUT is a load such as a micro-grid or induction motor, then the VES models the power generation and distribution system, and the Sim–Stim interface delivers power. On the other hand, if the HUT is a source such as a generator, battery, fuel cell, or distribution system, then the Sim–Stim interface absorbs power. The Sim–Stim interface translates the computed VES power information output (e.g. voltage, current, frequency, phase, harmonics, etc.) via the DAC and power source/sink into real energy which powers to the HUT (feedforward). Moreover, the Sim–Stim interface also monitors HUT and supplies information on its operating states to the VES via the sensors and ADC (feedback), thus allowing closed-loop, real-time interaction between the HUT and the VES as if the HUT were connected to a real system. The requirement to deliver power to HUT differentiates PHIL from the traditional HIL systems that deal only with low-level control signals (e.g. small voltages/currents) for digital logic purposes or servo-control. Ideally, the HUT should perform the same whether it is a part of a real system or connected to the PHIL system. In other words, from the HUT’s point of view, it should be unable to distinguish between being connected either to the VES via the Sim–Stim interface or to a real system. This means that the interface should not introduce any characteristics that might alter the operation of the HUT. For the PHIL system of Fig. 1 to perform electrically in the same manner as the original system (without the interface), the Sim–Stim interface must be seamless in terms of real-time performance of the power system for various operating conditions such
Fig. 1. Structure of the PHIL system showing the Sim–Stim interface, VES and HUT.
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as steady-state operation (i.e., load flow, power transfer, and power quality) and dynamic operation (i.e., stability, on and off switching, etc.). That is, the Sim–Stim interface must be lossless to maintain the same power quality, have unity gain, and infinite bandwidth and dynamic range, and not introduce additional dynamics. However, in the actual hardware implementation of the interface using a power converter, a certain level of power loss will occur. If not properly quantified, this loss can affect the designed PHIL experiment. For a seamless operation of the interface during the actual realization, any power loss encountered must be compensated for within the VES. In addition, the presence of the Sim–Stim interface in the PHIL system can introduce additional dynamics and time delays into the system both in the feedforward and feedback paths. Time delays and other interface parameters such as sampling rate, quantization and saturation may adversely affect the stability performance of the PHIL system [12]. Thus, in an actual implementation, to provide a matched performance of the HUT as compared to when it is connected to a real system, certain measures must be accounted within the VES to account for these additional effects. For example, to account for quantifiable delays in the Sim–Stim interface, optimal control schemes may be utilized that use receding horizon schemes for improved predictive control inputs [13]. But before this actual implementation it is necessary to understand this novel PHIL system in terms of its operational limits or its stability. Since an ideal Sim–Stim interface cannot be realized, there is a need to develop a mathematical model of the PHIL system (VES plus Sim–Stim interface) and a method of evaluating its stability. This study concentrates on the closed-loop stability of PHIL system of Fig. 1 and how the stability of such a hybrid system will be affected by the newly introduced Sim–Stim interface parameters. Similar to the networked control systems, time delays and sampling rate are the most significant interface parameters that could degenerate the stability performance of the system [14–17]. The Sim–Stim interface is the key component of the PHIL system that needs to be modeled for stability analysis. Therefore, this paper first gives an overview of modeling issues for such an interface and then discusses the parameters that must be included in the model depending on the phenomenon of interest. A realizable Sim–Stim interface model whose main parameters are sampling rate and time delay is developed for theoretical evaluation of stability using sampled-system theory [14]. The PHIL application of the proposed Sim–Stim interface is illustrated for a low power DC system. An RL load is chosen as being the HUT that is connected to a virtual model of DC source through the Sim–Stim interface. In order to evaluate the stability performance, a two-step approach is adopted. In the first step, a discrete-time model of the PHIL system is determined to investigate the stability analytically by means of stability regions in terms of sampling rate and time delay. The characterization of the stability using regions in the Sim–Stim interface parameter space (that is, sampling rate vs. time delay) is useful since it offers a set of acceptable interface parameters for which the PHIL system is stable. In the second step, a prototype of the Sim–Stim interface is designed and realized to validate theoretical stability results. Differences between theoretical and experimental stability results are also discussed in details. 2. Sim–Stim interface model 2.1. Modeling issues The key component of the PHIL system shown in Fig. 1 is the Sim–Stim interface that needs to be modeled for stability analysis. Fig. 2 illustrates the Sim–Stim interface partitioned as two major subsystems, the feed-
Fig. 2. Block diagram of the Sim–Stim interface in terms of the feed-forward (TF) and feedback (TB) maps.
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Fig. 3. A conceptual hardware realization of the Sim–Stim interface.
forward subsystem (D/A map), TF and the feedback subsystem (A/D map), TB. These subsystems provide bidirectional signal paths between the VES and the HUT. As shown in Fig. 1, the feedback A/D map consists of the power (voltage and current) sensors and an ADC. The feedforward D/A map is composed of a DAC and a power source/sink. The A/D map in the feedback part converts the continuous signal coming from the HUT to a quantized discrete signal while the D/A map converts the digital data coming from the VES into electric power quantities. Note that this representation is for a DC system or a single phase of a multi-phase system. The specific mapping TF and TB of the interface are determined by the type of components that define the boundary between HUT and VES subsystems, the type of HUT and VES architecture, and the phenomenon of interest. Mathematically the D/A and A/D maps can be represented as: Feedforward D/A map: v1 ðtÞ ¼ T F fz2 ½k; wF g ð1Þ Feedback A/D map: v2 ½k ¼ T B fz1 ðtÞ; wB g ð2Þ where v1(t) denotes continuous time power signals such as ac and/or dc voltage, current, power, etc. used to drive the HUT; z1(t) denotes analog sensor output signals measured at the HUT; v2[k] denotes digital signals (corresponding to sensor measurements, z1(t)) into the VES; z2[k] denotes digital data out of the VES which is converted by TF into power signals, v1(t), that drive the HUT; wF and wB are vectors denoting the key parameters of feedforward and feedback mappings that affect the performance of the PHIL system. wF and wB are best understood by looking at a conceptual hardware realization of the Sim–Stim interface shown in Fig. 3. Since the feedforward mapping consists of a DAC and power converter, the key parameters will include the DAC parameters such as sampling period hF, the conversion delays sF, and quantization qF, associated with the DAC; and the power converter parameters such as bandwidth, BWF dynamic range, DRF, switching frequency, fs, and output impedance, Z0, so wF ¼ ½ sF hF qF BWF DRF fs Z 0 T . Since the feedback mapping consists of the current/voltage sensors and an ADC, the key parameters are the sensors’ and ADC bandwidth, BWB, dynamic range, DRB, ADC sampling period, hB, quantization, qB, and the comT munication and conversion time delay, sB, so that the parameter vector wB ¼ ½ sB hB qB BWB DRB . To decide which of these parameters must be imbedded in the model, it is necessary to know the types of applications in which the PHIL system will be used (i.e., the type of power system that is studied such as AC, DC, or AC/DC and the HUT architecture) and phenomena of interest such as steady-state and/or dynamic stability, real power transfer and power quality. Depending on the PHIL application, certain assumptions on the dynamics of ADC, DAC and converter need to be made to develop an interface model containing appropriate parameters. In the following section, a mathematical model of the Sim–Stim interface for stability analysis is given. 2.2. (h, s) Sim–Stim interface The PHIL system shown in Fig. 1 is a closed-loop hybrid dynamical system similar to the networked control systems in which the network induced delays and sampling rate are the two significant parameters
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Fig. 4. PHIL system with the (h, s) Sim–Stim interface model.
that could degenerate the stability performance. The most critical Sim–Stim interface parameters for the stability performance evaluation of PHIL system are the sampling period (h) and time delays (sB and sF) observed in the feedback and feedforward parts of the interface. [12,15,16]. The time delays arise from the computational time in the VES and the processing time of ADC and DAC. In order to develop a practical interface model that allows the theoretical evaluation of stability, assumptions on the dynamics of ADC, DAC and power converter need to be made. For this purpose, in the feedback part of the interface it is assumed that the ADC is an ideal sampler with a sampling period, h (i.e., quantization and approximation errors are ignored). In the feedforward part, a Zero-Order-Hold (ZOH) circuit is selected for the DAC since it is commonly used in practice to convert digital signals to a series of rectangular pulses [14]. Finally, an ideal converter (i.e., dynamics are ignored and it has an infinite gain) is assumed for the power source to provide power to the HUT. The block diagram of the Sim–Stim interface model developed based on these assumptions is illustrated in Fig. 4. The ideal converter is represented by a voltage source. Note that a time delay (s) is introduced before the ZOH block. This delay represents the sum of the communication delays (sB and sF) from ADC to the VES in the feedback part and from the VES to the converter in the feedforward part as well as the processing delay observed in the VES. Since the Sim–Stim interface parameters are solely the time delay (s) and sampling period (h), this Sim–Stim interface model is called (h, s) Sim–Stim interface. The operation of PHIL system of Fig. 4 can be summarized as follows: First, the HUT quantities such as voltages and currents are sensed. These continuous signals z1(t) are then converted to digital signals, v2[k] = z1(t = tk) by the ideal sampler for input into the VES. The VES computed output signal, z2(tk) is delayed by (s) amount of time as to take into account the total delay in the loop and is fed into the ZOH block. Finally, the ZOH converts the digital signal to an analog one, which provides power to the HUT through a voltage source. The output of the ZOH, v1(t+) is a piecewise continuous voltage that only changes value at kh + s, and is defined as v1 ðtþ Þ ¼ z2 ½kh s pðtÞ;
t 2 fkh þ s; k ¼ 0; 1; 2; . . .g
ð3Þ
The ideal sampler defines the A/D map and its output is given as v2 ½k ¼ z1 ðt ¼ tk Þ;
tk ¼ kh; k ¼ 0; 1; 2; . . .
ð4Þ
where p(t) = [u(t) u(t s)] is a unit pulse of width h. This interface model has two essential features: (i) it is a very practical interface model that could easily be realized using readily available low-cost data acquisition (DAQ) cards, (ii) it is an analytically tractable model that enables to determine the discrete-time state-space model of the PHIL system for stability analysis. 3. Application of (h, s) Sim–Stim interface In this section, a low power DC PHIL system is used to illustrate the application of the (h, s) Sim–Stim interface and to analyze the stability in terms of the delay. Fig. 5 shows the block diagram of the PHIL system
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Fig. 5. Linear circuit application of the (h, s)-Sim–Stim interface.
under study. An RL impedance is chosen as being the HUT which is connected to a virtual model of a DC source with an internal resistance through the (h, s) Sim–Stim interface. The Sim–Stim interface parameters are the sampling period (h) and lumped time delay (s), which will affect the stability performance of the closed-loop hybrid dynamical system. In order to evaluate the stability performance of the PHIL system in Fig. 5, a two-step approach is adopted. In the first step, a discrete-time (DT) model of the system is determined to investigate the stability theoretically by obtaining region of stable operation in terms of Sim–Stim interface parameters w ¼ ½ h s T while the RL impedance parameters are fixed. In the second step, a prototype low power Sim–Stim interface is designed and realized to validate theoretical stability results. In the following section, theoretical evaluation of the stability is presented. 3.1. Theoretical analysis The PHIL system shown in Fig. 5 consists of a continuous subsystem (i.e., RL impedance as being HUT) and discrete subsystem (VES) acting upon the continuous HUT through the Sim–Stim interface. The dynamic of the HUT is described by a first-order differential equation diðtÞ ¼ aiðtÞ þ bvðtþ Þ; dt
t 2 ½kh þ s; ðk þ 1Þh þ s
ð5Þ
where a = R/L, b = 1/L. The driving voltage v(t+) is the output of the ZOH consists of a series of rectangular pulses whose value changes only at kh + s for k = 0, 1, 2, . . . The value of v(t+) is given by vðtþ Þ ¼ R0 iðt sÞ þ EðtÞ;
t 2 fkh þ s; k ¼ 0; 1; 2; . . .g
ð6Þ
Note that Eqs. (5) and (6) give the continuous-time (CT) model of the PHIL system. Although this model inT cludes the two Sim–Stim parameters, w ¼ ½ h s , they are included implicitly, and thus making it difficult to quantify how they affect the system stability. This can be overcome by obtaining a DT model of the PHIL system that will be done next. The DT model of the VES is given by V ½k ¼ R0 i½k þ E½k
ð7Þ
The value of i[k] is the sampled value of the current flowing in the HUT circuit. This current is due to the piecewise continuous voltage, v(t+), applied during the period (k 1)h 6 t < kh. This means that at most two voltage samples, v[k 1] and v[k] need to be considered when evaluating i[k] from the solution of the HUT model of Eq. (5). The sampled solution of Eq. (5) gives i[k] which is then combined with Eq. (7) to give the following DT state-space representation of the PHIL system for the case when the delay is less than or equal to sampling period {s 6 h} [14]:
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i½k þ 1
v½k
¼
U C0 R0
C1
i½k
v½k 1 R 0 |fflfflfflfflfflfflfflfflfflfflfflfflfflffl0{zfflfflfflfflfflfflfflfflfflfflfflfflfflffl}
þ
½Aaug
C0
1 |fflffl{zfflffl}
E½k
ð8Þ
½Baug
where U ¼ eah ;
C0 ¼ "
½Aaug ¼ " ½Baug ¼
Z
hs
eas ds b;
0 ah
e
b aðhsÞ ½e a
R0 b ðeaðhsÞ a
1Þ
1R0
eas ds b hs # b ah as e ½1 e a C1 ¼
Z
h
0
#
ð9Þ
1
When the delays are longer than one sampling period, (i.e., 0 < s < ‘h, ‘ > 1). The system matrix [Aaug] of Eq. (8) needs to be modified. In the special case where (‘ 1)h < s < ‘h for all k, one current sample is received every sample period for k > ‘. In this case, it follows from [14] that 2 3 U C1 ðs0 Þ C0 ðs0 Þ 0 6 0 0 I 07 6 7 ð10Þ ½Aaug ¼ 6 .. 7 .. .. .. 6 .. 7 4 . . .5 . . R0
0
0
0
where s 0 = s (‘ 1)h. The stability of the PHIL system is guaranteed if all the eigenvalues of the system matrix [Aaug] lie inside the unit circle: fjki ðAaug Þj ¼ jki ðwÞj < 1;
for i ¼ 1; 2; . . .g
ð11Þ
Note from Eq. (9) or (10), that the eigenvalues of the PHIL system, thus stability, are function of not only the T T system parameters / ¼ ½ R R0 L , but also Sim–Stim interface parameters w ¼ ½ h s . Moreover, even though the original system (i.e., RL impedance connected to the DC source without the Sim–Stim interface) is only first-order continuous system, the order of the DT model of the PHIL system has increased at least by one degree due to the introduction of the Sim–Stim interface. The effects of sampling period (h) and time delay (s) on stability performance of the PHIL system can be analyzed using the region of stable operation, SPHIL(wj/ = /0) in the Sim–Stim interface parameter space (i.e., h vs. s/h). The definition of the stability region is as follows: S PHIL ðwj/ ¼ /0 Þ ¼ fw : jki ðAaug ð/ ¼ /0 ; wÞÞj 6 1
8i; i ¼ 1; 2; . . .g
ð12Þ
where Aaug(/ = /0, w) is obtained from either Eq. (9) or (10) depending on the delay size and /0 defines a particular choice of system parameters. Fig. 6 shows the region of stable operation for R = 9.75 X, L = 0.08 H, R0 = 19.5 X and 0 < s < 12h. This region is plotted by incrementally increasing the delay and testing the system matrix of (9) or (10). If the system matrix is stable, a point is marked in that location of the stability region. The lower shaded area represents a set of h and s for which the system is stable. Such a region is helpful to determine how much delay the system can tolerate before it becomes unstable indicating the trade-off between the sampling period and delay. 3.2. Experimental validation A prototype of the Sim–Stim interface was designed and experimentally realized to validate the theoretical stability results presented in the previous section. Fig. 7 shows the experimental setup of the PHIL system of Fig. 5 indicating main hardware components of the Sim–Stim interface. As can be seen in Fig. 7, the experimental setup is composed of the followings: Virtual power system, DAQ card, power source, related control
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Fig. 6. Region of stable operation for R = 9.75 X, L = 0.08 H, R0 = 19.5 X and 0 < s < 12h.
Fig. 7. Block diagram of the experimental setup illustrating main hardware components of Sim–Stim interface.
and sense signals such as voltage control, voltage sense and current sense, and hardware-under-test consisting of two switched RL impedances. The value of each load is R = 19.5 X and L = 0.16 H. The Virtual Power System located in a Pentium III laptop PC. It is the virtual model of a DC source (Es) with an internal resistance (R0) and it was implemented in LabVIEW environment. LabVIEW is an object-oriented software programming tool that combines the advantages of graphical programming and high quality user interface tools [18,19]. The user interface ‘‘front panel’’ of LabVIEW has ready-to-go controls, such as graphs, knobs, and switches that can be manipulated by the programmer. The front panel can be constructed and viewed like a physical instrument, where the user can visualize the results on the computer screen. Fig. 8 shows the front panel of the experimental setup. It provides interactive control of the following system parameters: sampling period (h), time delay (s), the source voltage (Es), and source resistance (R0), and displays voltage across the RL load impedance. The LabVIEW program determines sampling period and time delay based on the ‘‘Scan Rate’’ (SR) control and ‘‘# of Sample to Delay ’’ control specified by the user. The sampling period is h = 1/SR and ‘‘ # of Sample to Delay ’’ represents the ratio of s/h. The front panel is driven by the G-language code or ‘‘block diagram’’, which is the actual code of the program. This program (i) prepares
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Fig. 8. The front panel of the PHIL experiment.
the DAQ system to accept data, (ii) allows interactive control of system parameters (s, h, Es, R0) through the front panel, and (iii) implements Sim–Stim interface equations. The hardware interface to the computer is a National Instruments NI DAQ-6024E, multifunction, low-cost DAQ card inserted into PCMCIA slot of the laptop. This DAQ and control card configured by LabVIEW has 16 analog inputs in a single-ended mode, two analog outputs and eight digital input/output lines. The maximum sampling rate for analog input is 200 kHz, and it has an accuracy of 12 bits [20]. The DAQ card is shown in the left side of the Sim–Stim interface box of Fig. 7. The Power Source of Sim–Stim interface box in Fig. 7 provides power to the RL impedance. It consists of an op-amp buffer in the non-inverting mode and a transistor operating as an emitter follower. The power source is controlled by the delayed Voltage Control signal that is the analog output of the DAQ card. The power may be obtained from an internal +5 V supply or an external supply if higher voltage/power is needed. The operation of the experimental setup can be summarized as follows: First, the RL impedance current is sensed and this analog signal is then converted to a digital signal using the DAQ card. The LabVIEW program computes a digital voltage control signal using Eq. (7). This control signal is delayed by the amount of time delay specified. The delayed control signal is converted to an analog one using the DAQ card and sent to the Power Source. The waveform of the voltage across the RL impedance can be displayed either in the front panel of the experiment (Fig. 8) or using an oscilloscope connected to output of the Sim–Stim interface (Fig. 7). The user can easily change the system parameters (s, h, Es, R0) in real-time in order to study interactively how they affect the output voltage and how much time delay the system can tolerate before loosing stability. In the following section, experimental stability results are compared with theoretical ones and reasons for differences are discussed. 4. Comparison of stability results The experimental validation studies for verifying the effects that the time delay (s) and sampling period (h) have on the stability performance were performed using the experimental setup shown in Fig. 7. In order to verify theoretical stability results shown in Fig. 6, two points (stable and unstable) were selected in the region. As can be seen from the left figure of Fig. 9, the stable point is the lower one with h = 1 ms and s/h = 2 while the unstable one is the upper point with h = 1 ms, s/h = 9. For each one, experiment was performed and voltage across the RL impedance was measured. The voltage waveforms are shown in the right figure of Fig. 9. For the stable point, the voltage reaches its steady-state value while for the unstable case a growing oscillation was observed. These measured results verify both stable and unstable operation of PHIL system predicted by theory. It is also essential to investigate whether there exists an experimental stability boundary between stable and unstable regions of operation similar to the theoretical stability boundary shown in Fig. 6. For this reason several experiments were performed using (h, s) data around the theoretical boundary. The experiment results
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Fig. 9. The stable and unstable operations of PHIL system validated by the experiment.
Fig. 10. Regions of stable, unstable and neutrally stable operation of the PHIL system.
indicate that there is a neutrally stable region of operation that occurs with the hardware realization of the Sim–Stim interface, rather than a sharp boundary between stable and unstable regions. Fig. 10 shows these three regions of operation for different sampling periods and delays and the corresponding voltage waveforms. The neutrally stable region is the region between two dashed lines. The upper dashed line is the boundary between unstable and neutrally stable regions while the lower one corresponds to the boundary between the stable and neutrally stable regions. As can be seen from the left figure of Fig. 10 the stable region of the experimental setup was larger than the one predicted by theory. It is felt that the larger stability region and the neutrally stable region occur due to hardware limitations such as limited bandwidth and gain dv/dt limits, drifts, finite dynamic range and circuit losses, which were not taken into account in theoretical stability analysis. 5. Discussions The proposed (h, s) Sim–Stim interface and the experimental setup shown in Fig. 7 could not be used to test and design power hardware components in a PHIL configuration because of its low power level. In order to
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Table 1 Potential application of power hardware in the loop(PHIL) Power application/level
Hardware-under-test (HUT)
Storage, conversion, distribution hardware Small: 1–10 kW Medium: 5–100 kW Large: >100 kW
Small–medium: batteries/fuel cells/controllers/converters/back-up generators/uninterruptible power supplies/flywheels Large: generators/prime movers/transformers/power supplies/etc.
take the advantage of virtual prototyping in the design and testing of power hardware, the Sim–Stim interface must be capable of power exchange at the level of kW. Table 1 indicates potential applications of the PHIL system and the power levels that it must deliver. The actual KVA or KW rating of the power hardware-undertest will depend on the power capability of the power converter of the Sim–Stim interface. However, there are some limitations in designing and implementation of such a power interface. The main challenge in the implementation of the interface at high power level is to have a wide dynamic range with low latency. The investigation of power system issues such as stability, power transfer, response to harmonics, requires that the interface have very high bandwidth [21]. With respect to sensing, using a fast ADC with low latency such a high bandwidth could be easily obtained. Moreover, the computing delay could be significantly reduced using high performance computers in the VES. The major limitation comes from the design of an appropriate power converter that will be used as a power source/sink in the interface (as shown in Fig. 3). This limitation is related to the switching frequency of the power components and to the controller of the converter. Fast switching (1 MHz) is feasible using power MOSFET switching devices. In order to meet the high switching demands of such a power interface (>1 MHz), some recent studies have reported the development of gallium nitride (GaN) switching devices to be used in power converters for PHIL applications [22,23]. For the controller part of the converter, a discrete-time sliding mode control algorithm implemented in a FPGA has been proposed as an option for controlling a high-bandwidth power converter [24]. Incorporating all the capabilities of interest such as an adjustable frequency range, the ability to produce an arbitrary waveform and four quadrant operation, makes the associated power converter design a separate research effort. The incorporation of power electronic converters in the interface is a future capability, and as these devices become more readily available, their incorporation into PHIL configurations will follow the foundation being developed. For the case of non-linear load and complex VES models, analytical approach presented in Section 3.1 and (h, s) Sim–Stim interface model shown in Fig. 4 can not be used to investigate the closed-loop stability of the PHIL system with respect to sampling period and time delay. Simulation approach that implements PHIL simulation structure of Fig. 1 (with a power converter as a power source/sink) using an appropriate software tool should be adopted. Such a simulation model must replicate the characteristics of the real hybrid system through multi-rate integration. The HUT such as an induction motor, which exists in continuous-time, should be approximated by simulation model that is integrated with very small time step. The simulation model of VES, which is already a discrete-time model, should be integrated with longer time step than we plan to apply in the actual implementation. One possible simulation environment for PHIL applications is Virtual Test Bed (VTB) [25] designed for simulation and virtual prototyping of complex dynamic systems. In VTB environment, different solvers can interact using different time steps. VTB is a freely available software package developed at University of South Carolina (http://vtb.ee.sc.edu/).With its graphical user interface and extensive library of components including power electronic converters, electrical machinery, various types of electrical sources, measurement devices, electrical and mechanics loads, etc., VTB provides engineers and researchers with a modern and interactive design tool to build simulation models of dynamic systems rapidly and easily. 6. Conclusions In this paper, a Simulation–Stimulation interface for testing hardware for various operating conditions has been introduced and a hybrid model of the interface that includes two key parameters, time delay and sampling period has been developed for stability evaluation. The proposed interface has been applied to a linear
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circuit to illustrate its application and stability problems. Using the sampled-system theory, a discrete-time model of the linear PHIL system has been determined and trade-off between time delay and sampling period has been obtained by the region of stable operation. An experimental setup has been designed and realized for validation the theoretical stability results. A larger stability region compared to theoretical one and a neutrally stable region have been observed in the experimental studies. Results indicate the time delay is the major concern for the stability of the PHIL system. Further work will be performed to develop a Sim–Stim interface model that includes a power converter for PHIL applications. Using the steady-state and dynamic models of power interface to be developed, it will be feasible to evaluate the performance of power hardware components for various power operating phenomena such as load flow, real power transfer, power quality and stability. Acknowledgement This work was supported by the US Office of Naval Research (ONR) under Grant N00014-01-C-0045. References [1] D. Maclay, Simulation gets into loop, IEE Rev. 5 (1997) 109–112. [2] P. Terwiesch, T. Keller, E. Scheiben, Rail vehicle control system integration testing using digital hardware in-the-loop simulation, IEEE Trans. Contr. Syst. Technol. 7 (1999) 352–362. [3] C.O. Sung, Evaluation of motor characteristics for hybrid electric vehicles using hardware-in-the-loop concept, IEEE Trans. Vehicular Technol. 54 (2005) 817–824. [4] A.J. Grono, Synchronizing generators with HITL simulation, IEEE Comput. Appl. Power 14 (2001) 43–46. [5] V.R. Dinavahi, M.R. Iravani, R. Bonert, Real-time digital simulation of power electronic apparatus interfaced with digital controllers, IEEE Trans. Power Delivery 16 (2001) 775–781. [6] A. Monti, E. Santi, R. Dougal, M. Riva, Rapid prototyping of digital controls for power electronics, IEEE Trans. Power Electron. 18 (2003) 915–923. [7] Y. Liu, M. Steurer, P. Riberiro, A novel approach to power quality assessment: real time hardware-in-the-loop test bed, IEEE Trans. Power Delivery 20 (2005) 1200–1201. [8] P.S. Shiakolas, D. Piyabongkarn, Development of a real-time digital control system with a hardware-in-the-loop magnetic levitation device for reinforcement of controls education, IEEE Trans. Educ. 46 (2003) 79–87. [9] S. Ayasun, S. Vallieu, R. Fischl, T. Chmielewski, Electric machinery diagnostic/testing system and power hardware-in-the-loop studies, in: Proceedings of the IEEE International Symposium on Diagnostics for Electric Machinery, Power Electronics and Drives (SDEMPED 2003), Atlanta, GA, 24–26 August 2003, pp. 361–366. [10] X. Wu, S. Lentijo, A. Monti, A novel interface for power-hardware-in-the-loop simulation, in: Proceedings of the IEEE Workshops on Computers and Power Electronics (COMPEL 2004), University of Illinois, Urbana, IL, 15–18 August 2004, pp. 178–182. [11] W. Zhu, S. Pekarek, J. Jatskevich, O. Wasynczuk, D. Delisle, A model-in-the-loop interface to emulate source dynamics in a Zonal DC distribution system, IEEE Trans. Power Electron. 20 (2005) 438–445. [12] S. Ayasun, A. Monti, R. Dougal, R. Fischl, S. Vallieu, On the stability of hardware in the loop simulation, in: Proceedings of the 7th International Conference on Modeling and Simulation of Electric Machines, Converters and Systems (ELECTRIMACS 2002), Montreal (Quebec), Canada, 18–21 August 2002, pp. 185–191. [13] Y.I. Lee, W.H. Kwon, Y.H. Kim, Weighted receding horizon predictive control and its related GPC with guaranteed stability, in: Proceedings of the 32nd IEEE Conference on Decision and Control, San Antonio, Texas, 15–17 December 1993, pp.1316–1321. [14] K.J. Astrom, B. Wittenmark, Computer-Controlled Systems: Theory and Design, third ed., Prentice-Hall, Englewood Cliffs, NJ, 1997. [15] W. Zhang, M.S. Branicky, M. Phillips, Stability of networked-control systems, IEEE Contr. Syst. Mag. 21 (2001) 84–99. [16] G.C. Walsh, H. Ye, L.G. Bushnell, Stability analysis of networked control systems, IEEE Trans. Contr. Syst. Technol. 10 (2002) 438– 446. [17] D. Yue, Q.L. Han, C. Peng, State feedback controller design of networked control systems, IEEE Trans. Circ. Syst.-II 51 (2004) 640– 644. [18] LabVIEW User Manual, National Instruments Corporation, 2002. [19] LabVIEW Measurements Manual, National Instruments Corporation, 2002. [20] DAQ 6024E User Manual, National Instruments Corporation, 2002. [21] A.Monti, H. Figueroa, X. Wu, R. Dougal, Interface issues in hardware-in-the-loop simulation, in: Proceedings of the IEEE Electric Ship Technical Symposium, Philadelphia, PA, July 2005, pp. 39–45. [22] S. Pytel, S. Lentijo, A. Koudymov, S. Rai, V. Adivarahan, J. Yang, J. Hudgins, E. Santi, A. Monti, AlGaN/GaN MOSHFET integrated circuit power converter, in: Proceedings of the IEEE Power Electronic Specialists Conference, Aachen, Germany, 20–25 June 2004, pp. 579–584.
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[23] M.A. Khan, G. Simin, S.G. Pytel, A. Monti, E. Santi, J.L. Hudgins, New developments in gallium nitride and the impact on power electronics, in: Proceedings of the IEEE Power Electronics Specialists Conference, Recife, Brazil, June 2005, pp. 15–26. [24] S. Lentijo, S. Pytel, A. Monti A., J. Hudgins, E. Santi, G. Simin, FPGA based sliding mode control for high frequency power converters, in: Proceedings of the IEEE Power Electronic Specialists Conference, Aachen, Germany, 20–25 June 2004, pp. 3588–3592. [25] R. Dougal, T. Lovett, A. Monti, E. Santi, A Multilanguage environment for interactive simulation and development of controls for power electronics, in: Proceedings of the IEEE Power Electronics Specialist Conference, Vancouver, CA, June 2001, pp. 1725–1729.
Modeling and stability analysis of a simulation– stimulation interface for hardware-in-the-loop applications Saffet Ayasun a
a,*
, Robert Fischl b, Sean Vallieu b, Jack Braun c, Dilek C ¸ adırlı
a
Department of Electrical and Electronics Engineering, Nigde University, 51100 Nigde, Turkey b F&H Applied Science Associates, Inc., 900 Briggs Rd. Mt. Laurel, NJ 08054, USA c Burlington County College, County Route 530, Pemberton, NJ 08068, USA
Received 1 September 2006; received in revised form 18 January 2007; accepted 30 March 2007 Available online 5 April 2007
Abstract This paper presents the stability evaluation of a Simulation–Stimulation (Sim–Stim) interface that integrates hardware to software to perform Hardware-In-the-Loop (HIL) studies for testing and developing electrical equipment. Modeling issues of such an interface are discussed and a practical Sim–Stim interface model whose parameters are sampling rate and time delay is developed for the theoretical evaluation of the stability. The developed Sim–Stim interface model is applied to a low power DC system and closed-loop stability of the resulting HIL system is studied analytically in terms of time delay and sampling rate. A prototype of Sim–Stim interface is designed and realized to validate theoretical stability results using HIL simulation. Ó 2007 Elsevier B.V. All rights reserved. Keywords: Hardware-in-the-loop simulation; Simulation–stimulation interface; Power supply emulator; Load emulator; Modeling; Time delay; Stability
1. Introduction Hardware-in-the-loop (HIL) simulation is an effective method to design, develop and test new hardware and/or systems. Within HIL environment, a real hardware to be tested interacts with a virtual system (i.e., a simulation based mathematical model) that replaces part of a real system or component. The main advantage of using the HIL approach is that the critical equipment can be tested in a variety of scenarios of operation without: (i) The need to build an actual or scale down version of the system in which the equipment will be installed; (ii) the need to develop a validated model of the equipment for inclusion in a computer simulation. Hence, HIL techniques can provide lower cost and faster implementation than the conventional ways of testing equipment. Because of these advantages, the HIL simulation has been extensively used as a design step in a wide range of fields such as: traction control and anti-lock braking system [1], testing the controls for an *
Corresponding author. Tel.: +90 388 225 2301; fax: +90 388 225 0112. E-mail addresses: [email protected], saff[email protected] (S. Ayasun), rfi[email protected] (R. Fischl), svallieu@ fhasa.com (S. Vallieu), [email protected] (J. Braun), [email protected] (D. C ¸ adırlı). 1569-190X/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.simpat.2007.03.002
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electrical locomotive system [2], performance evaluation of a commercial motor used for drive-train of hybrid vehicles [3], automatic synchronization of generators in power systems [4], testing and controlling for power electronics equipment [5,6], designing a real-time test bed for power quality assessment [7], digital control system for magnetic levitation system [8]. The key element of HIL simulation is the interface between the simulation model and hardware. Although the applications may vary, a commonality of HIL approaches is that there is only signal coupling (low-level control signals) between the hardware and the virtual system. In this way, the monitoring and controlling hardware can be easily achieved. In order to take the advantage of virtual prototyping in the design and testing of power hardware, some recent studies have extended the HIL concept to a more interesting and challenging case where a real power must be virtually exchanged between the simulation and the actual hardware [9–11]. We denote this HIL by Power-Hardware-in-the-Loop (PHIL) system to differentiate it from the signal based HIL systems. The PHIL system can evaluate the performance of power hardware components (Hardware-Under-Test, HUT) as if they were operating in an actual power system environment. The objective of the PHIL is to test/diagnose power components (such as RL-load, induction motor, generator, power converter, uninterruptible power supplies, UPS, etc.) as if they were connected to a real system represented by a simulation model. The key to an effective PHIL is the interface called Simulation–Stimulation (Sim–Stim) interface (shown in Fig. 1) that connects the Hardware-Under-Test (HUT) with the Virtual Electrical System (VES). The VES is a computer program that simulates the electrical system in which the HUT will be implemented in an actual operation. The interface consists of sensors plus Analog-to-Digital Converters (ADC) in the feedback part and Digital-to-Analog Converters (DAC) plus a power source/sink in the feedforward part. Since the VES output will be either a current or voltage, the power source must be a current- or voltage-source inverter/converter. It must be noted that the Sim–Stim interface must be able to both deliver and absorb real power depending on the type of the HUT. If the HUT is a load such as a micro-grid or induction motor, then the VES models the power generation and distribution system, and the Sim–Stim interface delivers power. On the other hand, if the HUT is a source such as a generator, battery, fuel cell, or distribution system, then the Sim–Stim interface absorbs power. The Sim–Stim interface translates the computed VES power information output (e.g. voltage, current, frequency, phase, harmonics, etc.) via the DAC and power source/sink into real energy which powers to the HUT (feedforward). Moreover, the Sim–Stim interface also monitors HUT and supplies information on its operating states to the VES via the sensors and ADC (feedback), thus allowing closed-loop, real-time interaction between the HUT and the VES as if the HUT were connected to a real system. The requirement to deliver power to HUT differentiates PHIL from the traditional HIL systems that deal only with low-level control signals (e.g. small voltages/currents) for digital logic purposes or servo-control. Ideally, the HUT should perform the same whether it is a part of a real system or connected to the PHIL system. In other words, from the HUT’s point of view, it should be unable to distinguish between being connected either to the VES via the Sim–Stim interface or to a real system. This means that the interface should not introduce any characteristics that might alter the operation of the HUT. For the PHIL system of Fig. 1 to perform electrically in the same manner as the original system (without the interface), the Sim–Stim interface must be seamless in terms of real-time performance of the power system for various operating conditions such
Fig. 1. Structure of the PHIL system showing the Sim–Stim interface, VES and HUT.
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as steady-state operation (i.e., load flow, power transfer, and power quality) and dynamic operation (i.e., stability, on and off switching, etc.). That is, the Sim–Stim interface must be lossless to maintain the same power quality, have unity gain, and infinite bandwidth and dynamic range, and not introduce additional dynamics. However, in the actual hardware implementation of the interface using a power converter, a certain level of power loss will occur. If not properly quantified, this loss can affect the designed PHIL experiment. For a seamless operation of the interface during the actual realization, any power loss encountered must be compensated for within the VES. In addition, the presence of the Sim–Stim interface in the PHIL system can introduce additional dynamics and time delays into the system both in the feedforward and feedback paths. Time delays and other interface parameters such as sampling rate, quantization and saturation may adversely affect the stability performance of the PHIL system [12]. Thus, in an actual implementation, to provide a matched performance of the HUT as compared to when it is connected to a real system, certain measures must be accounted within the VES to account for these additional effects. For example, to account for quantifiable delays in the Sim–Stim interface, optimal control schemes may be utilized that use receding horizon schemes for improved predictive control inputs [13]. But before this actual implementation it is necessary to understand this novel PHIL system in terms of its operational limits or its stability. Since an ideal Sim–Stim interface cannot be realized, there is a need to develop a mathematical model of the PHIL system (VES plus Sim–Stim interface) and a method of evaluating its stability. This study concentrates on the closed-loop stability of PHIL system of Fig. 1 and how the stability of such a hybrid system will be affected by the newly introduced Sim–Stim interface parameters. Similar to the networked control systems, time delays and sampling rate are the most significant interface parameters that could degenerate the stability performance of the system [14–17]. The Sim–Stim interface is the key component of the PHIL system that needs to be modeled for stability analysis. Therefore, this paper first gives an overview of modeling issues for such an interface and then discusses the parameters that must be included in the model depending on the phenomenon of interest. A realizable Sim–Stim interface model whose main parameters are sampling rate and time delay is developed for theoretical evaluation of stability using sampled-system theory [14]. The PHIL application of the proposed Sim–Stim interface is illustrated for a low power DC system. An RL load is chosen as being the HUT that is connected to a virtual model of DC source through the Sim–Stim interface. In order to evaluate the stability performance, a two-step approach is adopted. In the first step, a discrete-time model of the PHIL system is determined to investigate the stability analytically by means of stability regions in terms of sampling rate and time delay. The characterization of the stability using regions in the Sim–Stim interface parameter space (that is, sampling rate vs. time delay) is useful since it offers a set of acceptable interface parameters for which the PHIL system is stable. In the second step, a prototype of the Sim–Stim interface is designed and realized to validate theoretical stability results. Differences between theoretical and experimental stability results are also discussed in details. 2. Sim–Stim interface model 2.1. Modeling issues The key component of the PHIL system shown in Fig. 1 is the Sim–Stim interface that needs to be modeled for stability analysis. Fig. 2 illustrates the Sim–Stim interface partitioned as two major subsystems, the feed-
Fig. 2. Block diagram of the Sim–Stim interface in terms of the feed-forward (TF) and feedback (TB) maps.
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Fig. 3. A conceptual hardware realization of the Sim–Stim interface.
forward subsystem (D/A map), TF and the feedback subsystem (A/D map), TB. These subsystems provide bidirectional signal paths between the VES and the HUT. As shown in Fig. 1, the feedback A/D map consists of the power (voltage and current) sensors and an ADC. The feedforward D/A map is composed of a DAC and a power source/sink. The A/D map in the feedback part converts the continuous signal coming from the HUT to a quantized discrete signal while the D/A map converts the digital data coming from the VES into electric power quantities. Note that this representation is for a DC system or a single phase of a multi-phase system. The specific mapping TF and TB of the interface are determined by the type of components that define the boundary between HUT and VES subsystems, the type of HUT and VES architecture, and the phenomenon of interest. Mathematically the D/A and A/D maps can be represented as: Feedforward D/A map: v1 ðtÞ ¼ T F fz2 ½k; wF g ð1Þ Feedback A/D map: v2 ½k ¼ T B fz1 ðtÞ; wB g ð2Þ where v1(t) denotes continuous time power signals such as ac and/or dc voltage, current, power, etc. used to drive the HUT; z1(t) denotes analog sensor output signals measured at the HUT; v2[k] denotes digital signals (corresponding to sensor measurements, z1(t)) into the VES; z2[k] denotes digital data out of the VES which is converted by TF into power signals, v1(t), that drive the HUT; wF and wB are vectors denoting the key parameters of feedforward and feedback mappings that affect the performance of the PHIL system. wF and wB are best understood by looking at a conceptual hardware realization of the Sim–Stim interface shown in Fig. 3. Since the feedforward mapping consists of a DAC and power converter, the key parameters will include the DAC parameters such as sampling period hF, the conversion delays sF, and quantization qF, associated with the DAC; and the power converter parameters such as bandwidth, BWF dynamic range, DRF, switching frequency, fs, and output impedance, Z0, so wF ¼ ½ sF hF qF BWF DRF fs Z 0 T . Since the feedback mapping consists of the current/voltage sensors and an ADC, the key parameters are the sensors’ and ADC bandwidth, BWB, dynamic range, DRB, ADC sampling period, hB, quantization, qB, and the comT munication and conversion time delay, sB, so that the parameter vector wB ¼ ½ sB hB qB BWB DRB . To decide which of these parameters must be imbedded in the model, it is necessary to know the types of applications in which the PHIL system will be used (i.e., the type of power system that is studied such as AC, DC, or AC/DC and the HUT architecture) and phenomena of interest such as steady-state and/or dynamic stability, real power transfer and power quality. Depending on the PHIL application, certain assumptions on the dynamics of ADC, DAC and converter need to be made to develop an interface model containing appropriate parameters. In the following section, a mathematical model of the Sim–Stim interface for stability analysis is given. 2.2. (h, s) Sim–Stim interface The PHIL system shown in Fig. 1 is a closed-loop hybrid dynamical system similar to the networked control systems in which the network induced delays and sampling rate are the two significant parameters
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Fig. 4. PHIL system with the (h, s) Sim–Stim interface model.
that could degenerate the stability performance. The most critical Sim–Stim interface parameters for the stability performance evaluation of PHIL system are the sampling period (h) and time delays (sB and sF) observed in the feedback and feedforward parts of the interface. [12,15,16]. The time delays arise from the computational time in the VES and the processing time of ADC and DAC. In order to develop a practical interface model that allows the theoretical evaluation of stability, assumptions on the dynamics of ADC, DAC and power converter need to be made. For this purpose, in the feedback part of the interface it is assumed that the ADC is an ideal sampler with a sampling period, h (i.e., quantization and approximation errors are ignored). In the feedforward part, a Zero-Order-Hold (ZOH) circuit is selected for the DAC since it is commonly used in practice to convert digital signals to a series of rectangular pulses [14]. Finally, an ideal converter (i.e., dynamics are ignored and it has an infinite gain) is assumed for the power source to provide power to the HUT. The block diagram of the Sim–Stim interface model developed based on these assumptions is illustrated in Fig. 4. The ideal converter is represented by a voltage source. Note that a time delay (s) is introduced before the ZOH block. This delay represents the sum of the communication delays (sB and sF) from ADC to the VES in the feedback part and from the VES to the converter in the feedforward part as well as the processing delay observed in the VES. Since the Sim–Stim interface parameters are solely the time delay (s) and sampling period (h), this Sim–Stim interface model is called (h, s) Sim–Stim interface. The operation of PHIL system of Fig. 4 can be summarized as follows: First, the HUT quantities such as voltages and currents are sensed. These continuous signals z1(t) are then converted to digital signals, v2[k] = z1(t = tk) by the ideal sampler for input into the VES. The VES computed output signal, z2(tk) is delayed by (s) amount of time as to take into account the total delay in the loop and is fed into the ZOH block. Finally, the ZOH converts the digital signal to an analog one, which provides power to the HUT through a voltage source. The output of the ZOH, v1(t+) is a piecewise continuous voltage that only changes value at kh + s, and is defined as v1 ðtþ Þ ¼ z2 ½kh s pðtÞ;
t 2 fkh þ s; k ¼ 0; 1; 2; . . .g
ð3Þ
The ideal sampler defines the A/D map and its output is given as v2 ½k ¼ z1 ðt ¼ tk Þ;
tk ¼ kh; k ¼ 0; 1; 2; . . .
ð4Þ
where p(t) = [u(t) u(t s)] is a unit pulse of width h. This interface model has two essential features: (i) it is a very practical interface model that could easily be realized using readily available low-cost data acquisition (DAQ) cards, (ii) it is an analytically tractable model that enables to determine the discrete-time state-space model of the PHIL system for stability analysis. 3. Application of (h, s) Sim–Stim interface In this section, a low power DC PHIL system is used to illustrate the application of the (h, s) Sim–Stim interface and to analyze the stability in terms of the delay. Fig. 5 shows the block diagram of the PHIL system
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Fig. 5. Linear circuit application of the (h, s)-Sim–Stim interface.
under study. An RL impedance is chosen as being the HUT which is connected to a virtual model of a DC source with an internal resistance through the (h, s) Sim–Stim interface. The Sim–Stim interface parameters are the sampling period (h) and lumped time delay (s), which will affect the stability performance of the closed-loop hybrid dynamical system. In order to evaluate the stability performance of the PHIL system in Fig. 5, a two-step approach is adopted. In the first step, a discrete-time (DT) model of the system is determined to investigate the stability theoretically by obtaining region of stable operation in terms of Sim–Stim interface parameters w ¼ ½ h s T while the RL impedance parameters are fixed. In the second step, a prototype low power Sim–Stim interface is designed and realized to validate theoretical stability results. In the following section, theoretical evaluation of the stability is presented. 3.1. Theoretical analysis The PHIL system shown in Fig. 5 consists of a continuous subsystem (i.e., RL impedance as being HUT) and discrete subsystem (VES) acting upon the continuous HUT through the Sim–Stim interface. The dynamic of the HUT is described by a first-order differential equation diðtÞ ¼ aiðtÞ þ bvðtþ Þ; dt
t 2 ½kh þ s; ðk þ 1Þh þ s
ð5Þ
where a = R/L, b = 1/L. The driving voltage v(t+) is the output of the ZOH consists of a series of rectangular pulses whose value changes only at kh + s for k = 0, 1, 2, . . . The value of v(t+) is given by vðtþ Þ ¼ R0 iðt sÞ þ EðtÞ;
t 2 fkh þ s; k ¼ 0; 1; 2; . . .g
ð6Þ
Note that Eqs. (5) and (6) give the continuous-time (CT) model of the PHIL system. Although this model inT cludes the two Sim–Stim parameters, w ¼ ½ h s , they are included implicitly, and thus making it difficult to quantify how they affect the system stability. This can be overcome by obtaining a DT model of the PHIL system that will be done next. The DT model of the VES is given by V ½k ¼ R0 i½k þ E½k
ð7Þ
The value of i[k] is the sampled value of the current flowing in the HUT circuit. This current is due to the piecewise continuous voltage, v(t+), applied during the period (k 1)h 6 t < kh. This means that at most two voltage samples, v[k 1] and v[k] need to be considered when evaluating i[k] from the solution of the HUT model of Eq. (5). The sampled solution of Eq. (5) gives i[k] which is then combined with Eq. (7) to give the following DT state-space representation of the PHIL system for the case when the delay is less than or equal to sampling period {s 6 h} [14]:
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i½k þ 1
v½k
¼
U C0 R0
C1
i½k
v½k 1 R 0 |fflfflfflfflfflfflfflfflfflfflfflfflfflffl0{zfflfflfflfflfflfflfflfflfflfflfflfflfflffl}
þ
½Aaug
C0
1 |fflffl{zfflffl}
E½k
ð8Þ
½Baug
where U ¼ eah ;
C0 ¼ "
½Aaug ¼ " ½Baug ¼
Z
hs
eas ds b;
0 ah
e
b aðhsÞ ½e a
R0 b ðeaðhsÞ a
1Þ
1R0
eas ds b hs # b ah as e ½1 e a C1 ¼
Z
h
0
#
ð9Þ
1
When the delays are longer than one sampling period, (i.e., 0 < s < ‘h, ‘ > 1). The system matrix [Aaug] of Eq. (8) needs to be modified. In the special case where (‘ 1)h < s < ‘h for all k, one current sample is received every sample period for k > ‘. In this case, it follows from [14] that 2 3 U C1 ðs0 Þ C0 ðs0 Þ 0 6 0 0 I 07 6 7 ð10Þ ½Aaug ¼ 6 .. 7 .. .. .. 6 .. 7 4 . . .5 . . R0
0
0
0
where s 0 = s (‘ 1)h. The stability of the PHIL system is guaranteed if all the eigenvalues of the system matrix [Aaug] lie inside the unit circle: fjki ðAaug Þj ¼ jki ðwÞj < 1;
for i ¼ 1; 2; . . .g
ð11Þ
Note from Eq. (9) or (10), that the eigenvalues of the PHIL system, thus stability, are function of not only the T T system parameters / ¼ ½ R R0 L , but also Sim–Stim interface parameters w ¼ ½ h s . Moreover, even though the original system (i.e., RL impedance connected to the DC source without the Sim–Stim interface) is only first-order continuous system, the order of the DT model of the PHIL system has increased at least by one degree due to the introduction of the Sim–Stim interface. The effects of sampling period (h) and time delay (s) on stability performance of the PHIL system can be analyzed using the region of stable operation, SPHIL(wj/ = /0) in the Sim–Stim interface parameter space (i.e., h vs. s/h). The definition of the stability region is as follows: S PHIL ðwj/ ¼ /0 Þ ¼ fw : jki ðAaug ð/ ¼ /0 ; wÞÞj 6 1
8i; i ¼ 1; 2; . . .g
ð12Þ
where Aaug(/ = /0, w) is obtained from either Eq. (9) or (10) depending on the delay size and /0 defines a particular choice of system parameters. Fig. 6 shows the region of stable operation for R = 9.75 X, L = 0.08 H, R0 = 19.5 X and 0 < s < 12h. This region is plotted by incrementally increasing the delay and testing the system matrix of (9) or (10). If the system matrix is stable, a point is marked in that location of the stability region. The lower shaded area represents a set of h and s for which the system is stable. Such a region is helpful to determine how much delay the system can tolerate before it becomes unstable indicating the trade-off between the sampling period and delay. 3.2. Experimental validation A prototype of the Sim–Stim interface was designed and experimentally realized to validate the theoretical stability results presented in the previous section. Fig. 7 shows the experimental setup of the PHIL system of Fig. 5 indicating main hardware components of the Sim–Stim interface. As can be seen in Fig. 7, the experimental setup is composed of the followings: Virtual power system, DAQ card, power source, related control
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Fig. 6. Region of stable operation for R = 9.75 X, L = 0.08 H, R0 = 19.5 X and 0 < s < 12h.
Fig. 7. Block diagram of the experimental setup illustrating main hardware components of Sim–Stim interface.
and sense signals such as voltage control, voltage sense and current sense, and hardware-under-test consisting of two switched RL impedances. The value of each load is R = 19.5 X and L = 0.16 H. The Virtual Power System located in a Pentium III laptop PC. It is the virtual model of a DC source (Es) with an internal resistance (R0) and it was implemented in LabVIEW environment. LabVIEW is an object-oriented software programming tool that combines the advantages of graphical programming and high quality user interface tools [18,19]. The user interface ‘‘front panel’’ of LabVIEW has ready-to-go controls, such as graphs, knobs, and switches that can be manipulated by the programmer. The front panel can be constructed and viewed like a physical instrument, where the user can visualize the results on the computer screen. Fig. 8 shows the front panel of the experimental setup. It provides interactive control of the following system parameters: sampling period (h), time delay (s), the source voltage (Es), and source resistance (R0), and displays voltage across the RL load impedance. The LabVIEW program determines sampling period and time delay based on the ‘‘Scan Rate’’ (SR) control and ‘‘# of Sample to Delay ’’ control specified by the user. The sampling period is h = 1/SR and ‘‘ # of Sample to Delay ’’ represents the ratio of s/h. The front panel is driven by the G-language code or ‘‘block diagram’’, which is the actual code of the program. This program (i) prepares
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Fig. 8. The front panel of the PHIL experiment.
the DAQ system to accept data, (ii) allows interactive control of system parameters (s, h, Es, R0) through the front panel, and (iii) implements Sim–Stim interface equations. The hardware interface to the computer is a National Instruments NI DAQ-6024E, multifunction, low-cost DAQ card inserted into PCMCIA slot of the laptop. This DAQ and control card configured by LabVIEW has 16 analog inputs in a single-ended mode, two analog outputs and eight digital input/output lines. The maximum sampling rate for analog input is 200 kHz, and it has an accuracy of 12 bits [20]. The DAQ card is shown in the left side of the Sim–Stim interface box of Fig. 7. The Power Source of Sim–Stim interface box in Fig. 7 provides power to the RL impedance. It consists of an op-amp buffer in the non-inverting mode and a transistor operating as an emitter follower. The power source is controlled by the delayed Voltage Control signal that is the analog output of the DAQ card. The power may be obtained from an internal +5 V supply or an external supply if higher voltage/power is needed. The operation of the experimental setup can be summarized as follows: First, the RL impedance current is sensed and this analog signal is then converted to a digital signal using the DAQ card. The LabVIEW program computes a digital voltage control signal using Eq. (7). This control signal is delayed by the amount of time delay specified. The delayed control signal is converted to an analog one using the DAQ card and sent to the Power Source. The waveform of the voltage across the RL impedance can be displayed either in the front panel of the experiment (Fig. 8) or using an oscilloscope connected to output of the Sim–Stim interface (Fig. 7). The user can easily change the system parameters (s, h, Es, R0) in real-time in order to study interactively how they affect the output voltage and how much time delay the system can tolerate before loosing stability. In the following section, experimental stability results are compared with theoretical ones and reasons for differences are discussed. 4. Comparison of stability results The experimental validation studies for verifying the effects that the time delay (s) and sampling period (h) have on the stability performance were performed using the experimental setup shown in Fig. 7. In order to verify theoretical stability results shown in Fig. 6, two points (stable and unstable) were selected in the region. As can be seen from the left figure of Fig. 9, the stable point is the lower one with h = 1 ms and s/h = 2 while the unstable one is the upper point with h = 1 ms, s/h = 9. For each one, experiment was performed and voltage across the RL impedance was measured. The voltage waveforms are shown in the right figure of Fig. 9. For the stable point, the voltage reaches its steady-state value while for the unstable case a growing oscillation was observed. These measured results verify both stable and unstable operation of PHIL system predicted by theory. It is also essential to investigate whether there exists an experimental stability boundary between stable and unstable regions of operation similar to the theoretical stability boundary shown in Fig. 6. For this reason several experiments were performed using (h, s) data around the theoretical boundary. The experiment results
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Fig. 9. The stable and unstable operations of PHIL system validated by the experiment.
Fig. 10. Regions of stable, unstable and neutrally stable operation of the PHIL system.
indicate that there is a neutrally stable region of operation that occurs with the hardware realization of the Sim–Stim interface, rather than a sharp boundary between stable and unstable regions. Fig. 10 shows these three regions of operation for different sampling periods and delays and the corresponding voltage waveforms. The neutrally stable region is the region between two dashed lines. The upper dashed line is the boundary between unstable and neutrally stable regions while the lower one corresponds to the boundary between the stable and neutrally stable regions. As can be seen from the left figure of Fig. 10 the stable region of the experimental setup was larger than the one predicted by theory. It is felt that the larger stability region and the neutrally stable region occur due to hardware limitations such as limited bandwidth and gain dv/dt limits, drifts, finite dynamic range and circuit losses, which were not taken into account in theoretical stability analysis. 5. Discussions The proposed (h, s) Sim–Stim interface and the experimental setup shown in Fig. 7 could not be used to test and design power hardware components in a PHIL configuration because of its low power level. In order to
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Table 1 Potential application of power hardware in the loop(PHIL) Power application/level
Hardware-under-test (HUT)
Storage, conversion, distribution hardware Small: 1–10 kW Medium: 5–100 kW Large: >100 kW
Small–medium: batteries/fuel cells/controllers/converters/back-up generators/uninterruptible power supplies/flywheels Large: generators/prime movers/transformers/power supplies/etc.
take the advantage of virtual prototyping in the design and testing of power hardware, the Sim–Stim interface must be capable of power exchange at the level of kW. Table 1 indicates potential applications of the PHIL system and the power levels that it must deliver. The actual KVA or KW rating of the power hardware-undertest will depend on the power capability of the power converter of the Sim–Stim interface. However, there are some limitations in designing and implementation of such a power interface. The main challenge in the implementation of the interface at high power level is to have a wide dynamic range with low latency. The investigation of power system issues such as stability, power transfer, response to harmonics, requires that the interface have very high bandwidth [21]. With respect to sensing, using a fast ADC with low latency such a high bandwidth could be easily obtained. Moreover, the computing delay could be significantly reduced using high performance computers in the VES. The major limitation comes from the design of an appropriate power converter that will be used as a power source/sink in the interface (as shown in Fig. 3). This limitation is related to the switching frequency of the power components and to the controller of the converter. Fast switching (1 MHz) is feasible using power MOSFET switching devices. In order to meet the high switching demands of such a power interface (>1 MHz), some recent studies have reported the development of gallium nitride (GaN) switching devices to be used in power converters for PHIL applications [22,23]. For the controller part of the converter, a discrete-time sliding mode control algorithm implemented in a FPGA has been proposed as an option for controlling a high-bandwidth power converter [24]. Incorporating all the capabilities of interest such as an adjustable frequency range, the ability to produce an arbitrary waveform and four quadrant operation, makes the associated power converter design a separate research effort. The incorporation of power electronic converters in the interface is a future capability, and as these devices become more readily available, their incorporation into PHIL configurations will follow the foundation being developed. For the case of non-linear load and complex VES models, analytical approach presented in Section 3.1 and (h, s) Sim–Stim interface model shown in Fig. 4 can not be used to investigate the closed-loop stability of the PHIL system with respect to sampling period and time delay. Simulation approach that implements PHIL simulation structure of Fig. 1 (with a power converter as a power source/sink) using an appropriate software tool should be adopted. Such a simulation model must replicate the characteristics of the real hybrid system through multi-rate integration. The HUT such as an induction motor, which exists in continuous-time, should be approximated by simulation model that is integrated with very small time step. The simulation model of VES, which is already a discrete-time model, should be integrated with longer time step than we plan to apply in the actual implementation. One possible simulation environment for PHIL applications is Virtual Test Bed (VTB) [25] designed for simulation and virtual prototyping of complex dynamic systems. In VTB environment, different solvers can interact using different time steps. VTB is a freely available software package developed at University of South Carolina (http://vtb.ee.sc.edu/).With its graphical user interface and extensive library of components including power electronic converters, electrical machinery, various types of electrical sources, measurement devices, electrical and mechanics loads, etc., VTB provides engineers and researchers with a modern and interactive design tool to build simulation models of dynamic systems rapidly and easily. 6. Conclusions In this paper, a Simulation–Stimulation interface for testing hardware for various operating conditions has been introduced and a hybrid model of the interface that includes two key parameters, time delay and sampling period has been developed for stability evaluation. The proposed interface has been applied to a linear
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circuit to illustrate its application and stability problems. Using the sampled-system theory, a discrete-time model of the linear PHIL system has been determined and trade-off between time delay and sampling period has been obtained by the region of stable operation. An experimental setup has been designed and realized for validation the theoretical stability results. A larger stability region compared to theoretical one and a neutrally stable region have been observed in the experimental studies. Results indicate the time delay is the major concern for the stability of the PHIL system. Further work will be performed to develop a Sim–Stim interface model that includes a power converter for PHIL applications. Using the steady-state and dynamic models of power interface to be developed, it will be feasible to evaluate the performance of power hardware components for various power operating phenomena such as load flow, real power transfer, power quality and stability. Acknowledgement This work was supported by the US Office of Naval Research (ONR) under Grant N00014-01-C-0045. References [1] D. Maclay, Simulation gets into loop, IEE Rev. 5 (1997) 109–112. [2] P. Terwiesch, T. Keller, E. Scheiben, Rail vehicle control system integration testing using digital hardware in-the-loop simulation, IEEE Trans. Contr. Syst. Technol. 7 (1999) 352–362. [3] C.O. Sung, Evaluation of motor characteristics for hybrid electric vehicles using hardware-in-the-loop concept, IEEE Trans. Vehicular Technol. 54 (2005) 817–824. [4] A.J. Grono, Synchronizing generators with HITL simulation, IEEE Comput. Appl. Power 14 (2001) 43–46. [5] V.R. Dinavahi, M.R. Iravani, R. Bonert, Real-time digital simulation of power electronic apparatus interfaced with digital controllers, IEEE Trans. Power Delivery 16 (2001) 775–781. [6] A. Monti, E. Santi, R. Dougal, M. Riva, Rapid prototyping of digital controls for power electronics, IEEE Trans. Power Electron. 18 (2003) 915–923. [7] Y. Liu, M. Steurer, P. Riberiro, A novel approach to power quality assessment: real time hardware-in-the-loop test bed, IEEE Trans. Power Delivery 20 (2005) 1200–1201. [8] P.S. Shiakolas, D. Piyabongkarn, Development of a real-time digital control system with a hardware-in-the-loop magnetic levitation device for reinforcement of controls education, IEEE Trans. Educ. 46 (2003) 79–87. [9] S. Ayasun, S. Vallieu, R. Fischl, T. Chmielewski, Electric machinery diagnostic/testing system and power hardware-in-the-loop studies, in: Proceedings of the IEEE International Symposium on Diagnostics for Electric Machinery, Power Electronics and Drives (SDEMPED 2003), Atlanta, GA, 24–26 August 2003, pp. 361–366. [10] X. Wu, S. Lentijo, A. Monti, A novel interface for power-hardware-in-the-loop simulation, in: Proceedings of the IEEE Workshops on Computers and Power Electronics (COMPEL 2004), University of Illinois, Urbana, IL, 15–18 August 2004, pp. 178–182. [11] W. Zhu, S. Pekarek, J. Jatskevich, O. Wasynczuk, D. Delisle, A model-in-the-loop interface to emulate source dynamics in a Zonal DC distribution system, IEEE Trans. Power Electron. 20 (2005) 438–445. [12] S. Ayasun, A. Monti, R. Dougal, R. Fischl, S. Vallieu, On the stability of hardware in the loop simulation, in: Proceedings of the 7th International Conference on Modeling and Simulation of Electric Machines, Converters and Systems (ELECTRIMACS 2002), Montreal (Quebec), Canada, 18–21 August 2002, pp. 185–191. [13] Y.I. Lee, W.H. Kwon, Y.H. Kim, Weighted receding horizon predictive control and its related GPC with guaranteed stability, in: Proceedings of the 32nd IEEE Conference on Decision and Control, San Antonio, Texas, 15–17 December 1993, pp.1316–1321. [14] K.J. Astrom, B. Wittenmark, Computer-Controlled Systems: Theory and Design, third ed., Prentice-Hall, Englewood Cliffs, NJ, 1997. [15] W. Zhang, M.S. Branicky, M. Phillips, Stability of networked-control systems, IEEE Contr. Syst. Mag. 21 (2001) 84–99. [16] G.C. Walsh, H. Ye, L.G. Bushnell, Stability analysis of networked control systems, IEEE Trans. Contr. Syst. Technol. 10 (2002) 438– 446. [17] D. Yue, Q.L. Han, C. Peng, State feedback controller design of networked control systems, IEEE Trans. Circ. Syst.-II 51 (2004) 640– 644. [18] LabVIEW User Manual, National Instruments Corporation, 2002. [19] LabVIEW Measurements Manual, National Instruments Corporation, 2002. [20] DAQ 6024E User Manual, National Instruments Corporation, 2002. [21] A.Monti, H. Figueroa, X. Wu, R. Dougal, Interface issues in hardware-in-the-loop simulation, in: Proceedings of the IEEE Electric Ship Technical Symposium, Philadelphia, PA, July 2005, pp. 39–45. [22] S. Pytel, S. Lentijo, A. Koudymov, S. Rai, V. Adivarahan, J. Yang, J. Hudgins, E. Santi, A. Monti, AlGaN/GaN MOSHFET integrated circuit power converter, in: Proceedings of the IEEE Power Electronic Specialists Conference, Aachen, Germany, 20–25 June 2004, pp. 579–584.
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