MPC8544E PowerQUICC⢠III Bring-up Guide - NXP
Freescale Semiconductor Application Note
Document Number: AN3547 Rev. 2, 02/2009
MPC8544E PowerQUICC™ III Bring-up Guide
This document provides recommendations for new designs based on the MPC8544E PowerQUICC III family of integrated host communications processors (collectively referred to throughout this document as MPC8544E): • MPC8544E • MPC8544 This document may also be useful in debugging newly designed systems by highlighting those aspects of a design that merit special attention during initial system startup. For updates to this document, refer to the website listed on the back cover of this document.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21.
Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Power-on Reset and Reset Configurations . . . . . . . . . 9 Device Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 DDR Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Debug and Test Interface . . . . . . . . . . . . . . . . . . . . . 55 DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 DUART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Ethernet Management Interface . . . . . . . . . . . . . . . . 57 eTSEC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Local Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PIC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Spare Configuration Pins . . . . . . . . . . . . . . . . . . . . . 67 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . 67 Documentation History . . . . . . . . . . . . . . . . . . . . . . . 68
Introduction
1
Introduction
This section outlines recommendations to simplify the first phase of design. Before designing a system with a MPC8544E device, it is recommended that the designer be familiar with the available documentation, software, models, and tools.
1.1
MPC8544E Overview
This section provides a high-level overview of MPC8544E features. Figure 1 shows the major functional units within the device.
MPC8544E
e500 Core 32-Kbyte I-Cache
XOR Acceleration
Local Bus
Security Acceleration
Performance Monitor DUART 2x I2C
OpenPIC
Gigabit Ethernet SGMII
256-Kbyte L2 Cache
32-Kbyte D-Cache
e500 Coherency Module
64-Bit DDR/DDR2 SDRAM Controller
32-Bit PCI
PCI Express x4/x2/x1
PCI Express x1
PCI Express x4/x2/x1
DMA
Figure 1. MPC8544E Block Diagram
1.2 •
References Collateral — MPC8544E PowerQUICC III™ Integrated Host Processor Family Reference Manual (MPC8544ERM) — Errata to MPC8544E PowerQUICC™ III Integrated Host Processor Family Reference Manual (MPC8544ERMAD) — Device Errata for the MPC8544E PowerQUICC™ III (MPC8544ECE) — MPC8544E PowerQUICC III™ Integrated Processor Hardware Specifications (MPC8544EEC)
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Introduction
•
•
1.3
— A Strategy for Routing the MPC8544E in a Six-Layer PCB (AN3535) — PowerQUICC™ DDR2 SDRAM Controller Register Setting Considerations (AN3369) — Programming the PowerQUICC™ III/PowerQUICC II Pro DDR SDRAM Controller (AN2583) — Hardware and Layout Design Considerations for DDR Memory Interfaces (AN2582) — Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces (AN2910) Tools — Software – Boot sequencer generator tool (I2CBOOTSEQ) – UPM Programming tool (LBCUPMIBCG) — Hardware – Development System (MPC8544DS) including schematics, bill of materials, board errata list, User’s Guide, and configuration guide Models — IBIS — BSDL — Flowtherm
Device Errata
The device errata document MPC8544ECE describes the latest fixes and work arounds for the MPC8544E. The errata document should be thoroughly researched prior to starting a design with the respective MPC8544E device.
1.4
Boot Sequencer Tool
The MPC8544E features the boot sequencer to allow configuration of any memory-mapped register before the completion of power-on reset (POR). The register data to be changed is stored in an I2C EEPROM. The MPC8544E requires a particular data format for register changes as outlined in the MPC8544ERM. The boot sequencer tool (I2CBOOTSEQ) is a C-code file. When compiled and given a sample data file, it will generate the appropriate raw data format as outlined in the MPC8544ERM. The file that is generated is an s-record file that can be used to program the EEPROM.
1.5
UPM Programming Tool
The UPM Programming Tool (LBCUPMIBCG) features a GUI for a user-friendly programming interface. It allows programming of all three of the MPC8544E’s UPM machines. The GUI consists of a wave editor, a table editor, and a report generator. The user can edit the waveform directly or the RAM array directly.
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
3
Power
At the end of programming, the report generator will print out the UPM RAM array that can be used in a C-program.
1.6
Available Training
Our third-party partners are part of an extensive Design Alliance Program. The current training partners can be found on our website under Design Alliance Program at www.freescale.com/alliances. Training material from past Smart Network Developer’s Forums and Freescale Technology Forums are also available. These trainings modules are a valuable resource in understanding the MPC8544E. This material is also available at our website listed on the back cover of this document.
1.7
Product Revisions
Table 1 lists the Processor Version Register (PVR) and System Version Register (SVR) values for the various MPC8544E derivatives of silicon. Table 1. MPC8544E PowerQUICC III Product Revisions Device Number
Device Revision
e500 v2 Core Revision
Processor Version Register Value
System Version Register Value
Note
MPC8544E
1.0
2.1
0x8021_0021
0x803C_0110
With Security
MPC8544
1.0
2.1
0x8021_0021
0x8034_0110
Without Security
MPC8544E
1.1/1.1.1
2.2
0x8021_0022
0x803C_0111
With Security
MPC8544
1.1
2.2
0x8021_0022
0x8034_0111
Without Security
2
Power
This section provides design considerations for the power supplies and power sequencing. For information on AC and DC electrical specifications and thermal characteristics, refer to the MPC8544EEC Hardware Specification document.
2.1
Power Supplies
The MPC8544E has a core voltage VDD and SerDes voltages SVDD and XVDD that operate at a lower voltage than the I/O voltages BVDD, GVDD, LVDD, OVDD, and TVDD. The core voltage, 1.0 V (±5%), is supplied across VDD and GND. The I/O blocks are supplied with the following: • 1.8 V (±5%) or 2.5 V (±5%) or 3.3 V (±5%) across BVDD and GND • 1.8 V (±5%) or 2.5 V (±5%) across GVDD and GND • 2.5 V (±5%) or 3.3 V (±5%) across LVDD and GND • 3.3 V (±5%) across OVDD and GND • 1.0 V (±5%) across SVDD and GND MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 4
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Power
• •
2.5 V (±5%) or 3.3 V (±5%) across TVDD and GND 1.0 V (±5%) across XVDD and GND
Both LVDD and TVDD are used to supply the eTSEC interfaces on the device: LVDD manages eTSEC1, and TVDD manages eTSEC3. For the respective eTSEC, LVDD/TVDD • 3.3 V or 2.5 V for GMII, MII, RMII, TBI, or FIFO modes of operation • 2.5 V for RGMII or RTBI modes of operation NOTE eTSEC1 and/or eTSEC3 can be configured to operate in SGMII mode. Details are provided in the MPC8544E PowerQUICC III™ Integrated Host Processor Family Reference Manual (MPC8544ERM).
2.2
Power Consumption
Operating-mode power dissipation numbers (Typical) are provided in the MPC8544EEC Hardware Specification. Typical and Thermal numbers are provided to assist in the thermal design for the device. If the targeted junction temperature (TJ) of the MPC8544E in the system is not one of these two temperatures, a linear extrapolation of these two TYPICAL dissipation values can be used to estimate the power dissipation at the targeted junction temperature. The Maximum is intended to assist in the power supply design selection.
2.2.1
Low Power Modes Power Dissipation
A low-power mode estimates provided in Table 2 for applications concerned about minimizing power consumption when the core is not active. Table 2. Power Dissipation Estimated For Low Power Modes Core/CCB Frequency Low Power Modes
667/333 MHz
800/400 MHz
1000/400 MHz
1067/533 MHz
SLEEP
1.50 W
1.55 W
1.55 W
1.6 W
NAP
1.75 W
1.80 W
1.90 W
2.0 W
DOZE
2.20 W
2.35 W
2.6 W
2.7 W
NOTE The Typical, Thermal, and Maximum power numbers are based on the power dissipation on the 1.0 V nominal VDD supply only. Typical power dissipation estimates on the peripheral supplies (BVDD, GVDD, LVDD, OVDD, TVDD, and XVDD) are provided in MPC8544EEC.
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Power
2.2.2
I/O Power Dissipation
Because I/O usage varies from design to design, power dissipation estimates for the I/O supplies are provided in Table 3. Table 3. Estimated I/O Power Dissipation Interface
Parameters
1.0 V (XVDD)
1.8 V (GVDD)
2.5 V (B/G/LV DD)
3.3 V (B/L/OV DD)
Comments
DDR
333 MHz data
—
0.38 W
0.73 W
—
—
400 MHz data
—
0.46 W
—
—
533 MHz data
—
0.60 W
—
—
PCI Express
x4, 2.5 G-baud
0.36 W
—
—
—
—
PCI
32-bit, 66 MHz
—
—
—
0.07 W
32-bit, 33 MHz
—
—
—
0.04 W
Power per PCI port
32-bit, 133 MHz
—
—
0.14 W
0.24 W
32-bit, 66 MHz
—
—
0.07 W
0.13 W
32-bit, 33 MHz
—
—
0.04 W
0.07 W
MII
—
—
—
0.01 W
GMII
—
—
—
0.07 W
TBI
—
—
—
0.07 W
RGMII
—
—
0.04 W
—
RTBI
—
—
0.04 W
—
8-bit, 200 MHz
—
—
0.11 W
—
8-bit, 155 MHz
—
—
0.08 W
—
Local bus
eTSEC (10/100/1000 Ethernet)
eTSEC (packet FIFO)
2.3
—
Power per eTSEC used
Power per FIFO interface used
Power Sequencing
The device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. Per MPC8544EEC, the requirements for power-up are as follows: 1. VDD, AVDD_n, BVDD, LVDD, OVDD, SVDD, TVDD, XVDD 2. GVDD All supplies must be at their stable values within 50 ms. Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. The purpose of the sequence is to guarantee the state of the DDR signals at reset. In order to guarantee MCKE low during power-up (as should be attempted per the JEDEC JESD79-2C specification), the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power-up, then the sequencing of GVDD is not required. MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 6
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Power
From a system standpoint, if any of the I/O power supplies ramp prior to the VDD core supply, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device.
2.4
PLL Power Supply Filtering
Each of the PLLs is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CORE, AVDD_PCI, AVDD_LBIU, and AVDD_SRDS respectively). Preferably these voltages will be derived directly from VDD through a low-frequency filter scheme. Although there are a number of ways to reliably provide power to the PLLs, the recommended solution is to provide independent filter circuits per PLL power supply as illustrated in Figure 2, one to each of the AVDD pins. By providing independent filters to each PLL, the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs’ resonant frequency range from a 500 kHz to 10 MHz range. If the PCI is run in synchronous mode, no filter is required for AVDD_PCI. 10 Ω V DD
AVDD 2.2 µF
2.2 µF
GND
Low ESL Surface Mount Capacitors
Figure 2. PLL Power Supply Filter Circuit
The AVDD_SRDSn signals provide power for the analog portions of the SerDes PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in Figure 3. For maximum effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn balls to ensure it filters out as much noise as possible. The ground connection should be near the AVDD_SRDSn balls. The 0.003-µF capacitor is closest to the balls, followed by the 1-µF capacitor, and finally the 1-Ω resistor to the board supply plane. The capacitors are connected from AVDD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. If the SerDes is not used, a filter for AVDD_SRDS is not required. SVDD
1.0 Ω
AVDD_SRDS 2.2 µF 1
2.2 µF 1
0.003 µF
GND 1. An 0805 sized capacitor is recommended for system initial bring-up. 2. AVDD_SRDS should be a filtered version of SVDD. 3. Signals on the SerDes interface are fed from the XVDD power plane.
Figure 3. SerDes PLL Power Supply Filter
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. These filters are a necessary extension of the PLL circuitry and are to what the device is specified. Any deviation from the recommended filters are done at the customer’s risk. MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
7
Power
2.5
Power Supply Decoupling
The MPC8544E requires a clean, tightly regulated source of power. The system designer should place at least one decoupling capacitor at each VDD and B/G/L/O/TVDD pin of the device. These decoupling capacitors should have a value of 0.01 or 0.1 µF and receive their power from separate VDD, B/G/L/O/TVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. In addition, several bulk storage capacitors should be distributed around the PCB to feed the VDD and B/G/L/O/TVDD planes in order to enable quick recharging of the smaller chip capacitors. The capacitors should be placed as close as possible to the processor. The capacitors need to be selected to work well with the power-supply so as to be able to handle the MPC8544E’s dynamic load requirements. The customer should work closely with their power-supply vendor to choose the correct value and type of capacitors for good and clean power. If the SerDes is used, it requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low jitter on transmit and reliable recovery of data in the receiver: • • •
2.6
The board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls of the device. There should be a 1-µF ceramic chip capacitor from each SerDes supply (SVDD and XVDD) to the board ground plane on each side of the device. Between the device and any SerDes voltage regulator there should be a 10-µF, low ESR SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies.
Power Supplies Checklist
Table 4 provides a summary power supply checklist for the designer. Table 4. Power Supplies Checklist Item
Description
Completed
1
All power supplies have a voltage tolerance no greater than 5% from the nominal value.
2
eTSEC supplies are chosen according to the mode of operation used.
3
Power supply selected is based on MAXIMUM power dissipation.
4
Thermal design is based on TYPICAL power dissipation.
5
Power-up sequence is less than 50 ms.
6
Power sequencing is understood and based on whether or not latch-up or garbage data written to DDR is a concern.
7
Recommended PLL filter circuit is applied to AVDD_PLAT, AVDD_CORE, and AVDD_LBIU.
8
If PCI is used in asynchonous mode, then the recommended PLL filter circuit is applied to AVDD_PCI. However, If the PCI is used in synchronous mode, no filter is required for AVDD_PCI.
9
If SerDes is used, the recommended PLL filter circuit is applied to AVDD_SRDS. However, If SerDes is not used, a filter for AVDD_SRDS is not required.
10
PLL filter circuits are placed as close to the respective AVDD pin as possible.
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Power-on Reset and Reset Configurations
Table 4. Power Supplies Checklist Item
Description
Completed
11
Decoupling capacitors of 0.01 or 0.1 µF are placed at each VDD, B/G/L/O/TVDD pin.
12
Bulk capacitors are placed on each VDD, B/G/L/O/TVDD plane.
13
If SerDes is used, the recommended decoupling for S/XVDD is used.
3
Power-on Reset and Reset Configurations
This section discusses reset configurations.
3.1
Configuration and Timing
Various device functions are initialized by sampling certain signals during the assertion of HRESET. These power-on reset (POR) inputs are either pulled high or low during this period. While these pins are generally output pins during normal operation, they are treated as inputs while HRESET is asserted. HRESET must be asserted for a minimum on 100 μs. When HRESET de-asserts, the configuration pins are sampled and latched into registers, and the pins then take on their normal output circuit characteristics. Most of the configuration pins have an internally gated 20 kΩ pull-up resistor, enabled only during HRESET. For those configurations in which the default state is desired, no external pull-up is required. Otherwise, a 4.7 kΩ pull-down resistor is recommended to pull the configuration pin to a valid logic low level. In the case where a configuration pin has no default, 4.7 kΩ pull-up or pull-down resistors are recommended for appropriate configuration of the pin. An alternative to using pull-up and pull-down resistors to configure the POR pins is to use a PLD or similar device that drives the configuration signals to the MPC8544E when HRESET is asserted. The PLD must begin to drive these signals at least four SYSCLK cycles prior to the de-assertion of HRESET (PLL configuration inputs must meet a 100 μs set-up time to HRESET), hold their values for at least 2 SYSCLK cycles after the de-assertion of HRESET, and then release the pins to high impedance afterward for normal device operation.
3.2
Configuration Settings
The following table summarizes the customer configurable device settings. Refer to the MPC8544ERM for a more detailed description of each configuration option. Table 5. User Configuration Options Configuration Type
Functional Pins
Device
DMA_DACK[0:1]
CCB Clock PLL Ratio
LA[28:31]
e500 Core PLL Ratio
Comments Refer to Table 7 Checklist for POR and Reset Configurations There is no default value for this PLL ratio; these signals must be pulled to the desired value. Refer to Section 5.1, “System PLL Ratio.”
LBCTL, LALE, There is no default value for this PLL ratio; these signals must be pulled LGPL2/LOE/LSDRAS to the desired value. Refer to Section 5.2, “e500 Core PLL Ratio.”
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
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Power-on Reset and Reset Configurations
Table 5. User Configuration Options (continued) Configuration Type
Functional Pins
Comments
SEC Frequency Ratio
LWE[0]
Boot ROM Location
TSEC1_TXD[6:4]
Default: Local Bus GPCM (32-bit ROM)
Host/Agent
LWE[1:3]/LBS[1:3]
Default: MPC8544E acts as the host processor/root complex on all interfaces.
I/O Port Selection
TSEC3_TXD[6:4]
Default: All three PCI Express ports active and SGMII ports active.
CPU Boot
LA27
Boot Sequencer
LGPL3/LSDCAS, LGPL5
DDR SDRAM Type
LGPL[0:1]
eTSEC1 Serial
TSEC1_TXD[2]
Default: eTSEC1 Ethernet interface uses parallel interface according to POR config inputs of eTSEC1 width and eTSEC1 protocol.
eTSEC3 Serial
TSEC3_TXD[2]
Default: eTSEC3 Ethernet interface uses parallel interface according to POR config inputs of eTSEC3 width and eTSEC3 protocol.
eTSEC1 Width
TSEC1_TX_ER
Default: eTSEC1 interface operates in standard width TBI, GMII, MII, or 8-bit FIFO mode.
eTSEC3 Width
TSEC3_TX_ER
Default: eTSEC3 Ethernet interface operates in standard TBI, GMII, MII, or 8-bit FIFO mode.
eTSEC1 Protocol
TSEC1_TXD[0:1]
Default: The eTSEC1 controller operates using the TBI protocol (or RTBI if configured in reduced mode).
eTSEC3 Protocol
TSEC3_TXD[0:1]
Default: The eTSEC3 controller operates using the TBI protocol (or RTBI if configured in reduced mode).
SGMII SerDes Reference Clock
TSEC3_TXD[3]
Default: SGMII SerDes expects a 125 MHz reference clock frequency.
PCI Clock Select
PCI1_GNT[4]
Default: Synchronous mode. SYSCLK is used as the clock for the PCI interface.
PCI Speed
PCI1_GNT[3]
Default: PCI frequency above 33 MHz.
PCI I/O Impedance
PCI1_GNT[1]
Default: 42 Ω I/O drivers are used on the PCI interface.
PCI Arbiter
PCI1_GNT[2]
Default: The on-chip PCI arbiter is enabled.
Memory Debug
MSRCID[0]
Default: Debug information from the DDR SDRAM controller is driven on the MSRCID and MDVAL signals.
DDR Debug
MSRCID[1]
Default: Debug information is not driven on ECC pins. ECC pins function in their normal mode.
General Purpose POR
LAD[0:31]
There is no default value for this general purpose POR.
Default: SEC in 3:1 (CCB CLK:SEC CLK). Refer to Section 5.3, “Security Controller PLL Ratio.”
Default: e500 core is allowed to boot without waiting for configuration by an external master. Default: Boot sequencer is disabled. No I2C ROM is accessed. Default: DDR controller is configured for DDR2.
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Power-on Reset and Reset Configurations
3.3
Internal Test Modes
Several pins double as test mode enables. These test modes are for internal use only, and if enabled during reset could result in the MPC8544E not coming out of reset. Table 6 lists these pins and how they should be addressed during the reset sequence. Table 6. Internal Test Mode Pins Pin Group
Pins
DDR
TEST_IN
Guideline for Reset Connect directly to ground
TEST_OUT Debug
This pin may be left floating.
TRIG_OUT/READY/ Because these pins have an internal pull-up enabled only at QUIESCE reset, they may be left floating if unconnected. Otherwise, they may need to be driven high (i.e., by a PLD), if the device to MSRCID[2] which they are connected does not release these pins to high impedance during reset. MSRCID[3] MSRCID[4
Design For Test
LSSD_MODE
These pins must be pulled to OVDD via a 100 Ω - 1 kΩ resistor.
L1_TSTCLK L2_TSTCLK TEST_SEL eTSEC
EC_MDC TSEC1_TXD[7] TSEC1_TXD[3]
Because these pins have an internal pull-up enabled only at reset, they may be left floating if unconnected. Otherwise, they may need to be driven high (i.e., by a PLD), if the device to which they are connected does not release these pins to high impedance during reset.
TSEC3_TXD[7]
3.4
Power Management
ASLEEP
System Control
HRESET_REQ
Reset Checklist
Table 7 provides a summary POR and reset checklist for the designer. Table 7. Checklist for POR and Reset Configurations Item
Description
1
HRESET is asserted for a minimum of 100 μs.
2
SRESET is asserted for a minimum of 3 SYSCLKs.
3
DMA_DACK[0:1] For proper state of these signals during reset, DMA_DACK[1] must be pulled down to GND through a resistor. DMA_DACK[0] can be pulled up or left without a resistor. However, if there is any device on the net which might pull down the value of the net at reset, a pull-up is needed on DMA_DACK[0].
4
Configuration pins are either appropriately tied-off with a 4.7 kΩ resistor or driven by an external device (meeting their required setup and hold times).
Completed
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
11
Device Pins
Table 7. Checklist for POR and Reset Configurations (continued) Item
Description
5
PLL configurations are defined and meet the required set-up and hold times.
6
Internal test mode pins are guaranteed not to be low during reset.
4
Completed
Device Pins
This section discusses the recommended test points and provides a device pin map.
4.1
Recommended Test Points
For easier debug, it is recommended that the test points on the board include the following pins: • CLK_OUT (This helps to verify the CCB clock.) • TRIG_OUT (This helps to verify the end of the reset sequence.) • ASLEEP (This helps to verify the end of the reset sequence.) • SENSEVDD (This helps to verify power plane VDD.) • SENSEVSS (This helps to verify ground plane VSS.) • HRESET_REQ (This helps to verify proper boot sequencer functions and reset requests.)
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 12
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Device Pins
4.2
Pin Map
Figure 4 provides a bottom view of the pin map of the device. A 1 2
MDQ [44]
B
C
D
E
F
G
GVDD
MDQS [5]
MDQ [32]
MDQ [46]
MDQ [47]
MDQ [34]
MDQ [40]
MDM [5]
MDQ [45]
MDQ [41]
4
MBA [0]
MWE
MCS [2]
5
MA [10]
MBA [1]
3
GND
MRAS
TEST_ OUT
NC
GND
7
GND
MA [0]
GVDD
8
MCK [3]
MCK [3]
MA [2]
6
9
MCK [0]
10
MA [3]
11
MA [6]
12
MA [11]
MCK [0]
GND
MODT [0]
GVDD
NC
GND
MA [4]
GVDD
MA [12]
14
GND
15
MDQ [26]
MDQ [31] MDQS [3]
GND
MECC [7]
MECC [6]
MDQS [8]
GVDD
MECC [1]
GND MDQ [19]
GVDD MDQ [23]
17
MDQS [3]
MDM [3]
GVDD
GND
18
MDQ [25]
MDQ [24]
MDQS [2]
MDM [2]
19 20
MDQ [29] MDQ [11]
21
MDQ [15]
22
MDQS [1]
23
MDQ [9]
MDQ [28] MDQ [10]
GVDD
MDQS [1]
MDQ [2]
MDQ [6]
MDM [1]
24 25
MDQ [12]
MDQ [5]
27 28
GND
GVDD MDQ [3]
MDQ [13]
MDQ [0]
GND
MDQ [17]
MDQ [14]
MDQ [8]
26
NC
MDQ [1] LDP [2]
MVREF
GND
A
B
MDQS [0]
MDQ [42] MDQ [33]
GVDD
GND
MDM [4]
GVDD
MDQ [37]
K
GND
MDQ [57]
MDQ [35]
MDQ [60]
MDQ [61]
GND
MA [15]
GVDD
MECC [2]
NC
GND
GND
MDQ [49]
MDQS [6]
MDQ [54]
MDQ [55]
LVDD [1]
MDQS [4]
MDQS [4]
MDQ [48]
GVDD
MCK [2]
NC
MCK [2]
MCKE [3]
MCK [5]
MCKE [0]
GVDD
GVDD
MCK [1]
MCK [1]
GVDD
GND
GND
GVDD
GVDD
GVDD
GND
GVDD
GND
MDIC [0]
GND
MDIC [1]
LCS [4]
LCS5/ DMA_ DREQ2
LCS6/ DMA_ DACK2
GND
MDQS [2]
MDQ [22]
GVDD
MDQ [21]
MDQ [16]
GND
LA [31]
LA [30]
GND
LGPL3/ LSDCAS
MDQ [20]
LCS [1]
BVDD
LGPL2 /LOE/ LSDRAS
LCS [3]
LAD [31]
LWE3/ LBS3/ LSDDQM [3]
MDQ [7]
GND
LCS [2]
GVDD LAD [27]
BVDD
GVDD
LAD [23]
MDM [0]
MDQ [4]
LDP [3]
LAD [19]
LAD [22]
LAD [18]
LAD [16]
BVDD
VDD
BVDD
GND
TSEC1_ TX_CLK
LGPL5
TVDD [1]
TSEC3_ TSEC3_ TSEC1_ TSEC1_ RXD RXD RXD RX_DV [3] [2] [3]
GND
TSEC3_ TSEC3_ RXD RXD [2] [0]
TVDD [2]
LA [27]
NC
VDD
GND
VDD
GND
VDD
GND
NC
VDD
GND
VDD
GND
VDD
GND
VDD
NC
NC
VDD
GND
VDD
GND
VDD
GND
NC
VDD
GND
VDD
GND
VDD
GND
VDD
NC
TSEC1_ TSEC1_ RXD RXD [7] [5] NC
NC
VDD
GND
VDD
GND
VDD
GND
NC
NC
VDD
GND
VDD
GND
VDD
GND
VDD
NC
NC
NC
BVDD
BVDD
AC
NC
MSRCID DMA_ DDONE [0] [0]
MSRCID [1]
MDVAL EC_ MDIO
UART_ CTS [0]
8
MSRCID PCI1_ AD [2] [26]
PCI1_ AD [25]
OVDD [7]
PCI1_ AD [24]
PCI1_ REQ [4]
UART_ RTS [1]
GND
9
PCI1_ AD [23]
PCI1_ AD [22]
OVDD [14]
PCI1_ REQ [3]
PCI1_ REQ [2]
10
PCI1_ GNT [2]
11
GND
NC
SENSE- DMA_ DMA_ VDD DDONE DREQ [1] [1]
PCI1_ AD [20]
PCI1_ AD [21]
OVDD [8]
PCI1_ AD [16]
GND
PCI1_ GNT [3]
NC
NC
DMA_ DACK [1]
CKSTP_ PCI1_ AD OUT [19]
PCI1_ AD [18]
PCI1_ FRAME
PCI1_ C_BE [2]
PCI1_ AD [17]
PCI1_ AD [27]
PCI1_ AD [28]
12
NC
DMA_ DACK [0]
PCI1_ STOP
OVDD PCI1_ DEVSEL [4]
PCI1_ TRDY
OVDD [9]
PCI1_ IRDY
IIC2_ SCL
TEST_ SEL
13
NC
PCI1_ AD [15]
PCI1_ C_BE [1]
PCI1_ PAR
PCI1_ SERR
IRQ_ OUT
PCI1_ PERR
GND
IIC2_ SDA
AVDD_ CORE
14
NC
PCI1_ AD [9]
PCI1_ AD [11]
PCI1_ AD [12]
PCI1_ AD [13]
OVDD [10]
PCI1_ AD [14]
RTC
HRESET_ REQ
UDE
15
OVDD [1]
PCI1_ AD [0]
PCI1_ AD [8]
GND
PCI1_ AD [10]
CLK_ OUT
IRQ [5]
HRESET SYSCLK
PCI1_ L2_ C_BE TSTCLK [0]
NC
NC
NC
NC
NC
NC
NC
NC SD1_ PLL_ TPA
LAD [15]
LAD [14]
GND
LAD [11]
LAD [9]
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SRDS [0] [2] SRDS SRDS
AVDD_ LSYNC_ OUT LBIU
LAD [20]
LAD [17]
LDP [1]
LAD [13]
LAD [12]
LAD [10]
LAD [8]
SGND_ SD1_RX SVDD_ SD1_RX SGND_ [2] [0] SRDS SRDS SRDS
SD1_ REF_ CLK
SD1_ PLL_ TPD
E
F
G
H
J
K
L
U
V
T
7
UART_ RTS [0]
OVDD [3]
GND
R
UART_ SOUT [0]
SENSEVSS
NC
GND
NC
NC
GND
PCI1_ AD [2]
PCI1_ AD [5]
NC
PCI1_ AD [1]
OVDD [6] IRQ [8]
AGND_ SRDS
IRQ [1]
16
IRQ [4]
ASLEEP
17 18
GND
PCI1_ AD [6]
PCI1_ AD [7]
MCP
AVDD_ PLAT
PCI1_ AD [3]
PCI1_ AD [4]
IRQ [3]
SRESET
LSSD_ MODE
19
GPIN [7]
OVDD [15]
IRQ[9] DMA_ DREQ3
AVDD_ PCI1
20
IRQ [2]
GPIN [3]
GPOUT [4]
IIC1_ SCL
IIC1_ SDA
21
GPIN [4]
OVDD [13]
GPOUT [0]
IRQ [0]
TRST
22
GPIN [2]
GND
GPIN [5]
GND
GPOUT [1]
23
IRQ[11] DMA_ DDONE3
OVDD [16]
GPIN [1]
GPIN [0]
24
SGND_ SD1_RX SVDD_ SD1_RX SGND_ SD2_RX SGND_ GPOUT [5] SRDS2 SRDS2 SRDS [0] [4] [6] SRDS
GPIN [6]
GPOUT [3]
25
PCI1_ CLK
26
NC
NC
NC
SVDD_ SGND_ SGND_ SVDD_ SRDS SRDS SRDS SRDS
SD1_ SGND_ SD1_RX SVDD_ SD1_RX SGND_ IMP_CAL SRDS SRDS [3] [1] SRDS _RX
P
UART_ SIN [0]
NC
NC
NC
NC
L1_ OVDD TSTCLK [11]
NC
GND
SEE DETAIL D
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SRDS [1] [3] SRDS SRDS
N
UART_ SOUT [1] PCI1_ AD [29]
IRQ [6]
M
6
PCI1_ GNT [4] PCI1_ AD [31]
NC
GND
PCI1_ IDSEL
UART_ SIN [1]
GND
XVDD_ SD1_TX XGND_ SD1_TX XVDD_ [5] [7] SRDS SRDS SRDS2
LDP [0]
UART_ CTS [1]
PCI1_ AD [30]
SD1_TX XVDD_ SD1_TX XGND_ [0] [2] SRDS SRDS
NC
PCI1_ GNT [0]
PCI1_ GNT [1]
NC
LBCTL
5
PCI1_ REQ [1]
PCI1_ REQ [0]
SD1_ TST_ CLK
NC
XVDD_ XVDD_ CKSTP_ SRDS2 SRDS2 IN
EC_ MDC
IRQ [7]
LAD [6]
4
OVDD [12]
SD2_ TST_ CLK
OVDD [2]
XGND_ SD1_TX XVDD_ SD1_TX XGND_ [5] [7] SRDS SRDS2 SRDS
LAD [7]
2 3
SEE DETAIL B
NC
1
XGND_ SRDS2
NC
XVDD_ XVDD_ MSRCID OVDD [3] [5] SRDS2 SRDS2
SVDD_ SGND_ SRDS2 SRDS2
SD2_ TST_ CLK
TRIG_ SD2_TX SD2_TX OUT/READY TRIG_ MSRCID IN [3] [3] [4] /QUIESCE
NC
AH SD2_ PLL_ TPA
SD2_ IMP_CAL _RX
NC
SD1_ TST_ CLK
SGND_ SVDD_ SRDS SRDS
AG
SD2_ PLL_ TPD
XGND_ XGND_ SD2_TX SD2_TX XGND_ XGND_ SRDS2 SRDS2 SRDS2 SRDS2 [2] [2]
SD1_TX XGND_ SD1_TX XVDD_ [2] SRDS [0] SRDS
XGND_ SRDS
SD2_ REF_ CLK
TEMP_ TEMP_ SGND_ SGND_ SGND_ SGND_ SGND_ ANODE CATHODE SRDS2 SRDS2 SRDS2 SRDS2 SRDS2
LAD [2]
LAD [5]
SD2_ REF_ CLK
NC
LAD [0]
LAD [4]
AF
NC
GND
BVDD
AE
SGND_ SD2_RX SD2_RX SGND_ SVDD_ SRDS2 SRDS2 SRDS2 [3] [3]
XVDD_ SD1_TX XGND_ SD1_TX XGND_ SD1_TX XVDD_ SD1_TX XGND_ SD2_TX SRDS SRDS SRDS [0] [3] [4] [6] [1] SRDS SRDS
LAD [3]
AD
NC
LAD [1]
LCLK [1]
LALE
AB
NC
LAD [21]
D
AA
PCI1_ C_BE [3]
LSYNC_ IN
C
Y
SD2_ SGND_ SVDD_ SD2_RX SD2_RX SGND_ AGND_ AVDD_ IMP_CAL SRDS2 SRDS2 SRDS2 SRDS2 SRDS2 [2] [2] _TX
DMA_ DREQ [0]
SD1_ REF_ CLK
GND
W
LGPL4 LGPL0/ LGPL1/ /LGTA/ XGND_ SD1_TX XVDD_ SD1_TX XVDD_ SD1_TX XGND_ SD1_TX XVDD_ SD2_TX LSDA10 LSDWE LUPWAIT/ SRDS [1] [3] [4] [6] [0] SRDS SRDS SRDS SRDS LPBSE
LAD [28]
GND
GND
LCS7/ DMA_ DDONE2
LWE2/ LBS2/ LSDDQM [2]
LCLK [2]
VDD
LCS [0]
LWE1/ LWE0/ LBS1/ LBS0/ LSDDQM LSDDQM [1] [0]
LCLK [0]
LA [28]
NC
LCKE
LAD [30]
LAD [26]
NC
GND
LA [29]
SEE DETAIL C LAD [29]
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TXD TXD RXD TXD TX_EN [2] [1] [0] [0]
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC3_ RXD RXD RXD RXD RX_ER [4] [5] [6] [7]
GND
BVDD
GND
TSEC1_ TSEC1_ TSEC1_ TSEC1_ TXD TXD TXD COL [6] [7] [5]
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ RXD RXD RX_CLK RX_ER RXD CRS COL [6] [1] [4]
MCKE TSEC3_ TX_CLK [1]
MECC [4]
MDQ [18]
MCK [4]
TSEC1_ TSEC1_ TX_EN CRS
TSEC1_ TXD [4]
GND
MECC [5]
MCK [4]
GND
LVDD [2]
TSEC3_ TSEC3_ TXD TX_ER [4]
NC
NC
GVDD
V
GND
GND
LAD [24]
GND
MCK [5]
NC
GND
U
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ GTX_ TXD TXD TXD TXD RXD RX_DV RX_CLK [5] [6] [3] CLK [7] [1]
MDM [8]
GVDD
MDQ [63]
MDQ [53]
MDQS [8]
GND
MDQS [7]
MDQ [39]
MCKE [2]
MECC [0]
GND
GVDD TSEC1_ TX_ER
MCAS
MA [14]
MDQS [7]
MDQ [51]
MODT [1]
GVDD
GVDD
T
TSEC1_ TSEC1_ TSEC1_ GTX_ TXD TXD [0] [2] CLK EC_ TSEC1_ TSEC1_ GTX_ TXD TXD CLK125 [1] [3]
MDQ [50]
GVDD
MA [7]
R MDQ [59]
MDQS [6]
MA [13]
MA [8]
P MDQ [58]
MDM [6]
MCS [1]
GND
MDM [7]
N MDQ [62]
GVDD
MCS [3]
GVDD
GND
M
MDQ [52]
MODT [3]
MA [1]
L
MDQ [38]
MODT [2]
MDQS [0]
LAD [25]
MDQ [43]
J MDQ [56]
SEE DETAIL A
MECC [3]
MDQ [27]
MDQ [30]
GVDD
MDQ [36]
NC
MBA [2]
16
GND
MA [5]
MA [9]
GVDD
MCS [0]
GND
TEST_ IN
13
GVDD
MDQS [5]
H
SVDD_ SGND_ SGND_ SGND_ SGND_ SRDS SRDS SRDS SRDS2 SRDS
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SD2_RX SVDD_ GPOUT GPOUT [7] [6] SRDS [6] [4] SRDS SRDS2 SRDS2 [0] NC
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SRDS [5] [7] SRDS SRDS
IRQ[10] DMA_ DACK3
AVDD_ SGND_ SD1_RX SVDD_ SD1_RX SGND_ SD1_ IMP_CAL [7] [5] SRDS SRDS SRDS SRDS _TX
W
Y
AA
AB
AC
AD
AE
OVDD [17]
GPOUT [2]
TMS
27
TDO
TCK
TDI
28
AF
AG
AH
Figure 4. MPC8544E Pin Map Top View
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
13
Device Pins
A 1
B
C
D
E
F
G
H
J
K
L
M
N
P
GVDD
MDQS [5]
MDQ [32]
MDQ [46]
MDQ [47]
MDQ [34]
GND
MDQ [56]
MDQ [57]
GND
GVDD
MDQ [62]
MDQ [58]
2
MDQ [44]
MDQ [40]
MDM [5]
MDQS [5]
GVDD
MDQ [42]
MDQ [43]
MDQ [35]
MDQ [60]
MDQ [61]
MDM [7]
MDQS [7]
GND
MDQS [7]
3
GND
MDQ [45]
MDQ [41]
MCS [0]
GND
MDQ [33]
GVDD
MDQ [38]
MDQ [52]
GVDD
MDM [6]
MDQS [6]
MDQ [50]
MDQ [51]
4
MBA [0]
MWE
MCS [2]
GVDD
MDQ [36]
GND
MDM [4]
GND
MDQ [39]
MDQ [53]
MDQ [49]
MDQS [6]
MDQ [54]
MDQ [55]
5
MA [10]
MBA [1]
MRAS
GND
MODT [0]
GVDD
MDQ [37]
GVDD
MDQS [4]
MDQS [4]
MDQ [48]
GND
GVDD
GND
6
TEST_ OUT
NC
GND
GVDD
MODT [2]
MODT [3]
MCS [3]
MCS [1]
MCK [2]
MCK [2]
NC
7
GND
MA [0]
GVDD
NC
MCAS
MA [13]
GVDD
MODT [1]
NC
GND
TSEC3_ TSEC3_ TXD TXD [3] [7]
8
MCK [3]
MCK [3]
MA [2]
GND
GVDD
GND
MA [1]
MCK [5]
MCK [5]
GND
TSEC3_ TSEC3_ TXD TX_ER [4]
9
MCK [0]
MCK [0]
GVDD
MA [4]
MA [8]
MA [7]
GVDD
MCKE [3]
NC
NC
TSEC3_ TSEC3_ CRS COL
TSEC3_ TSEC3_ RXD RX_CLK [1]
10
MA [3]
GND
MA [5]
NC
MA [14]
MA [15]
MCKE [2]
MCKE [0]
GVDD
MCKE [1]
TSEC3_ TX_CLK
TSEC3_ TSEC3_ RXD RXD [0] [2]
11
MA [6]
GVDD
MECC [3]
MA [12]
GVDD
MECC [2]
GVDD
MCK [1]
MCK [1]
GND
TSEC3_ TSEC3_ TSEC3_ TSEC3_ RXD RXD RXD RXD [4] [5] [6] [7]
12
MA [11]
MA [9]
GND
MECC [7]
GND
NC
MECC [0]
GVDD
GND
GVDD
GND
NC
VDD
NC
13
TEST_ IN
MBA [2]
MECC [6]
MDQS [8]
MDQS [8]
MDM [8]
GND
MCK [4]
MCK [4]
NC
NC
VDD
GND
VDD
14
GND
MDQ [27]
GVDD
MECC [1]
GVDD
MECC [5]
MECC [4]
GVDD
GND
GVDD
VDD
GND
VDD
GND
TSEC3_ TSEC3_ TSEC3_ TXD TXD TX_EN [1] [0]
GND
TSEC3_ TSEC3_ TXD TXD [5] [6] TVDD [1]
TSEC3_ RX_DV
DETAIL A Figure 5. MPC8544E Pin Map Detail A
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 14
Freescale Semiconductor
Device Pins
R
T
U
MDQ [59]
TSEC1_ GTX_ CLK
TSEC1_ TSEC1_ TXD TXD [2] [0]
NC
MDQ [63]
EC_ GTX_ CLK125
TSEC1_ TSEC1_ TXD TXD [3] [1]
NC
SGND_ SD2_RX SD2_RX SRDS2 [3] [3]
SGND_ SRDS2
GVDD
TSEC1_ TX_ER
TSEC1_ TXD [4]
NC
TEMP_ TEMP_ SGND_ ANODE CATHODE SRDS2
LVDD [1]
TSEC1_ TSEC1_ TX_EN CRS
GND
NC
XGND_ SRDS2
LVDD [2]
V
W
Y
AA
SD2_ SGND_ IMP_CAL SRDS2 _TX
XGND_ SRDS2
AB
AE
AF
AG
AH
SGND_ SRDS2
AGND_ SRDS2
AVDD_ SRDS2
SD2_ PLL_ TPA
1
SVDD_ SRDS2
SD2_ REF_ CLK
SD2_ REF_ CLK
SVDD_ SRDS2
SGND_ SRDS2
2
SGND_ SRDS2
SGND_ SRDS2
SGND_ SRDS2
SGND_ SRDS2
SD2_ PLL_ TPD
SD2_ IMP_CAL _RX
3
SD2_TX SD2_TX [2] [2]
XGND_ SRDS2
XGND_ SRDS2
SD2_ TST_ CLK
SD2_ TST_ CLK
XGND_ SRDS2
4
MSRCID [4]
OVDD [12]
XVDD_ SRDS2
XVDD_ SRDS2
CKSTP_ IN
5
OVDD [5]
PCI1_ REQ [1]
PCI1_ GNT [0]
UART_ CTS [1]
PCI1_ IDSEL
UART_ SIN [1]
6
SVDD_ SRDS2
AC
AD
SD2_RX SD2_RX [2] [2]
TSEC1_ COL
TSEC1_ TSEC1_ TSEC1_ TXD TXD TXD [5] [7] [6]
NC
TRIG_ SD2_TX SD2_TX OUT/READY TRIG_ IN [3] [3] /QUIESCE
TSEC3_ TXD [2]
TSEC1_ RXD [0]
TSEC1_ TX_CLK
NC
XVDD_ SRDS2
TSEC3_ TSEC1_ TSEC1_ TSEC1_ GTX_ RXD RX_DV RX_CLK [1] CLK
NC
DMA_ MSRCID DDONE [0] [0]
OVDD [2]
EC_ MDC
GND
PCI1_ GNT [4]
UART_ SOUT [1]
UART_ SIN [0]
UART_ SOUT [0]
7
TSEC3_ TSEC1_ TSEC1_ RXD RXD RXD [2] [3] [3]
NC
NC
MDVAL
GND
PCI1_ REQ [0]
PCI1_ GNT [1]
PCI1_ AD [30]
PCI1_ AD [31]
PCI1_ AD [29]
UART_ RTS [0]
UART_ CTS [0]
8
TSEC1_ TSEC1_ RXD RX_ER [4]
TSEC1_ RXD [6]
NC
MSRCID [1]
EC_ MDIO
MSRCID [2]
PCI1_ AD [26]
PCI1_ AD [25]
OVDD [7]
PCI1_ AD [24]
PCI1_ REQ [4]
UART_ RTS [1]
GND
9
TVDD [2]
TSEC1_ RXD [5]
TSEC1_ RXD [7]
NC
SENSEVSS
GND
DMA_ DREQ [0]
OVDD [3]
PCI1_ C_BE [3]
PCI1_ AD [23]
PCI1_ AD [22]
OVDD [14]
PCI1_ REQ [3]
PCI1_ REQ [2]
10
TSEC3_ RX_ER
NC
NC
NC
DMA_ SENSEDDONE VDD [1]
DMA_ DREQ [1]
PCI1_ AD [20]
PCI1_ AD [21]
OVDD [8]
PCI1_ AD [16]
GND
PCI1_ GNT [3]
PCI1_ GNT [2]
11
VDD
NC
VDD
NC
NC
DMA_ DACK [1]
CKSTP_ OUT
PCI1_ AD [19]
PCI1_ AD [18]
PCI1_ FRAME
PCI1_ C_BE [2]
PCI1_ AD [17]
PCI1_ AD [27]
PCI1_ AD [28]
12
GND
VDD
GND
NC
NC
DMA_ DACK [0]
PCI1_ STOP
OVDD [4]
PCI1_ DEVSEL
PCI1_ TRDY
OVDD [9]
PCI1_ IRDY
IIC2_ SCL
TEST_ SEL
13
VDD
GND
VDD
NC
NC
PCI1_ AD [15]
PCI1_ C_BE [1]
PCI1_ PAR
PCI1_ SERR
IRQ_ OUT
PCI1_ PERR
GND
IIC2_ SDA
AVDD_ CORE
14
GND
XVDD_ MSRCID [3] SRDS2
DETAIL B Figure 6. MPC8544E Pin Map Detail B
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
15
Device Pins
DETAIL C 15
MDQ [26]
MDQ [31]
GND
GVDD
GND
GVDD
GND
MDIC [0]
GND
MDIC [1]
GND
VDD
GND
VDD
16
MDQ [30]
MDQS [3]
MDQ [19]
MDQ [23]
MDQ [18]
GND
LCS [4]
LCS5/ DMA_ DREQ2
LCS6/ DMA_ DACK2
LA [28]
VDD
GND
VDD
GND
17
MDQS [3]
MDM [3]
GVDD
GND
MDQS [2]
MDQ [22]
LA [31]
LA [30]
GND
LA [29]
LCKE
VDD
GND
VDD
18
MDQ [25]
MDQ [24]
MDQS [2]
MDM [2]
GVDD
MDQ [21]
GND
LGPL3/ LSDCAS
BVDD
LCS [0]
LCS7/ DMA_ DDONE2
GND
VDD
GND
19
MDQ [29]
MDQ [28]
NC
MDQ [17]
MDQ [16]
MDQ [20]
LCS [1]
LCS [2]
BVDD
LGPL5
LA [27]
NC
NC
NC
20
MDQ [11]
MDQ [10]
GND
GVDD
GND
BVDD
LGPL2 /LOE/ LSDRAS
LCS [3]
LGPL0/ LSDA10
LGPL4 LGPL1/ /LGTA/ XGND_ LSDWE LUPWAIT/ SRDS LPBSE
SD1_TX [1]
XVDD_ SRDS
21
MDQ [15]
MDQ [14]
GVDD
MDQ [3]
MDQ [7]
GND
LAD [31]
LWE3/ LBS3/ LSDDQM [3]
BVDD
22
MDQS [1]
MDQS [1]
MDQ [2]
MDQ [6]
GVDD
LAD [29]
LAD [30]
23
MDQ [9]
MDM [1]
MDQS [0]
GND
LAD [27]
BVDD
24
MDQ [8]
MDQ [13]
GVDD
MDQS [0]
LAD [24]
25
MDQ [12]
MDQ [5]
MDM [0]
MDQ [4]
26
MDQ [0]
MDQ [1]
LAD [25]
27
GND
LDP [2]
28
MVREF
A
GND
LAD [1]
XVDD_ SRDS
SD1_TX [1]
XGND_ SRDS
LWE1/ LWE0/ LBS1/ LBS0/ LSDDQM LSDDQM [1] [0]
LAD [0]
LAD [2]
SD1_TX [0]
XGND_ SRDS
SD1_TX [2]
LAD [28]
LWE2/ LBS2/ LSDDQM [2]
BVDD
LAD [3]
BVDD
SD1_TX [0]
XVDD_ SRDS
SD1_TX [2]
LAD [23]
LAD [26]
LCLK [0]
LCLK [1]
LAD [4]
LAD [5]
XGND_ SRDS
NC
SGND_ SRDS
LDP [3]
LAD [19]
GND
LCLK [2]
LBCTL
LAD [7]
LAD [6]
NC
SVDD_ SRDS
SD1_RX [1]
GND
LAD [22]
LAD [18]
LAD [16]
BVDD
LALE
LDP [0]
GND
GND
LSYNC_ IN
LAD [21]
GND
LAD [15]
LAD [14]
GND
LAD [11]
LAD [9]
SVDD_ SRDS
SD1_RX [0]
SGND_ SRDS
GND
AVDD_ LBIU
LSYNC_ OUT
LAD [20]
LAD [17]
LDP [1]
LAD [13]
LAD [12]
LAD [10]
LAD [8]
SGND_ SRDS
SD1_RX [0]
SVDD_ SRDS
B
C
D
E
F
G
H
J
K
L
M
N
P
SD1_ SGND_ SD1_RX IMP_CAL SRDS [1] _RX
Figure 7. MPC8544E Pin Map Detail C
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 16
Freescale Semiconductor
Device Pins
DETAIL D GND
VDD
GND
NC
NC
PCI1_ AD [9]
PCI1_ AD [11]
PCI1_ AD [12]
PCI1_ AD [13]
OVDD [10]
PCI1_ AD [14]
RTC
HRESET_ REQ
VDD
GND
VDD
NC
NC
OVDD [1]
PCI1_ AD [0]
PCI1_ AD [8]
GND
PCI1_ AD [10]
CLK_ OUT
IRQ [5]
HRESET SYSCLK
GND
VDD
GND
NC
NC
NC
GND
PCI1_ AD [2]
PCI1_ AD [5]
PCI1_ C_BE [0]
L2_ TSTCLK
IRQ [1]
IRQ [4]
ASLEEP
17
VDD
GND
VDD
NC
NC
NC
NC
PCI1_ AD [1]
OVDD [6]
GND
PCI1_ AD [6]
PCI1_ AD [7]
MCP
AVDD_ PLAT
18
NC
NC
NC
NC
NC
NC
NC
NC
IRQ [8]
PCI1_ AD [3]
PCI1_ AD [4]
IRQ [3]
SRESET
LSSD_ MODE
19
SD1_TX [3]
XVDD_ SRDS
SD1_TX [4]
XGND_ SRDS
SD1_TX [6]
XVDD_ SRDS
SD2_TX [0]
NC
L1_ TSTCLK
OVDD [11]
GPIN [7]
OVDD [15]
IRQ[9] DMA_ DREQ3
AVDD_ PCI1
20
SD1_TX [3]
XGND_ SRDS
SD1_TX [4]
XVDD_ SRDS
SD1_TX [6]
XGND_ SRDS
SD2_TX [0]
NC
GND
IRQ [2]
GPIN [3]
GPOUT [4]
IIC1_ SCL
IIC1_ SDA
21
XVDD_ SRDS
SD1_ TST_ CLK
XGND_ SRDS
SD1_TX [5]
XVDD_ SRDS
SD1_TX [7]
XGND_ SRDS2
NC
IRQ [7]
GPIN [4]
OVDD [13]
GPOUT [0]
IRQ [0]
TRST
22
XGND_ SRDS
SD1_ TST_ CLK
XVDD_ SRDS
SD1_TX [5]
XGND_ SRDS
SD1_TX [7]
XVDD_ SRDS2
NC
IRQ [6]
GPIN [2]
GND
GPIN [5]
GND
GPOUT [1]
23
SVDD_ SRDS
SVDD_ SRDS
SGND_ SRDS
SGND_ SRDS
SVDD_ SRDS
SVDD_ SRDS
SGND_ SRDS
SGND_ SRDS
SGND_ SRDS
SGND_ SRDS2
IRQ[11] DMA_ DDONE3
OVDD [16]
GPIN [1]
GPIN [0]
24
SGND_ SRDS
SD1_RX [3]
SVDD_ SRDS
NC
SGND_ SD1_RX SRDS [4]
SVDD_ SRDS
SD1_RX SGND_ SRDS2 [6]
SD2_RX SGND_ [0] SRDS2
GPOUT [5]
GPIN [6]
GPOUT [3]
25
SVDD_ SRDS
SD1_RX [3]
SGND_ SRDS
SD1_ PLL_ TPA
SVDD_ SRDS
SD1_RX [4]
SGND_ SD1_RX [6] SRDS
SVDD_ SRDS2
SD2_RX [0]
SVDD_ SRDS2
GPOUT [7]
GPOUT [6]
PCI1_ CLK
26
SD1_RX [2]
SVDD_ SRDS
SD1_ REF_ CLK
AGND_ SRDS
NC
SVDD_ SRDS
SD1_RX SGND_ SD1_RX [5] [7] SRDS
SVDD_ SRDS
IRQ[10] DMA_ DACK3
OVDD [17]
GPOUT [2]
TMS
27
SD1_RX [2]
SGND_ SRDS
SD1_ REF_ CLK
SD1_ PLL_ TPD
AVDD_ SRDS
TDO
TCK
TDI
28
R
T
U
V
W
AF
AG
AH
SGND_ SD1_RX [5] SRDS
Y
AA
SVDD_ SRDS
AB
SD1_ SD1_RX SGND_ IMP_CAL [7] SRDS _TX
AC
AD
AE
UDE
15
16
Figure 8. MPC8544E Pin Map Detail D
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
17
Device Pins
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
GVDD
MDQS [5]
MDQ [32]
MDQ [46]
MDQ [47]
MDQ [34]
GND
MDQ [56]
MDQ [57]
GND
GVDD
MDQ [62]
MDQ [58]
MDQ [59]
MDQ [44]
MDQ [40]
MDM [5]
MDQS [5]
GVDD
MDQ [42]
MDQ [43]
MDQ [35]
MDQ [60]
MDQ [61]
MDM [7]
MDQS [7]
GND
MDQS [7]
MDQ [63]
GND
MDQ [45]
MDQ [41]
MCS [0]
GND
MDQ [33]
GVDD
MDQ [38]
MDQ [52]
GVDD
MDM [6]
MDQS [6]
MDQ [50]
MDQ [51]
GVDD TSEC1_ TX_ER
1 2 3 4
MBA [0]
5
MA [10]
6
TEST_ OUT
7
GND
MWE MBA [1]
NC MA [0]
8
MCK [3]
MCK [3]
9
MCK [0]
10
MA [3]
11
MA [6]
MCS [2] MRAS
GND
GVDD
GVDD
MDQ [36]
GND
MDQ [37]
GVDD
MDQS [4]
MDQS [4]
GVDD
MODT [2]
MODT [3]
MCS [3]
MCS [1]
MCK [2]
MCK [2]
NC
MCAS
MA [13]
MA [7]
GVDD
MCKE [3]
MA [15]
MCKE [2]
MCKE [0]
GVDD
MA [4]
MA [8]
GND
MA [5]
NC
MA [14]
12 13
TEST_ IN
MBA [2]
GVDD
MODT [1] MCK [5]
MCK [0]
MA [12]
GVDD MA [1]
GND
MA [9]
MDQ [53]
GVDD
GVDD
MA [11]
MDQ [39]
MODT [0]
GND
MECC [3]
GND
GND
MA [2]
GVDD
MDM [4]
MECC [2]
GND
MECC [7]
GND
NC
MECC [6]
MDQS [8]
MDQS [8]
MDM [8]
GVDD
MCK [1]
NC MCK [5]
NC
GVDD MCK [1]
MECC [0]
GVDD
GND
GND
MCK [4]
MCK [4]
GND
GND
NC
MDQ [49] MDQ [48]
NC
GVDD
NC
GND
MDQ [54] GVDD
MDQ [55]
GND
LVDD [1]
U
V
LVDD [2]
TSEC1_ TSEC1_ TX_EN CRS
TSEC1_ TXD [4] GND
TSEC1_ TSEC1_ TSEC1_ TSEC1_ TXD TXD TXD COL [6] [7] [5]
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TXD TXD RXD TXD TX_EN [1] [2] [0] [0]
GND
TSEC1_ TX_CLK
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ GTX_ TXD TXD TXD TXD RXD RX_DV RX_CLK [6] [5] CLK [3] [7] [1] TSEC3_ TSEC3_ TXD TX_ER [4]
TVDD [1]
TSEC3_ TSEC3_ TSEC1_ TSEC1_ RXD RXD RXD RX_DV [3] [2] [3]
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ RXD RX_CLK RX_ER RXD RXD CRS COL [1] [6] [4]
MCKE TSEC3_ TX_CLK [1]
GND
MDQS [6]
T
TSEC1_ TSEC1_ TSEC1_ GTX_ TXD TXD [0] [2] CLK EC_ TSEC1_ GTX_ TSEC1_ TXD TXD CLK125 [1] [3]
GND
TSEC3_ TSEC3_ RXD RXD [2] [0]
TVDD [2]
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC3_ RXD RXD RXD RXD RX_ER [4] [5] [6] [7] GND
NC
NC
VDD
VDD
GND
NC
VDD
VDD
GND
TSEC1_ TSEC1_ RXD RXD [5] [7] NC
NC
VDD
NC
VDD
GND
W
Y
AC
AD
AE
NC
TEMP_ TEMP_ SGND_ SGND_ SGND_ SGND_ SGND_ ANODE CATHODE SRDS2 SRDS2 SRDS2 SRDS2 SRDS2
NC
XGND_ XGND_ SD2_TX SD2_TX XGND_ XGND_ SRDS2 SRDS2 SRDS2 SRDS2 [2] [2]
NC
TRIG_ SD2_TX SD2_TX OUT/READY TRIG_ MSRCID OVDD IN [4] [3] [3] [12] /QUIESCE
NC
XVDD_ SRDS2
NC
MSRCID DMA_ DDONE [0] [0]
OVDD [2]
EC_ MDC
PCI1_ REQ [0]
PCI1_ GNT [1]
MSRCID PCI1_ AD [2] [26]
MDVAL
NC
MSRCID [1]
EC_ MDIO
NC
SENSEVSS
NC
SENSE- DMA_ VDD DDONE [1]
GND
GND
6
GND
7
PCI1_ AD [30]
PCI1_ AD [31]
PCI1_ AD [29]
UART_ RTS [0]
UART_ CTS [0]
8
PCI1_ AD [25]
OVDD [7]
PCI1_ AD [24]
PCI1_ REQ [4]
UART_ RTS [1]
GND
9
PCI1_ AD [23]
PCI1_ AD [22]
OVDD [14]
PCI1_ REQ [3]
PCI1_ REQ [2]
10
OVDD [8]
PCI1_ AD [16]
GND
PCI1_ GNT [3]
PCI1_ GNT [2]
11
PCI1_ FRAME
PCI1_ C_BE [2]
PCI1_ AD [17]
PCI1_ AD [27]
PCI1_ AD [28]
12
OVDD [9]
PCI1_ IRDY
IIC2_ SCL
TEST_ SEL
13
DMA_ DREQ [0]
OVDD [3]
PCI1_ C_BE [3]
DMA_ DREQ [1]
PCI1_ AD [20]
PCI1_ AD [21]
NC
DMA_ DACK [1]
CKSTP_ OUT
PCI1_ AD [19]
NC
DMA_ DACK [0]
PCI1_ STOP
OVDD [4]
PCI1_ C_BE [1]
PCI1_ PAR
PCI1_ SERR
IRQ_ OUT
PCI1_ PERR
GND
IIC2_ SDA
AVDD_ CORE
14
PCI1_ AD [13]
OVDD [10]
PCI1_ AD [14]
RTC
HRESET_ REQ
UDE
15
CLK_ OUT
IRQ [5]
HRESET SYSCLK
PCI1_ AD [18]
PCI1_ PCI1_ DEVSEL TRDY
GND
GVDD
VDD
GND
VDD
GND
VDD
GND
VDD
NC
NC
15
MDQ [26]
MDQ [31]
GND
GVDD
GND
GVDD
GND
MDIC [0]
GND
MDIC [1]
GND
VDD
GND
VDD
GND
VDD
GND
NC
NC
PCI1_ AD [9]
PCI1_ AD [11]
PCI1_ AD [12]
16
MDQ [30]
MDQS [3]
MDQ [19]
MDQ [23]
MDQ [18]
GND
LCS [4]
LCS5/ DMA_ DREQ2
LCS6/ DMA_ DACK2
LA [28]
NC
OVDD [1]
PCI1_ AD [0]
PCI1_ AD [8]
GND
PCI1_ AD [10]
GND
PCI1_ AD [2]
PCI1_ AD [5]
PCI1_ L2_ C_BE TSTCLK [0]
NC
PCI1_ AD [1]
OVDD [6]
NC
IRQ [8]
MDM [3]
18
MDQ [25]
MDQ [24]
19
MDQ [29]
MDQ [28]
20
MDQ [11]
MDQ [10]
21
MDQ [15]
MDQ [14]
GVDD
GND
MDQS [2]
MDQ [22]
LA [31]
LA [30]
GND
LCKE
LCS [0]
LCS7/ DMA_ DDONE2
LGPL5
LA [27]
MDQS [2]
MDM [2]
GVDD
MDQ [21]
GND
NC
MDQ [17]
MDQ [16]
MDQ [20]
LCS [1]
LCS [2]
BVDD
LGPL2 /LOE/ LSDRAS
LCS [3]
LAD [31]
LWE3/ LBS3/ LSDDQM [3]
LAD [29]
LAD [30]
LWE1/ LWE0/ LBS1/ LBS0/ LSDDQM LSDDQM [1] [0]
LAD [0]
BVDD
LAD [28]
LWE2/ LBS2/ LSDDQM [2]
LAD [3]
GND
GVDD
22
MDQS [1]
MDQS [1]
MDQ [2]
23
MDQ [9]
MDM [1]
MDQS [0]
GVDD MDQ [3]
GND MDQ [7]
MDQ [6]
GVDD
GND
LAD [27]
GND
LGPL3/ BV DD LSDCAS
LA [29]
BVDD
VDD
GND
NC
NC
ASLEEP
17
GND
MCP
AVDD_ PLAT
18
PCI1_ AD [3]
PCI1_ AD [4]
IRQ [3]
LSSD_ SRESET MODE
19
L1_ OVDD TSTCLK [11]
GPIN [7]
OVDD [15]
IRQ[9] DMA_ DREQ3
AVDD_ PCI1
20
IIC1_ SDA
21
IIC1_ SCL
NC
IRQ [7]
GPIN [4]
OVDD [13]
GPOUT [0]
IRQ [0]
TRST
22
NC
IRQ [6]
GPIN [2]
GND
GPIN [5]
GND
GPOUT [1]
23
OVDD [16]
GPIN [1]
GPIN [0]
24
SGND_ SD1_RX SVDD_ SD1_RX SGND_ SD2_RX SGND_ GPOUT [5] SRDS2 SRDS2 SRDS [0] [4] [6] SRDS
GPIN [6]
GPOUT [3]
25
PCI1_ CLK
26
BVDD
LAD [2]
SD1_TX XGND_ SD1_TX XVDD_ [2] SRDS [0] SRDS
BVDD
SD1_TX XVDD_ SD1_TX XGND_ [2] [0] SRDS SRDS
SD1_ TST_ CLK
SGND_ SVDD_ SRDS SRDS
LCLK [1]
LAD [4]
LAD [5]
XGND_ SRDS
25
MDQ [12]
MDQ [5]
MDM [0]
MDQ [4]
LDP [3]
LAD [19]
GND
LCLK [2]
LBCTL
LAD [7]
LAD [6]
NC
26
MDQ [0]
MDQ [1]
LAD [25]
GND
LAD [22]
LAD [18]
LAD [16]
BVDD
LALE
LDP [0]
GND
GND
LDP [2]
LSYNC_ IN
LAD [21]
GND
LAD [15]
LAD [14]
GND
LAD [11]
LAD [9]
D
NC
IRQ [4]
PCI1_ AD [7]
GPOUT [4]
LCLK [0]
C
NC
NC
IRQ [1]
PCI1_ AD [6]
GPIN [3]
LAD [26]
B
NC
NC
NC
IRQ [2]
SD1_ TST_ CLK
LAD [23]
A
NC
NC
NC
GND
LAD [1]
LAD [24]
AVDD_ LSYNC_ OUT LBIU
NC
VDD
NC
NC
GND
MDQS [0]
GND
NC
GND
GND
XVDD_ SD1_TX XGND_ SD1_TX XGND_ SD1_TX XVDD_ SD1_TX XGND_ SD2_TX SRDS SRDS SRDS [3] [4] [6] [0] [1] SRDS SRDS
BVDD
GVDD
MVREF
NC
VDD
VDD
NC
MDQ [13]
28
NC
GND
GND
LGPL4
MDQ [8]
GND
VDD
VDD
16
LGPL0/ LGPL1/ /LGTA/ XGND_ SD1_TX XVDD_ SD1_TX XVDD_ SD1_TX XGND_ SD1_TX XVDD_ SD2_TX LSDA10 LSDWE LUPWAIT/ SRDS [1] [3] [4] [6] [0] SRDS SRDS SRDS SRDS LPBSE
24
27
GND
5
UART_ SOUT [0]
GVDD
MDQS [3]
XVDD_ XVDD_ CKSTP_ SRDS2 SRDS2 IN
UART_ SIN [0]
MECC [4]
17
4
UART_ SOUT [1]
MECC [5]
NC
XGND_ SRDS2
PCI1_ GNT [4]
GVDD
VDD
3
SD2_ TST_ CLK
SD2_ TST_ CLK
UART_ SIN [1]
MECC [1]
GND
SD2_ IMP_CAL _RX
PCI1_ IDSEL
GVDD
VDD
2
SD2_ PLL_ TPD
UART_ CTS [1]
MDQ [27]
GND
1
SVDD_ SGND_ SRDS2 SRDS2
PCI1_ GNT [0]
GND
VDD
SD2_ REF_ CLK
AH SD2_ PLL_ TPA
PCI1_ REQ [1]
XVDD_ MSRCID OVDD [3] [5] SRDS2
14
GND
AG
NC
SD2_ REF_ CLK
PCI1_ AD [15]
VDD
AF
SGND_ SD2_RX SD2_RX SGND_ SVDD_ SRDS2 SRDS2 SRDS2 [3] [3]
NC
NC
AB
SD2_ SGND_ SV DD_ SD2_RX SD2_RX SGND_ AGND_ AVDD_ IMP_CAL SRDS2 SRDS2 SRDS2 SRDS2 SRDS2 [2] [2] _TX
NC
NC
AA
NC
LAD [20]
LAD [17]
LDP [1]
LAD [13]
LAD [12]
LAD [10]
LAD [8]
E
F
G
H
J
K
L
NC
XGND_ SD1_TX XVDD_ SD1_TX XGND_ [5] [7] SRDS SRDS2 SRDS XVDD_ SD1_TX XGND_ SD1_TX XVDD_ [5] [7] SRDS SRDS SRDS2
SVDD_ SGND_ SGND_ SVDD_ SRDS SRDS SRDS SRDS
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SRDS [1] [3] SRDS SRDS
SD1_ SGND_ SD1_RX SVDD_ SD1_RX SGND_ IMP_CAL SRDS SRDS [3] [1] SRDS _RX
NC SD1_ PLL_ TPA
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SD2_RX SVDD_ GPOUT GPOUT [7] [6] SRDS [6] [4] SRDS SRDS2 SRDS2 [0]
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SRDS [0] [2] SRDS SRDS
SD1_ REF_ CLK
AGND_ SRDS
SGND_ SD1_RX SVDD_ SD1_RX SGND_ SRDS SRDS [2] [0] SRDS
SD1_ REF_ CLK
SD1_ PLL_ TPD
AVDD_ SRDS
U
V
W
M
N
P
R
T
SVDD_ SGND_ SGND_ SGND_ SGND_ IRQ[11] DMA_ SRDS SRDS SRDS2 DDONE3 SRDS SRDS
NC
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SRDS [5] [7] SRDS SRDS
IRQ[10] DMA_ DACK3
SD1_ SGND_ SD1_RX SVDD_ SD1_RX SGND_ IMP_CAL SRDS SRDS [7] [5] SRDS _TX
Y
AA
AB
AC
AD
AE
OVDD [17]
GPOUT [2]
TMS
27
TDO
TCK
TDI
28
AF
AG
AH
Figure 9. MPC8544E Ball Map
4.3
Pin Listings
A downloadable version of the pin list is available in the file AN3547SW.zip on Freescale.com.
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 18
Freescale Semiconductor
Table 7. Pin List—By Bus (continued)
Table 7. Pin List—By Bus Bus
PCI1_AD[31] PCI1_AD[30] PCI1_AD[29] PCI1_AD[28] PCI1_AD[27] PCI1_AD[26] PCI1_AD[25] PCI1_AD[24] PCI1_AD[23] PCI1_AD[22] PCI1_AD[21] PCI1_AD[20] PCI1_AD[19] PCI1_AD[18] PCI1_AD[17] PCI1_AD[16] PCI1_AD[15] PCI1_AD[14] PCI1_AD[13] PCI1_AD[12] PCI1_AD[11] PCI1_AD[10] PCI1_AD[9] PCI1_AD[8] PCI1_AD[7] PCI1_AD[6] PCI1_AD[5] PCI1_AD[4] PCI1_AD[3] PCI1_AD[2] PCI1_AD[1] PCI1_AD[0] PCI1_C_BE[3] PCI1_C_BE[2] PCI1_C_BE[1] PCI1_C_BE[0] PCI1_GNT[4] PCI1_GNT[3] PCI1_GNT[2] PCI1_GNT[1] PCI1_GNT[0] PCI1_IRDY PCI1_PAR PCI1_PERR PCI1_SERR PCI1_STOP
AE8 AD8 AF8 AH12 AG12 AB9 AC9 AE9 AD10 AE10 AC11 AB11 AB12 AC12 AF12 AE11 Y14 AE15 AC15 AB15 AA15 AD16 Y15 AB16 AF18 AE18 AC17 AE19 AD19 AB17 AB18 AA16 AC10 AE12 AA14 AD17 AE7 AG11 AH11 AC8 AE6 AF13 AB14 AE14 AC14 AA13
Bus
DDR SDRAM Memory Interface
Pin
PCI
PCI
Signal
Signal
Pin
PCI1_TRDY PCI1_REQ[4] PCI1_REQ[3] PCI1_REQ[2] PCI1_REQ[1] PCI1_REQ[0] PCI1_CLK PCI1_DEVSEL PCI1_FRAME PCI1_IDSEL MDQ[0] MDQ[1] MDQ[2] MDQ[3] MDQ[4] MDQ[5] MDQ[6] MDQ[7] MDQ[8] MDQ[9] MDQ[10] MDQ[11] MDQ[12] MDQ[13] MDQ[14] MDQ[15] MDQ[16] MDQ[17] MDQ[18] MDQ[19] MDQ[20] MDQ[21] MDQ[22] MDQ[23] MDQ[24] MDQ[25] MDQ[26] MDQ[27] MDQ[28] MDQ[29] MDQ[30] MDQ[31] MDQ[32] MDQ[33] MDQ[34] MDQ[35]
AD13 AF9 AG10 AH10 AD6 AB8 AH26 AC13 AD12 AG6 A26 B26 C22 D21 D25 B25 D22 E21 A24 A23 B20 A20 A25 B24 B21 A21 E19 D19 E16 C16 F19 F18 F17 D16 B18 A18 A15 B14 B19 A19 A16 B15 D1 F3 G1 H2
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
19
Table 7. Pin List—By Bus (continued) Bus
Table 7. Pin List—By Bus (continued) Pin
MDQ[36] MDQ[37] MDQ[38] MDQ[39] MDQ[40] MDQ[41] MDQ[42] MDQ[43] MDQ[44] MDQ[45] MDQ[46] MDQ[47] MDQ[48] MDQ[49] MDQ[50] MDQ[51] MDQ[52] MDQ[53] MDQ[54] MDQ[55] MDQ[56] MDQ[57] MDQ[58] MDQ[59] MDQ[60] MDQ[61] MDQ[62] MDQ[63] MECC[0] MECC[1] MECC[2] MECC[3] MECC[4] MECC[5] MECC[6] MECC[7] MDM[0] MDM[1] MDM[2] MDM[3] MDM[4] MDM[5] MDM[6] MDM[7] MDM[8] MDQS[0]
E4 G5 H3 J4 B2 C3 F2 G2 A2 B3 E1 F1 L5 L4 N3 P3 J3 K4 N4 P4 J1 K1 P1 R1 J2 K2 N1 R2 G12 D14 F11 C11 G14 F14 C13 D12 C25 B23 D18 B17 G4 C2 L3 L2 F13 D24
Bus
DDR SDRAM Memory Interface
DDR SDRAM Memory Interface
Signal
Signal
Pin
MDQS[1] MDQS[2] MDQS[3] MDQS[4] MDQS[5] MDQS[6] MDQS[7] MDQS[8] MDQS[0] MDQS[1] MDQS[2] MDQS[3] MDQS[4] MDQS[5] MDQS[6] MDQS[7] MDQS[8] MA[0] MA[1] MA[2] MA[3] MA[4] MA[5] MA[6] MA[7] MA[8] MA[9] MA[10] MA[11] MA[12] MA[13] MA[14] MA[15] MBA[0] MBA[1] MBA[2] MWE MCAS MRAS MCKE[0] MCKE[1] MCKE[2] MCKE[3] MCS[0] MCS[1] MCS[2]
B22 C18 A17 J5 C1 M4 M2 E13 C23 A22 E17 B16 K5 D2 M3 P2 D13 B7 G8 C8 A10 D9 C10 A11 F9 E9 B12 A5 A12 D11 F7 E10 F10 A4 B5 B13 B4 E7 C5 H10 K10 G10 H9 D3 H6 C4
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 20
Freescale Semiconductor
Table 7. Pin List—By Bus (continued) Bus
Table 7. Pin List—By Bus (continued)
DDR SDRAM Memory Interface
MCS[3] MCK[0] MCK[1] MCK[2] MCK[3] MCK[4] MCK[5] MCK[0] MCK[1] MCK[2] MCK[3] MCK[4] MCK[5] MODT[0] MODT[1] MODT[2] MODT[3] MDIC[0] MDIC[1] TEST_IN TEST_OUT LAD[0] LAD[1] LAD[2] LAD[3] LAD[4] LAD[5] LAD[6] LAD[7] LAD[8] LAD[9] LAD[10] LAD[11] LAD[12] LAD[13] LAD[14] LAD[15] LAD[16] LAD[17] LAD[18] LAD[19] LAD[20] LAD[21] LAD[22] LAD[23] LAD[24]
G6 A9 J11 J6 A8 J13 H8 B9 H11 K6 B8 H13 J8 E5 H7 E6 F6 H15 K15 A13 A6 K22 L21 L22 K23 K24 L24 L25 K25 L28 L27 K28 K27 J28 H28 H27 G27 G26 F28 F26 F25 E28 E27 E26 F24 E24
Bus
DMA
Pin
Local Bus Controller Interface
Local Bus Controller Interface
Signal
Signal
Pin
LAD[25] LAD[26] LAD[27] LAD[28] LAD[29] LAD[30] LAD[31] LDP[0] LDP[1] LDP[2] LDP[3] LA[27] LA[28] LA[29] LA[30] LA[31] LCS[0] LCS[1] LCS[2] LCS[3] LCS[4] LCS5/DMA_DREQ2 LCS6/DMA_DACK2 LCS7/DMA_DDONE2 LWE0/LBS0/LSDDQM[0] LWE1/LBS1/LSDDQM[1] LWE2/LBS2/LSDDQM[2] LWE3/LBS3/LSDDQM[3] LALE LBCTL LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LOE/LSDRAS LGPL3/LSDCAS LGPL4/LGTA/LUPWAIT/LPBSE LGPL5 LCKE LCLK[0] LCLK[1] LCLK[2] LSYNC_IN LSYNC_OUT DMA_DACK[0] DMA_DACK[1] DMA_DREQ[0] DMA_DREQ[1]
C26 G24 E23 G23 F22 G22 G21 K26 G28 B27 E25 L19 K16 K17 H17 G17 K18 G19 H19 H20 G16 H16 J16 L18 J22 H22 H23 H21 J26 J25 J20 K20 G20 H18 L20 K19 L17 H24 J24 H25 D27 D28 Y13 Y12 AA10 AA11
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
21
Table 7. Pin List—By Bus (continued) Bus DM A Gigabit Reference Clock
AA7 Y11 AH15 AG18 AG22 AF17 AD21 AF19 AG17 AF16 AC23 AC22 AC19 AG20 AE27 AE24 AD14 AC7 Y9 T2
TSEC1_RXD[7] TSEC1_RXD[6] TSEC1_RXD[5] TSEC1_RXD[4] TSEC1_RXD[3] TSEC1_RXD[2] TSEC1_RXD[1] TSEC1_RXD[0] TSEC1_TXD[7] TSEC1_TXD[6] TSEC1_TXD[5] TSEC1_TXD[4] TSEC1_TXD[3] TSEC1_TXD[2] TSEC1_TXD[1] TSEC1_TXD[0] TSEC1_COL TSEC1_CRS TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER TSEC1_TX_CLK TSEC1_TX_EN TSEC1_TX_ER
U10 U9 T10 T9 U8 T8 T7 T6 T5 U5 V5 V3 V2 V1 U2 U1 R5 T4 T1 V7 U7 R9 V6 U4 T3
SerDes1
DMA_DDONE[0] DMA_DDONE[1] UDE MCP IRQ[0] IRQ[1] IRQ[2] IRQ[3] IRQ[4] IRQ[5] IRQ[6] IRQ[7] IRQ[8] IRQ[9]/DMA_DREQ3 IRQ[10]/DMA_DACK3 IRQ[11]/DMA_DDONE3 IRQ_OUT EC_MDC EC_MDIO EC_GTX_CLK125
Bus
I2C Interface
Pin
DUART
Three-Speed Ethernet Controller (Gigabit Ethernet 1) Three-Speed Ethernet Controller (Gigabit Ethernet
Signal
Three-Speed Ethernet Controller (Gigabit Ethernet 3)
Programmable Interrupt Controller Ethernet
Table 7. Pin List—By Bus (continued) Signal
Pin
TSEC3_RXD[7] TSEC3_RXD[6] TSEC3_RXD[5] TSEC3_RXD[4] TSEC3_RXD[3] TSEC3_RXD[2] TSEC3_RXD[1] TSEC3_RXD[0] TSEC3_TXD[7] TSEC3_TXD[6] TSEC3_TXD[5] TSEC3_TXD[4] TSEC3_TXD[3] TSEC3_TXD[2] TSEC3_TXD[1] TSEC3_TXD[0] TSEC3_COL TSEC3_CRS TSEC3_GTX_CLK TSEC3_RX_CLK TSEC3_RX_DV TSEC3_RX_ER TSEC3_TX_CLK TSEC3_TX_EN TSEC3_TX_ER UART_CTS[0] UART_CTS[1] UART_RTS[0] UART_RTS[1] UART_SIN[0] UART_SIN[1] UART_SOUT[0] UART_SOUT[1] IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA SD1_RX[0] SD1_RX[1] SD1_RX[2] SD1_RX[3] SD1_RX[4] SD1_RX[5] SD1_RX[6] SD1_RX[7] SD1_RX[0]
P11 N11 M11 L11 R8 N10 N9 P10 M7 N7 P7 M8 L7 R6 P6 M6 M9 L9 R7 P9 P8 R11 L10 N6 L8 AH8 AF6 AG8 AG9 AG7 AH6 AH7 AF7 AG21 AH21 AG13 AG14 N28 P26 R28 T26 Y26 AA28 AB26 AC28 N27
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 22
Freescale Semiconductor
Table 7. Pin List—By Bus (continued) Bus
Table 7. Pin List—By Bus (continued)
System Control Debug Cloc k JTAG DFT
P25 R27 T25 Y25 AA27 AB25 AC27 M23 N21 P23 R21 U21 V23 W21 Y23 M22 N20 P22 R20 U20 V22 W20 Y22 V28 U28 U27 T22 T23 AD26 AD1 AB2 AD25 AC1 AA2 AA21 AC4 AA5 AA20 AB4 Y5 AG3 AE2 AF2 AG4 AF4
Ther mal Man age
SD1_RX[1] SD1_RX[2] SD1_RX[3] SD1_RX[4] SD1_RX[5] SD1_RX[6] SD1_RX[7] SD1_TX[0] SD1_TX[1] SD1_TX[2] SD1_TX[3] SD1_TX[4] SD1_TX[5] SD1_TX[6] SD1_TX[7] SD1_TX[0] SD1_TX[1] SD1_TX[2] SD1_TX[3] SD1_TX[4] SD1_TX[5] SD1_TX[6] SD1_TX[7] SD1_PLL_TPD SD1_REF_CLK SD1_REF_CLK SD1_TST_CLK SD1_TST_CLK SD2_RX[0] SD2_RX[2] SD2_RX[3] SD2_RX[0] SD2_RX[2] SD2_RX[3] SD2_TX[0] SD2_TX[2] SD2_TX[3] SD2_TX[0] SD2_TX[2] SD2_TX[3] SD2_PLL_TPD SD2_REF_CLK SD2_REF_CLK SD2_TST_CLK SD2_TST_CLK
Bus
General-Purpose Input
SerDes2
Pin
General-Purpose Output
SerDes1
Signal
Signal
Pin
GPOUT[0] GPOUT[1] GPOUT[2] GPOUT[3] GPOUT[4] GPOUT[5] GPOUT[6] GPOUT[7] GPIN[0] GPIN[1] GPIN[2] GPIN[3] GPIN[4] GPIN[5] GPIN[6] GPIN[7] HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT TRIG_IN TRIG_OUT/READY/QUIESCE MSRCID[0] MSRCID[1] MSRCID[2] MSRCID[3] MSRCID[4] MDVAL CLK_OUT RTC SYSCLK TCK TDI TDO TMS TRST L1_TSTCLK L2_TSTCLK LSSD_MODE TEST_SEL TEMP_ANODE TEMP_CATHODE
AF22 AH23 AG27 AH25 AF21 AF25 AG26 AF26 AH24 AG24 AD23 AE21 AD22 AF23 AG25 AE20 AG16 AG15 AG19 AH5 AA12 AC5 AB5 Y7 W9 AA9 AB6 AD5 Y8 AE16 AF15 AH16 AG28 AH28 AF28 AH27 AH22 AC20 AE17 AH19 AH13 Y3 AA3
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
23
Table 7. Pin List—By Bus (continued) Bus
Table 7. Pin List—By Bus (continued)
Power Management
Pin
ASLEEP
AH17
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
D5 M10 F4 D26 D23 C12 C15 E20 D8 B10 E3 J14 K21 F8 A3 F16 E12 E15 D17 L1 F21 H1 G13 G15 G18 C6 A14 A7 G25 H4 C20 J12 J15 J17 F27 M5 J27 K11 L26
Bus
Power and Ground Signals
Power and Ground Signals
Signal
Signal
Pin
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND OVDD OVDD OVDD OVDD OVDD
K7 K8 L12 L15 M14 M16 M18 N13 N15 N17 N2 P5 P14 P16 P18 R13 R15 R17 T14 T16 T18 U13 U15 U17 AA8 U6 Y10 AC21 AA17 AC16 V4 AD7 AD18 AE23 AF11 AF14 AG23 AH9 A27 B28 C27 Y16 AB7 AB10 AB13 AC6
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 24
Freescale Semiconductor
Table 7. Pin List—By Bus (continued) Bus
Table 7. Pin List—By Bus (continued) Pin
OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD LVDD LVDD TVDD TVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD
AC18 AD9 AD11 AE13 AD15 AD20 AE5 AE22 AF10 AF20 AF24 AF27 R4 U3 N8 R10 B1 B11 C7 C9 C14 C17 D4 D6 R3 D15 E2 E8 C24 E18 F5 E14 C21 G3 G7 G9 G11 H5 H12 E22 F15 J10 K3 K12 K14 H14
Bus
Power and Ground Signals
Power and Ground Signals
Signal
Signal
Pin
GVDD GVDD GVDD GVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS
D20 E11 M1 N5 L23 J18 J19 F20 F23 H26 J21 J23 L16 L14 M13 M15 M17 N12 N14 N16 N18 P13 P15 P17 R12 R14 R16 R18 T13 T15 T17 U12 U14 U16 U18 M27 N25 P28 R24 R26 T24 T27 U25 W24 W26 Y24
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
25
Table 7. Pin List—By Bus (continued) Bus
Table 7. Pin List—By Bus (continued)
Y27 AA25 AB28 AD27 AB1 AC26 AD2 AE26 AG2 M21 N23 P20 R22 T20 U23 V21 W22 Y20 Y6 AA6 AA23 AF5 AG5 M20 M24 N22 P21 R23 T21 U22 V20 W23 Y21 Y4 AA4 AA22 AD4 AE4 AH4 M28 N26 P24 P27 R25 T28 U24
No Connect Pins
SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS2 SVDD_SRDS2 SVDD_SRDS2 SVDD_SRDS2 SVDD_SRDS2 XVDD_SRDS XVDD_SRDS XVDD_SRDS XVDD_SRDS XVDD_SRDS XVDD_SRDS XVDD_SRDS XVDD_SRDS XVDD_SRDS XVDD_SRDS2 XVDD_SRDS2 XVDD_SRDS2 XVDD_SRDS2 XVDD_SRDS2 XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS2 XGND_SRDS2 XGND_SRDS2 XGND_SRDS2 XGND_SRDS2 XGND_SRDS2 SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS
Bus
Analog Signals
Pin
Power and Ground Signals
Power and Ground Signals
Signal
Signal
Pin
SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS AGND_SRDS SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 AGND_SRDS2 AVDD_LBIU AVDD_PCI1 AVDD_CORE AVDD_PLAT AVDD_SRDS AVDD_SRDS2 SENSEVDD SENSEVSS MVREF SD1_IMP_CAL_RX SD1_IMP_CAL_TX SD1_PLL_TPA SD2_IMP_CAL_RX SD2_IMP_CAL_TX SD2_PLL_TPA NC NC NC NC NC NC
U26 V24 W25 Y28 AA24 AA26 AB24 AB27 AC24 AD28 V27 Y2 AA1 AB3 AC2 AC3 AC25 AD3 AD24 AE3 AE1 AE25 AF3 AH2 AF1 C28 AH20 AH14 AH18 W28 AG1 W11 W10 A28 M26 AE28 V26 AH3 Y1 AH1 C19 D7 D10 K13 L6 K9
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 26
Freescale Semiconductor
Table 7. Pin List—By Bus (continued) Bus
Table 7. Pin List—By Bus (continued) Pin
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
B6 F12 J7 M19 M25 N19 N24 P19 R19 AB19 T12 W3 M12 W5 P12 T19 W1 W7 L13 U19 W4 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W2 W6 W8 T11 U11 W12 W13 W14 W15 W16 W17 W18 W19
Bus
No Connect Pins
No Connect Pins
Signal
Signal
Pin
NC NC NC NC NC NC NC NC NC NC NC NC
W27 V25 Y17 Y18 Y19 AA18 AA19 AB20 AB21 AB22 AB23 J9
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
27
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal Signal
Pin
Signal
Pin
AGND_SRDS
V27
GND
D23
AGND_SRDS2
AF1
GND
C12
ASLEEP
AH17
GND
C15
AVDD_CORE
AH14
GND
E20
AVDD_LBIU
C28
GND
D8
AVDD_PCI1
AH20
GND
B10
AVDD_PLAT
AH18
GND
E3
AVDD_SRDS
W28
GND
J14
AVDD_SRDS2
AG1
GND
K21
BVDD
L23
GND
F8
BVDD
J18
GND
A3
BVDD
J19
GND
F16
BVDD
F20
GND
E12
BVDD
F23
GND
E15
BVDD
H26
GND
D17
BVDD
J21
GND
L1
BVDD
J23
GND
F21
CKSTP_IN
AH5
GND
H1
CKSTP_OUT
AA12
GND
G13
CLK_OUT
AE16
GND
G15
DMA_DACK[0]
Y13
GND
G18
DMA_DACK[1]
Y12
GND
C6
DMA_DDONE[0]
AA7
GND
A14
DMA_DDONE[1]
Y11
GND
A7
DMA_DREQ[0]
AA10
GND
G25
DMA_DREQ[1]
AA11
GND
H4
EC_GTX_CLK125
T2
GND
C20
EC_MDC
AC7
GND
J12
EC_MDIO
Y9
GND
J15
GND
D5
GND
J17
GND
M10
GND
F27
GND
F4
GND
M5
GND
D26
GND
J27
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 28
Freescale Semiconductor
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
GND
K11
GND
AD7
GND
L26
GND
AD18
GND
K7
GND
AE23
GND
K8
GND
AF11
GND
L12
GND
AF14
GND
L15
GND
AG23
GND
M14
GND
AH9
GND
M16
GND
A27
GND
M18
GND
B28
GND
N13
GND
C27
GND
N15
GPIN[0]
AH24
GND
N17
GPIN[1]
AG24
GND
N2
GPIN[2]
AD23
GND
P5
GPIN[3]
AE21
GND
P14
GPIN[4]
AD22
GND
P16
GPIN[5]
AF23
GND
P18
GPIN[6]
AG25
GND
R13
GPIN[7]
AE20
GND
R15
GPOUT[0]
AF22
GND
R17
GPOUT[1]
AH23
GND
T14
GPOUT[2]
AG27
GND
T16
GPOUT[3]
AH25
GND
T18
GPOUT[4]
AF21
GND
U13
GPOUT[5]
AF25
GND
U15
GPOUT[6]
AG26
GND
U17
GPOUT[7]
AF26
GND
AA8
GVDD
B1
GND
U6
GVDD
B11
GND
Y10
GVDD
C7
GND
AC21
GVDD
C9
GND
AA17
GVDD
C14
GND
AC16
GVDD
C17
GND
V4
GVDD
D4
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
29
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
GVDD
D6
IRQ[0]
AG22
GVDD
R3
IRQ[1]
AF17
GVDD
D15
IRQ[10]/DMA_DACK3
AE27
GVDD
E2
IRQ[11]/DMA_DDONE3
AE24
GVDD
E8
IRQ[2]
AD21
GVDD
C24
IRQ[3]
AF19
GVDD
E18
IRQ[4]
AG17
GVDD
F5
IRQ[5]
AF16
GVDD
E14
IRQ[6]
AC23
GVDD
C21
IRQ[7]
AC22
GVDD
G3
IRQ[8]
AC19
GVDD
G7
IRQ[9]/DMA_DREQ3
AG20
GVDD
G9
IRQ_OUT
AD14
GVDD
G11
L1_TSTCLK
AC20
GVDD
H5
L2_TSTCLK
AE17
GVDD
H12
LA[27]
L19
GVDD
E22
LA[28]
K16
GVDD
F15
LA[29]
K17
GVDD
J10
LA[30]
H17
GVDD
K3
LA[31]
G17
GVDD
K12
LAD[0]
K22
GVDD
K14
LAD[1]
L21
GVDD
H14
LAD[10]
K28
GVDD
D20
LAD[11]
K27
GVDD
E11
LAD[12]
J28
GVDD
M1
LAD[13]
H28
GVDD
N5
LAD[14]
H27
HRESET
AG16
LAD[15]
G27
HRESET_REQ
AG15
LAD[16]
G26
IIC1_SCL
AG21
LAD[17]
F28
IIC1_SDA
AH21
LAD[18]
F26
IIC2_SCL
AG13
LAD[19]
F25
IIC2_SDA
AG14
LAD[2]
L22
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 30
Freescale Semiconductor
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
LAD[20]
E28
LDP[0]
K26
LAD[21]
E27
LDP[1]
G28
LAD[22]
E26
LDP[2]
B27
LAD[23]
F24
LDP[3]
E25
LAD[24]
E24
LGPL0/LSDA10
J20
LAD[25]
C26
LGPL1/LSDWE
K20
LAD[26]
G24
LGPL2/LOE/LSDRAS
G20
LAD[27]
E23
LGPL3/LSDCAS
H18
LAD[28]
G23
LGPL4/LGTA/LUPWAIT/LPBSE
L20
LAD[29]
F22
LGPL5
K19
LAD[3]
K23
LSSD_MODE
AH19
LAD[30]
G22
LSYNC_IN
D27
LAD[31]
G21
LSYNC_OUT
D28
LAD[4]
K24
LVDD
R4
LAD[5]
L24
LVDD
U3
LAD[6]
L25
LWE0/LBS0/LSDDQM[0]
J22
LAD[7]
K25
LWE1/LBS1/LSDDQM[1]
H22
LAD[8]
L28
LWE2/LBS2/LSDDQM[2]
H23
LAD[9]
L27
LWE3/LBS3/LSDDQM[3]
H21
LALE
J26
MA[0]
B7
LBCTL
J25
MA[1]
G8
LCKE
L17
MA[10]
A5
LCLK[0]
H24
MA[11]
A12
LCLK[1]
J24
MA[12]
D11
LCLK[2]
H25
MA[13]
F7
LCS[0]
K18
MA[14]
E10
LCS[1]
G19
MA[15]
F10
LCS[2]
H19
MA[2]
C8
LCS[3]
H20
MA[3]
A10
LCS[4]
G16
MA[4]
D9
LCS5/DMA_DREQ2
H16
MA[5]
C10
LCS6/DMA_DACK2
J16
MA[6]
A11
LCS7/DMA_DDONE2
L18
MA[7]
F9
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
31
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
MA[8]
E9
MDM[4]
G4
MA[9]
B12
MDM[5]
C2
MBA[0]
A4
MDM[6]
L3
MBA[1]
B5
MDM[7]
L2
MBA[2]
B13
MDM[8]
F13
MCAS
E7
MDQ[0]
A26
MCK[0]
A9
MDQ[1]
B26
MCK[0]
B9
MDQ[10]
B20
MCK[1]
J11
MDQ[11]
A20
MCK[1]
H11
MDQ[12]
A25
MCK[2]
J6
MDQ[13]
B24
MCK[2]
K6
MDQ[14]
B21
MCK[3]
A8
MDQ[15]
A21
MCK[3]
B8
MDQ[16]
E19
MCK[4]
J13
MDQ[17]
D19
MCK[4]
H13
MDQ[18]
E16
MCK[5]
H8
MDQ[19]
C16
MCK[5]
J8
MDQ[2]
C22
MCKE[0]
H10
MDQ[20]
F19
MCKE[1]
K10
MDQ[21]
F18
MCKE[2]
G10
MDQ[22]
F17
MCKE[3]
H9
MDQ[23]
D16
MCP
AG18
MDQ[24]
B18
MCS[0]
D3
MDQ[25]
A18
MCS[1]
H6
MDQ[26]
A15
MCS[2]
C4
MDQ[27]
B14
MCS[3]
G6
MDQ[28]
B19
MDIC[0]
H15
MDQ[29]
A19
MDIC[1]
K15
MDQ[3]
D21
MDM[0]
C25
MDQ[30]
A16
MDM[1]
B23
MDQ[31]
B15
MDM[2]
D18
MDQ[32]
D1
MDM[3]
B17
MDQ[33]
F3
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 32
Freescale Semiconductor
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
MDQ[34]
G1
MDQ[7]
E21
MDQ[35]
H2
MDQ[8]
A24
MDQ[36]
E4
MDQ[9]
A23
MDQ[37]
G5
MDQS[0]
C23
MDQ[38]
H3
MDQS[0]
D24
MDQ[39]
J4
MDQS[1]
A22
MDQ[4]
D25
MDQS[1]
B22
MDQ[40]
B2
MDQS[2]
E17
MDQ[41]
C3
MDQS[2]
C18
MDQ[42]
F2
MDQS[3]
B16
MDQ[43]
G2
MDQS[3]
A17
MDQ[44]
A2
MDQS[4]
K5
MDQ[45]
B3
MDQS[4]
J5
MDQ[46]
E1
MDQS[5]
D2
MDQ[47]
F1
MDQS[5]
C1
MDQ[48]
L5
MDQS[6]
M3
MDQ[49]
L4
MDQS[6]
M4
MDQ[5]
B25
MDQS[7]
P2
MDQ[50]
N3
MDQS[7]
M2
MDQ[51]
P3
MDQS[8]
D13
MDQ[52]
J3
MDQS[8]
E13
MDQ[53]
K4
MDVAL
Y8
MDQ[54]
N4
MECC[0]
G12
MDQ[55]
P4
MECC[1]
D14
MDQ[56]
J1
MECC[2]
F11
MDQ[57]
K1
MECC[3]
C11
MDQ[58]
P1
MECC[4]
G14
MDQ[59]
R1
MECC[5]
F14
MDQ[6]
D22
MECC[6]
C13
MDQ[60]
J2
MECC[7]
D12
MDQ[61]
K2
MODT[0]
E5
MDQ[62]
N1
MODT[1]
H7
MDQ[63]
R2
MODT[2]
E6
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
33
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
MODT[3]
F6
NC
L13
MRAS
C5
NC
U19
MSRCID[0]
Y7
NC
W4
MSRCID[1]
W9
NC
V8
MSRCID[2]
AA9
NC
V9
MSRCID[3]
AB6
NC
V10
MSRCID[4]
AD5
NC
V11
MVREF
A28
NC
V12
MWE
B4
NC
V13
NC
C19
NC
V14
NC
D7
NC
V15
NC
D10
NC
V16
NC
K13
NC
V17
NC
L6
NC
V18
NC
K9
NC
V19
NC
B6
NC
W2
NC
F12
NC
W6
NC
J7
NC
W8
NC
M19
NC
T11
NC
M25
NC
U11
NC
N19
NC
W12
NC
N24
NC
W13
NC
P19
NC
W14
NC
R19
NC
W15
NC
AB19
NC
W16
NC
T12
NC
W17
NC
W3
NC
W18
NC
M12
NC
W19
NC
W5
NC
W27
NC
P12
NC
V25
NC
T19
NC
Y17
NC
W1
NC
Y18
NC
W7
NC
Y19
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 34
Freescale Semiconductor
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
NC
AA18
PCI1_AD[17]
AF12
NC
AA19
PCI1_AD[18]
AC12
NC
AB20
PCI1_AD[19]
AB12
NC
AB21
PCI1_AD[2]
AB17
NC
AB22
PCI1_AD[20]
AB11
NC
AB23
PCI1_AD[21]
AC11
NC
J9
PCI1_AD[22]
AE10
OVDD
Y16
PCI1_AD[23]
AD10
OVDD
AB7
PCI1_AD[24]
AE9
OVDD
AB10
PCI1_AD[25]
AC9
OVDD
AB13
PCI1_AD[26]
AB9
OVDD
AC6
PCI1_AD[27]
AG12
OVDD
AC18
PCI1_AD[28]
AH12
OVDD
AD9
PCI1_AD[29]
AF8
OVDD
AD11
PCI1_AD[3]
AD19
OVDD
AE13
PCI1_AD[30]
AD8
OVDD
AD15
PCI1_AD[31]
AE8
OVDD
AD20
PCI1_AD[4]
AE19
OVDD
AE5
PCI1_AD[5]
AC17
OVDD
AE22
PCI1_AD[6]
AE18
OVDD
AF10
PCI1_AD[7]
AF18
OVDD
AF20
PCI1_AD[8]
AB16
OVDD
AF24
PCI1_AD[9]
Y15
OVDD
AF27
PCI1_C_BE[0]
AD17
PCI1_AD[0]
AA16
PCI1_C_BE[1]
AA14
PCI1_AD[1]
AB18
PCI1_C_BE[2]
AE12
PCI1_AD[10]
AD16
PCI1_C_BE[3]
AC10
PCI1_AD[11]
AA15
PCI1_CLK
AH26
PCI1_AD[12]
AB15
PCI1_DEVSEL
AC13
PCI1_AD[13]
AC15
PCI1_FRAME
AD12
PCI1_AD[14]
AE15
PCI1_GNT[0]
AE6
PCI1_AD[15]
Y14
PCI1_GNT[1]
AC8
PCI1_AD[16]
AE11
PCI1_GNT[2]
AH11
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
35
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
PCI1_GNT[3]
AG11
SD1_RX[6]
AB26
PCI1_GNT[4]
AE7
SD1_RX[6]
AB25
PCI1_IDSEL
AG6
SD1_RX[7]
AC28
PCI1_IRDY
AF13
SD1_RX[7]
AC27
PCI1_PAR
AB14
SD1_TST_CLK
T22
PCI1_PERR
AE14
SD1_TST_CLK
T23
PCI1_REQ[0]
AB8
SD1_TX[0]
M23
PCI1_REQ[1]
AD6
SD1_TX[0]
M22
PCI1_REQ[2]
AH10
SD1_TX[1]
N21
PCI1_REQ[3]
AG10
SD1_TX[1]
N20
PCI1_REQ[4]
AF9
SD1_TX[2]
P23
PCI1_SERR
AC14
SD1_TX[2]
P22
PCI1_STOP
AA13
SD1_TX[3]
R21
PCI1_TRDY
AD13
SD1_TX[3]
R20
RTC
AF15
SD1_TX[4]
U21
SD1_IMP_CAL_RX
M26
SD1_TX[4]
U20
SD1_IMP_CAL_TX
AE28
SD1_TX[5]
V23
SD1_PLL_TPA
V26
SD1_TX[5]
V22
SD1_PLL_TPD
V28
SD1_TX[6]
W21
SD1_REF_CLK
U28
SD1_TX[6]
W20
SD1_REF_CLK
U27
SD1_TX[7]
Y23
SD1_RX[0]
N28
SD1_TX[7]
Y22
SD1_RX[0]
N27
SD2_IMP_CAL_RX
AH3
SD1_RX[1]
P26
SD2_IMP_CAL_TX
Y1
SD1_RX[1]
P25
SD2_PLL_TPA
AH1
SD1_RX[2]
R28
SD2_PLL_TPD
AG3
SD1_RX[2]
R27
SD2_REF_CLK
AE2
SD1_RX[3]
T26
SD2_REF_CLK
AF2
SD1_RX[3]
T25
SD2_RX[0]
AD26
SD1_RX[4]
Y26
SD2_RX[0]
AD25
SD1_RX[4]
Y25
SD2_RX[2]
AD1
SD1_RX[5]
AA28
SD2_RX[2]
AC1
SD1_RX[5]
AA27
SD2_RX[3]
AB2
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 36
Freescale Semiconductor
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
SD2_RX[3]
AA2
SGND_SRDS2
AC25
SD2_TST_CLK
AG4
SGND_SRDS2
AD3
SD2_TST_CLK
AF4
SGND_SRDS2
AD24
SD2_TX[0]
AA21
SGND_SRDS2
AE3
SD2_TX[0]
AA20
SGND_SRDS2
AE1
SD2_TX[2]
AC4
SGND_SRDS2
AE25
SD2_TX[2]
AB4
SGND_SRDS2
AF3
SD2_TX[3]
AA5
SGND_SRDS2
AH2
SD2_TX[3]
Y5
SRESET
AG19
SENSEVDD
W11
SVDD_SRDS
M27
SENSEVSS
W10
SVDD_SRDS
N25
SGND_SRDS
M28
SVDD_SRDS
P28
SGND_SRDS
N26
SVDD_SRDS
R24
SGND_SRDS
P24
SVDD_SRDS
R26
SGND_SRDS
P27
SVDD_SRDS
T24
SGND_SRDS
R25
SVDD_SRDS
T27
SGND_SRDS
T28
SVDD_SRDS
U25
SGND_SRDS
U24
SVDD_SRDS
W24
SGND_SRDS
U26
SVDD_SRDS
W26
SGND_SRDS
V24
SVDD_SRDS
Y24
SGND_SRDS
W25
SVDD_SRDS
Y27
SGND_SRDS
Y28
SVDD_SRDS
AA25
SGND_SRDS
AA24
SVDD_SRDS
AB28
SGND_SRDS
AA26
SVDD_SRDS
AD27
SGND_SRDS
AB24
SVDD_SRDS2
AB1
SGND_SRDS
AB27
SVDD_SRDS2
AC26
SGND_SRDS
AC24
SVDD_SRDS2
AD2
SGND_SRDS
AD28
SVDD_SRDS2
AE26
SGND_SRDS2
Y2
SVDD_SRDS2
AG2
SGND_SRDS2
AA1
SYSCLK
AH16
SGND_SRDS2
AB3
TCK
AG28
SGND_SRDS2
AC2
TDI
AH28
SGND_SRDS2
AC3
TDO
AF28
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
37
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
TEMP_ANODE
Y3
TSEC1_TXD[7]
T5
TEMP_CATHODE
AA3
TSEC3_COL
M9
TEST_IN
A13
TSEC3_CRS
L9
TEST_OUT
A6
TSEC3_GTX_CLK
R7
TEST_SEL
AH13
TSEC3_RX_CLK
P9
TMS
AH27
TSEC3_RX_DV
P8
TRIG_IN
AC5
TSEC3_RX_ER
R11
TRIG_OUT/READY/QUIESCE
AB5
TSEC3_RXD[0]
P10
TRST
AH22
TSEC3_RXD[1]
N9
TSEC1_COL
R5
TSEC3_RXD[2]
N10
TSEC1_CRS
T4
TSEC3_RXD[3]
R8
TSEC1_GTX_CLK
T1
TSEC3_RXD[4]
L11
TSEC1_RX_CLK
V7
TSEC3_RXD[5]
M11
TSEC1_RX_DV
U7
TSEC3_RXD[6]
N11
TSEC1_RX_ER
R9
TSEC3_RXD[7]
P11
TSEC1_RXD[0]
T6
TSEC3_TX_CLK
L10
TSEC1_RXD[1]
T7
TSEC3_TX_EN
N6
TSEC1_RXD[2]
T8
TSEC3_TX_ER
L8
TSEC1_RXD[3]
U8
TSEC3_TXD[0]
M6
TSEC1_RXD[4]
T9
TSEC3_TXD[1]
P6
TSEC1_RXD[5]
T10
TSEC3_TXD[2]
R6
TSEC1_RXD[6]
U9
TSEC3_TXD[3]
L7
TSEC1_RXD[7]
U10
TSEC3_TXD[4]
M8
TSEC1_TX_CLK
V6
TSEC3_TXD[5]
P7
TSEC1_TX_EN
U4
TSEC3_TXD[6]
N7
TSEC1_TX_ER
T3
TSEC3_TXD[7]
M7
TSEC1_TXD[0]
U1
TVDD
N8
TSEC1_TXD[1]
U2
TVDD
R10
TSEC1_TXD[2]
V1
UART_CTS[0]
AH8
TSEC1_TXD[3]
V2
UART_CTS[1]
AF6
TSEC1_TXD[4]
V3
UART_RTS[0]
AG8
TSEC1_TXD[5]
V5
UART_RTS[1]
AG9
TSEC1_TXD[6]
U5
UART_SIN[0]
AG7
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 38
Freescale Semiconductor
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
UART_SIN[1]
AH6
XGND_SRDS
U22
UART_SOUT[0]
AH7
XGND_SRDS
V20
UART_SOUT[1]
AF7
XGND_SRDS
W23
UDE
AH15
XGND_SRDS
Y21
VDD
L16
XGND_SRDS2
Y4
VDD
L14
XGND_SRDS2
AA4
VDD
M13
XGND_SRDS2
AA22
VDD
M15
XGND_SRDS2
AD4
VDD
M17
XGND_SRDS2
AE4
VDD
N12
XGND_SRDS2
AH4
VDD
N14
XVDD_SRDS
M21
VDD
N16
XVDD_SRDS
N23
VDD
N18
XVDD_SRDS
P20
VDD
P13
XVDD_SRDS
R22
VDD
P15
XVDD_SRDS
T20
VDD
P17
XVDD_SRDS
U23
VDD
R12
XVDD_SRDS
V21
VDD
R14
XVDD_SRDS
W22
VDD
R16
XVDD_SRDS
Y20
VDD
R18
XVDD_SRDS2
Y6
VDD
T13
XVDD_SRDS2
AA6
VDD
T15
XVDD_SRDS2
AA23
VDD
T17
XVDD_SRDS2
AF5
VDD
U12
XVDD_SRDS2
AG5
VDD
U14
VDD
U16
VDD
U18
XGND_SRDS
M20
XGND_SRDS
M24
XGND_SRDS
N22
XGND_SRDS
P21
XGND_SRDS
R23
XGND_SRDS
T21
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
39
Table 9. Pin List—By Pin Number
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
MDQ[44]
A2
MA[0]
B7
GND
A3
MCK[3]
B8
MBA[0]
A4
MCK[0]
B9
MA[10]
A5
GND
B10
TEST_OUT
A6
GVDD
B11
GND
A7
MA[9]
B12
MCK[3]
A8
MBA[2]
B13
MCK[0]
A9
MDQ[27]
B14
MA[3]
A10
MDQ[31]
B15
MA[6]
A11
MDQS[3]
B16
MA[11]
A12
MDM[3]
B17
TEST_IN
A13
MDQ[24]
B18
GND
A14
MDQ[28]
B19
MDQ[26]
A15
MDQ[10]
B20
MDQ[30]
A16
MDQ[14]
B21
MDQS[3]
A17
MDQS[1]
B22
MDQ[25]
A18
MDM[1]
B23
MDQ[29]
A19
MDQ[13]
B24
MDQ[11]
A20
MDQ[5]
B25
MDQ[15]
A21
MDQ[1]
B26
MDQS[1]
A22
LDP[2]
B27
MDQ[9]
A23
GND
B28
MDQ[8]
A24
MDQS[5]
C1
MDQ[12]
A25
MDM[5]
C2
MDQ[0]
A26
MDQ[41]
C3
GND
A27
MCS[2]
C4
MVREF
A28
MRAS
C5
GVDD
B1
GND
C6
MDQ[40]
B2
GVDD
C7
MDQ[45]
B3
MA[2]
C8
MWE
B4
GVDD
C9
MBA[1]
B5
MA[5]
C10
NC
B6
MECC[3]
C11
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 40
Freescale Semiconductor
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
GND
C12
GND
D17
MECC[6]
C13
MDM[2]
D18
GVDD
C14
MDQ[17]
D19
GND
C15
GVDD
D20
MDQ[19]
C16
MDQ[3]
D21
GVDD
C17
MDQ[6]
D22
MDQS[2]
C18
GND
D23
NC
C19
MDQS[0]
D24
GND
C20
MDQ[4]
D25
GVDD
C21
GND
D26
MDQ[2]
C22
LSYNC_IN
D27
MDQS[0]
C23
LSYNC_OUT
D28
GVDD
C24
MDQ[46]
E1
MDM[0]
C25
GVDD
E2
LAD[25]
C26
GND
E3
GND
C27
MDQ[36]
E4
AVDD_LBIU
C28
MODT[0]
E5
MDQ[32]
D1
MODT[2]
E6
MDQS[5]
D2
MCAS
E7
MCS[0]
D3
GVDD
E8
GVDD
D4
MA[8]
E9
GND
D5
MA[14]
E10
GVDD
D6
GVDD
E11
NC
D7
GND
E12
GND
D8
MDQS[8]
E13
MA[4]
D9
GVDD
E14
NC
D10
GND
E15
MA[12]
D11
MDQ[18]
E16
MECC[7]
D12
MDQS[2]
E17
MDQS[8]
D13
GVDD
E18
MECC[1]
D14
MDQ[16]
E19
GVDD
D15
GND
E20
MDQ[23]
D16
MDQ[7]
E21
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
41
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
GVDD
E22
GND
F27
LAD[27]
E23
LAD[17]
F28
LAD[24]
E24
MDQ[34]
G1
LDP[3]
E25
MDQ[43]
G2
LAD[22]
E26
GVDD
G3
LAD[21]
E27
MDM[4]
G4
LAD[20]
E28
MDQ[37]
G5
MDQ[47]
F1
MCS[3]
G6
MDQ[42]
F2
GVDD
G7
MDQ[33]
F3
MA[1]
G8
GND
F4
GVDD
G9
GVDD
F5
MCKE[2]
G10
MODT[3]
F6
GVDD
G11
MA[13]
F7
MECC[0]
G12
GND
F8
GND
G13
MA[7]
F9
MECC[4]
G14
MA[15]
F10
GND
G15
MECC[2]
F11
LCS[4]
G16
NC
F12
LA[31]
G17
MDM[8]
F13
GND
G18
MECC[5]
F14
LCS[1]
G19
GVDD
F15
LGPL2/LOE/LSDRAS
G20
GND
F16
LAD[31]
G21
MDQ[22]
F17
LAD[30]
G22
MDQ[21]
F18
LAD[28]
G23
MDQ[20]
F19
LAD[26]
G24
BVDD
F20
GND
G25
GND
F21
LAD[16]
G26
LAD[29]
F22
LAD[15]
G27
BVDD
F23
LDP[1]
G28
LAD[23]
F24
GND
H1
LAD[19]
F25
MDQ[35]
H2
LAD[18]
F26
MDQ[38]
H3
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 42
Freescale Semiconductor
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
GND
H4
NC
J9
GVDD
H5
GVDD
J10
MCS[1]
H6
MCK[1]
J11
MODT[1]
H7
GND
J12
MCK[5]
H8
MCK[4]
J13
MCKE[3]
H9
GND
J14
MCKE[0]
H10
GND
J15
MCK[1]
H11
LCS6/DMA_DACK2
J16
GVDD
H12
GND
J17
MCK[4]
H13
BVDD
J18
GVDD
H14
BVDD
J19
MDIC[0]
H15
LGPL0/LSDA10
J20
LCS5/DMA_DREQ2
H16
BVDD
J21
LA[30]
H17
LWE0/LBS0/LSDDQM[0]
J22
LGPL3/LSDCAS
H18
BVDD
J23
LCS[2]
H19
LCLK[1]
J24
LCS[3]
H20
LBCTL
J25
LWE3/LBS3/LSDDQM[3]
H21
LALE
J26
LWE1/LBS1/LSDDQM[1]
H22
GND
J27
LWE2/LBS2/LSDDQM[2]
H23
LAD[12]
J28
LCLK[0]
H24
MDQ[57]
K1
LCLK[2]
H25
MDQ[61]
K2
BVDD
H26
GVDD
K3
LAD[14]
H27
MDQ[53]
K4
LAD[13]
H28
MDQS[4]
K5
MDQ[56]
J1
MCK[2]
K6
MDQ[60]
J2
GND
K7
MDQ[52]
J3
GND
K8
MDQ[39]
J4
NC
K9
MDQS[4]
J5
MCKE[1]
K10
MCK[2]
J6
GND
K11
NC
J7
GVDD
K12
MCK[5]
J8
NC
K13
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
43
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
GVDD
K14
LA[27]
L19
MDIC[1]
K15
LGPL4/LGTA/LUPWAIT/LPBSE
L20
LA[28]
K16
LAD[1]
L21
LA[29]
K17
LAD[2]
L22
LCS[0]
K18
BVDD
L23
LGPL5
K19
LAD[5]
L24
LGPL1/LSDWE
K20
LAD[6]
L25
GND
K21
GND
L26
LAD[0]
K22
LAD[9]
L27
LAD[3]
K23
LAD[8]
L28
LAD[4]
K24
GVDD
M1
LAD[7]
K25
MDQS[7]
M2
LDP[0]
K26
MDQS[6]
M3
LAD[11]
K27
MDQS[6]
M4
LAD[10]
K28
GND
M5
GND
L1
TSEC3_TXD[0]
M6
MDM[7]
L2
TSEC3_TXD[7]
M7
MDM[6]
L3
TSEC3_TXD[4]
M8
MDQ[49]
L4
TSEC3_COL
M9
MDQ[48]
L5
GND
M10
NC
L6
TSEC3_RXD[5]
M11
TSEC3_TXD[3]
L7
NC
M12
TSEC3_TX_ER
L8
VDD
M13
TSEC3_CRS
L9
GND
M14
TSEC3_TX_CLK
L10
VDD
M15
TSEC3_RXD[4]
L11
GND
M16
GND
L12
VDD
M17
NC
L13
GND
M18
VDD
L14
NC
M19
GND
L15
XGND_SRDS
M20
VDD
L16
XVDD_SRDS
M21
LCKE
L17
SD1_TX[0]
M22
LCS7/DMA_DDONE2
L18
SD1_TX[0]
M23
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 44
Freescale Semiconductor
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
XGND_SRDS
M24
MDQ[58]
P1
NC
M25
MDQS[7]
P2
SD1_IMP_CAL_RX
M26
MDQ[51]
P3
SVDD_SRDS
M27
MDQ[55]
P4
SGND_SRDS
M28
GND
P5
MDQ[62]
N1
TSEC3_TXD[1]
P6
GND
N2
TSEC3_TXD[5]
P7
MDQ[50]
N3
TSEC3_RX_DV
P8
MDQ[54]
N4
TSEC3_RX_CLK
P9
GVDD
N5
TSEC3_RXD[0]
P10
TSEC3_TX_EN
N6
TSEC3_RXD[7]
P11
TSEC3_TXD[6]
N7
NC
P12
TVDD
N8
VDD
P13
TSEC3_RXD[1]
N9
GND
P14
TSEC3_RXD[2]
N10
VDD
P15
TSEC3_RXD[6]
N11
GND
P16
VDD
N12
VDD
P17
GND
N13
GND
P18
VDD
N14
NC
P19
GND
N15
XVDD_SRDS
P20
VDD
N16
XGND_SRDS
P21
GND
N17
SD1_TX[2]
P22
VDD
N18
SD1_TX[2]
P23
NC
N19
SGND_SRDS
P24
SD1_TX[1]
N20
SD1_RX[1]
P25
SD1_TX[1]
N21
SD1_RX[1]
P26
XGND_SRDS
N22
SGND_SRDS
P27
XVDD_SRDS
N23
SVDD_SRDS
P28
NC
N24
MDQ[59]
R1
SVDD_SRDS
N25
MDQ[63]
R2
SGND_SRDS
N26
GVDD
R3
SD1_RX[0]
N27
LVDD
R4
SD1_RX[0]
N28
TSEC1_COL
R5
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
45
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
TSEC3_TXD[2]
R6
NC
T11
TSEC3_GTX_CLK
R7
NC
T12
TSEC3_RXD[3]
R8
VDD
T13
TSEC1_RX_ER
R9
GND
T14
TVDD
R10
VDD
T15
TSEC3_RX_ER
R11
GND
T16
VDD
R12
VDD
T17
GND
R13
GND
T18
VDD
R14
NC
T19
GND
R15
XVDD_SRDS
T20
VDD
R16
XGND_SRDS
T21
GND
R17
SD1_TST_CLK
T22
VDD
R18
SD1_TST_CLK
T23
NC
R19
SVDD_SRDS
T24
SD1_TX[3]
R20
SD1_RX[3]
T25
SD1_TX[3]
R21
SD1_RX[3]
T26
XVDD_SRDS
R22
SVDD_SRDS
T27
XGND_SRDS
R23
SGND_SRDS
T28
SVDD_SRDS
R24
TSEC1_TXD[0]
U1
SGND_SRDS
R25
TSEC1_TXD[1]
U2
SVDD_SRDS
R26
LVDD
U3
SD1_RX[2]
R27
TSEC1_TX_EN
U4
SD1_RX[2]
R28
TSEC1_TXD[6]
U5
TSEC1_GTX_CLK
T1
GND
U6
EC_GTX_CLK125
T2
TSEC1_RX_DV
U7
TSEC1_TX_ER
T3
TSEC1_RXD[3]
U8
TSEC1_CRS
T4
TSEC1_RXD[6]
U9
TSEC1_TXD[7]
T5
TSEC1_RXD[7]
U10
TSEC1_RXD[0]
T6
NC
U11
TSEC1_RXD[1]
T7
VDD
U12
TSEC1_RXD[2]
T8
GND
U13
TSEC1_RXD[4]
T9
VDD
U14
TSEC1_RXD[5]
T10
GND
U15
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 46
Freescale Semiconductor
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
VDD
U16
XVDD_SRDS
V21
GND
U17
SD1_TX[5]
V22
VDD
U18
SD1_TX[5]
V23
NC
U19
SGND_SRDS
V24
SD1_TX[4]
U20
NC
V25
SD1_TX[4]
U21
SD1_PLL_TPA
V26
XGND_SRDS
U22
AGND_SRDS
V27
XVDD_SRDS
U23
SD1_PLL_TPD
V28
SGND_SRDS
U24
NC
W1
SVDD_SRDS
U25
NC
W2
SGND_SRDS
U26
NC
W3
SD1_REF_CLK
U27
NC
W4
SD1_REF_CLK
U28
NC
W5
TSEC1_TXD[2]
V1
NC
W6
TSEC1_TXD[3]
V2
NC
W7
TSEC1_TXD[4]
V3
NC
W8
GND
V4
MSRCID[1]
W9
TSEC1_TXD[5]
V5
SENSEVSS
W10
TSEC1_TX_CLK
V6
SENSEVDD
W11
TSEC1_RX_CLK
V7
NC
W12
NC
V8
NC
W13
NC
V9
NC
W14
NC
V10
NC
W15
NC
V11
NC
W16
NC
V12
NC
W17
NC
V13
NC
W18
NC
V14
NC
W19
NC
V15
SD1_TX[6]
W20
NC
V16
SD1_TX[6]
W21
NC
V17
XVDD_SRDS
W22
NC
V18
XGND_SRDS
W23
NC
V19
SVDD_SRDS
W24
XGND_SRDS
V20
SGND_SRDS
W25
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
47
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
SVDD_SRDS
W26
TEMP_CATHODE
AA3
NC
W27
XGND_SRDS2
AA4
AVDD_SRDS
W28
SD2_TX[3]
AA5
SD2_IMP_CAL_TX
Y1
XVDD_SRDS2
AA6
SGND_SRDS2
Y2
DMA_DDONE[0]
AA7
TEMP_ANODE
Y3
GND
AA8
XGND_SRDS2
Y4
MSRCID[2]
AA9
SD2_TX[3]
Y5
DMA_DREQ[0]
AA10
XVDD_SRDS2
Y6
DMA_DREQ[1]
AA11
MSRCID[0]
Y7
CKSTP_OUT
AA12
MDVAL
Y8
PCI1_STOP
AA13
EC_MDIO
Y9
PCI1_C_BE[1]
AA14
GND
Y10
PCI1_AD[11]
AA15
DMA_DDONE[1]
Y11
PCI1_AD[0]
AA16
DMA_DACK[1]
Y12
GND
AA17
DMA_DACK[0]
Y13
NC
AA18
PCI1_AD[15]
Y14
NC
AA19
PCI1_AD[9]
Y15
SD2_TX[0]
AA20
OVDD
Y16
SD2_TX[0]
AA21
NC
Y17
XGND_SRDS2
AA22
NC
Y18
XVDD_SRDS2
AA23
NC
Y19
SGND_SRDS
AA24
XVDD_SRDS
Y20
SVDD_SRDS
AA25
XGND_SRDS
Y21
SGND_SRDS
AA26
SD1_TX[7]
Y22
SD1_RX[5]
AA27
SD1_TX[7]
Y23
SD1_RX[5]
AA28
SVDD_SRDS
Y24
SVDD_SRDS2
AB1
SD1_RX[4]
Y25
SD2_RX[3]
AB2
SD1_RX[4]
Y26
SGND_SRDS2
AB3
SVDD_SRDS
Y27
SD2_TX[2]
AB4
SGND_SRDS
Y28
TRIG_OUT/READY/QUIESCE
AB5
SGND_SRDS2
AA1
MSRCID[3]
AB6
SD2_RX[3]
AA2
OVDD
AB7
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 48
Freescale Semiconductor
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
PCI1_REQ[0]
AB8
PCI1_DEVSEL
AC13
PCI1_AD[26]
AB9
PCI1_SERR
AC14
OVDD
AB10
PCI1_AD[13]
AC15
PCI1_AD[20]
AB11
GND
AC16
PCI1_AD[19]
AB12
PCI1_AD[5]
AC17
OVDD
AB13
OVDD
AC18
PCI1_PAR
AB14
IRQ[8]
AC19
PCI1_AD[12]
AB15
L1_TSTCLK
AC20
PCI1_AD[8]
AB16
GND
AC21
PCI1_AD[2]
AB17
IRQ[7]
AC22
PCI1_AD[1]
AB18
IRQ[6]
AC23
NC
AB19
SGND_SRDS
AC24
NC
AB20
SGND_SRDS2
AC25
NC
AB21
SVDD_SRDS2
AC26
NC
AB22
SD1_RX[7]
AC27
NC
AB23
SD1_RX[7]
AC28
SGND_SRDS
AB24
SD2_RX[2]
AD1
SD1_RX[6]
AB25
SVDD_SRDS2
AD2
SD1_RX[6]
AB26
SGND_SRDS2
AD3
SGND_SRDS
AB27
XGND_SRDS2
AD4
SVDD_SRDS
AB28
MSRCID[4]
AD5
SD2_RX[2]
AC1
PCI1_REQ[1]
AD6
SGND_SRDS2
AC2
GND
AD7
SGND_SRDS2
AC3
PCI1_AD[30]
AD8
SD2_TX[2]
AC4
OVDD
AD9
TRIG_IN
AC5
PCI1_AD[23]
AD10
OVDD
AC6
OVDD
AD11
EC_MDC
AC7
PCI1_FRAME
AD12
PCI1_GNT[1]
AC8
PCI1_TRDY
AD13
PCI1_AD[25]
AC9
IRQ_OUT
AD14
PCI1_C_BE[3]
AC10
OVDD
AD15
PCI1_AD[21]
AC11
PCI1_AD[10]
AD16
PCI1_AD[18]
AC12
PCI1_C_BE[0]
AD17
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
49
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
GND
AD18
GND
AE23
PCI1_AD[3]
AD19
IRQ[11]/DMA_DDONE3
AE24
OVDD
AD20
SGND_SRDS2
AE25
IRQ[2]
AD21
SVDD_SRDS2
AE26
GPIN[4]
AD22
IRQ[10]/DMA_DACK3
AE27
GPIN[2]
AD23
SD1_IMP_CAL_TX
AE28
SGND_SRDS2
AD24
AGND_SRDS2
AF1
SD2_RX[0]
AD25
SD2_REF_CLK
AF2
SD2_RX[0]
AD26
SGND_SRDS2
AF3
SVDD_SRDS
AD27
SD2_TST_CLK
AF4
SGND_SRDS
AD28
XVDD_SRDS2
AF5
SGND_SRDS2
AE1
UART_CTS[1]
AF6
SD2_REF_CLK
AE2
UART_SOUT[1]
AF7
SGND_SRDS2
AE3
PCI1_AD[29]
AF8
XGND_SRDS2
AE4
PCI1_REQ[4]
AF9
OVDD
AE5
OVDD
AF10
PCI1_GNT[0]
AE6
GND
AF11
PCI1_GNT[4]
AE7
PCI1_AD[17]
AF12
PCI1_AD[31]
AE8
PCI1_IRDY
AF13
PCI1_AD[24]
AE9
GND
AF14
PCI1_AD[22]
AE10
RTC
AF15
PCI1_AD[16]
AE11
IRQ[5]
AF16
PCI1_C_BE[2]
AE12
IRQ[1]
AF17
OVDD
AE13
PCI1_AD[7]
AF18
PCI1_PERR
AE14
IRQ[3]
AF19
PCI1_AD[14]
AE15
OVDD
AF20
CLK_OUT
AE16
GPOUT[4]
AF21
L2_TSTCLK
AE17
GPOUT[0]
AF22
PCI1_AD[6]
AE18
GPIN[5]
AF23
PCI1_AD[4]
AE19
OVDD
AF24
GPIN[7]
AE20
GPOUT[5]
AF25
GPIN[3]
AE21
GPOUT[7]
AF26
OVDD
AE22
OVDD
AF27
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 50
Freescale Semiconductor
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
TDO
AF28
CKSTP_IN
AH5
AVDD_SRDS2
AG1
UART_SIN[1]
AH6
SVDD_SRDS2
AG2
UART_SOUT[0]
AH7
SD2_PLL_TPD
AG3
UART_CTS[0]
AH8
SD2_TST_CLK
AG4
GND
AH9
XVDD_SRDS2
AG5
PCI1_REQ[2]
AH10
PCI1_IDSEL
AG6
PCI1_GNT[2]
AH11
UART_SIN[0]
AG7
PCI1_AD[28]
AH12
UART_RTS[0]
AG8
TEST_SEL
AH13
UART_RTS[1]
AG9
AVDD_CORE
AH14
PCI1_REQ[3]
AG10
UDE
AH15
PCI1_GNT[3]
AG11
SYSCLK
AH16
PCI1_AD[27]
AG12
ASLEEP
AH17
IIC2_SCL
AG13
AVDD_PLAT
AH18
IIC2_SDA
AG14
LSSD_MODE
AH19
HRESET_REQ
AG15
AVDD_PCI1
AH20
HRESET
AG16
IIC1_SDA
AH21
IRQ[4]
AG17
TRST
AH22
MCP
AG18
GPOUT[1]
AH23
SRESET
AG19
GPIN[0]
AH24
IRQ[9]/DMA_DREQ3
AG20
GPOUT[3]
AH25
IIC1_SCL
AG21
PCI1_CLK
AH26
IRQ[0]
AG22
TMS
AH27
GND
AG23
TDI
AH28
GPIN[1]
AG24
GPIN[6]
AG25
GPOUT[6]
AG26
GPOUT[2]
AG27
TCK
AG28
SD2_PLL_TPA
AH1
SGND_SRDS2
AH2
SD2_IMP_CAL_RX
AH3
XGND_SRDS2
AH4
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
51
Clocks
5
Clocks
Figure 10 shows the internal distribution of clocks.
e500 Core cfg_core_pll[0:2]
cfg_sys_pll[0:3]
3
4
Core PLL
Device PLL
CCB_clk
÷2
core_clk
6 DDR
6
MCK[0:5] MCK[0:5]
DDR Controller
SYSCLK LSYNC_IN
÷n PCI_CLK
LSYNC_OUT PLL
PCI
LCLK0 LCLK1 LCLK2
LBC
CCB_clk to Rest of the Device
Figure 10. Clock Subsystem Block Diagram
The clock inputs for the MPC8544E are the EC_GTX_CLK125, PCI1_CLK, RTC, SD_REF_CLK/SD_REF_CLK and SYSCLK. The EC_GTX_CLK125 input is used by the eTSEC controller as a reference clock for gigabit Ethernet modes. The PCI1_CLK input are PCI clock input if the PCI controller is configured in asynchronous mode. SD_REF_CLK/SD_REF_CLK are the reference clocks for PCI-Express and SGMII operating modes. SYSCLK is the primary clock input to the device. Table 10 shows how the clock pins should be connected. Table 10. Clock Pin Recommendations Pin Name EC_GTX_CLK125 PCI1_CLK
RTC
Pin Used If any of the eTSECs are used in gigabit mode, connect to a 125 MHz clock.
Pin Not Used Pull high or low through a 2–10 kΩ resistor to LVDD or GND, respectively.
Pull high or low through a 2–10 kΩ resistor to If PCI1 is configured for PCI and isochronous OVDD or GND, respectively. mode, connect to a 16 - 66 MHz clock. If PCI1 is configured for PCI-X and asychronous mode, connect to a 66 - 133 MHz clock. If used, connect to a clock that runs no greater than 1/4 the platform CCB_clk.
Pull high or low through a 2–10 kΩ resistor to OVDD or GND, respectively.
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Clocks
Table 10. Clock Pin Recommendations (continued) Pin Name
Pin Used
SD_REF_CLK / SD_REF_CLK
These pins must be connected to GND. If the SerDes is enabled at POR, connect to a clock at the frequency specified per the POR I/O Port Selection.
SYSCLK
5.1
Pin Not Used
This must always be connected to an input clock of 16–133 MHz
System PLL Ratio
The system PLL inputs, shown in Table 11, establish the clock ratio between the SYSCLK input and the platform clock. Table 11. CCB Clock Ratio
5.2
Binary Value of LA[28:31] Signals
CCB:SYSCLK Ratio
Binary Value of LA[28:31] Signals
CCB:SYSCLK Ratio
0000
16:1
1000
8:1
0001
Reserved
1001
9:1
0010
Reserved
1010
10:1
0011
3:1
1011
Reserved
0100
4:1
1100
12:1
0101
5:1
1101
Reserved
0110
6:1
1110
Reserved
0111
Reserved
1111
Reserved
e500 Core PLL Ratio
Table 12 describes the e500 core clock PLL inputs that program the core PLL and establish the ratio between the e500 core clock and the e500 core complex bus (CCB) clock. Table 12. e500 Core to CCB Clock Ratio Binary Value of LBCTL, LALE, LGPL2 Signals
e500 core: CCB Clock Ratio
Binary Value of LBCTL, LALE, LGPL2 Signals
e500 core: CCB Clock Ratio
000
4:1
100
2:1
001
Reserved
101
5:2
010
Reserved
110
3:1
011
3:2
111
7:2
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
53
DDR Interface
5.3
Security Controller PLL Ratio
The SEC mode frequency configuration allows for CCB CLK:SEC_CLK ratio of 2:1 or 3:1. Depending on the SEC PLL ratio of 2:1 or 3:1 the serial bit clock frequency of I2C (SCL) can be either one -half or one third of the CCB clock respectively. Table 13. SEC Frequency Ratio Pin Name
Value (Binary)
CCB CLK:SEC CLK
LWE
0
2:11
1
3:12
Notes: 1. In 2:1 mode the CCB frequency must be operating
Document Number: AN3547 Rev. 2, 02/2009
MPC8544E PowerQUICC™ III Bring-up Guide
This document provides recommendations for new designs based on the MPC8544E PowerQUICC III family of integrated host communications processors (collectively referred to throughout this document as MPC8544E): • MPC8544E • MPC8544 This document may also be useful in debugging newly designed systems by highlighting those aspects of a design that merit special attention during initial system startup. For updates to this document, refer to the website listed on the back cover of this document.
© Freescale Semiconductor, Inc., 2009. All rights reserved.
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21.
Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Power-on Reset and Reset Configurations . . . . . . . . . 9 Device Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 DDR Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Debug and Test Interface . . . . . . . . . . . . . . . . . . . . . 55 DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 DUART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Ethernet Management Interface . . . . . . . . . . . . . . . . 57 eTSEC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Local Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PIC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Spare Configuration Pins . . . . . . . . . . . . . . . . . . . . . 67 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . 67 Documentation History . . . . . . . . . . . . . . . . . . . . . . . 68
Introduction
1
Introduction
This section outlines recommendations to simplify the first phase of design. Before designing a system with a MPC8544E device, it is recommended that the designer be familiar with the available documentation, software, models, and tools.
1.1
MPC8544E Overview
This section provides a high-level overview of MPC8544E features. Figure 1 shows the major functional units within the device.
MPC8544E
e500 Core 32-Kbyte I-Cache
XOR Acceleration
Local Bus
Security Acceleration
Performance Monitor DUART 2x I2C
OpenPIC
Gigabit Ethernet SGMII
256-Kbyte L2 Cache
32-Kbyte D-Cache
e500 Coherency Module
64-Bit DDR/DDR2 SDRAM Controller
32-Bit PCI
PCI Express x4/x2/x1
PCI Express x1
PCI Express x4/x2/x1
DMA
Figure 1. MPC8544E Block Diagram
1.2 •
References Collateral — MPC8544E PowerQUICC III™ Integrated Host Processor Family Reference Manual (MPC8544ERM) — Errata to MPC8544E PowerQUICC™ III Integrated Host Processor Family Reference Manual (MPC8544ERMAD) — Device Errata for the MPC8544E PowerQUICC™ III (MPC8544ECE) — MPC8544E PowerQUICC III™ Integrated Processor Hardware Specifications (MPC8544EEC)
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 2
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Introduction
•
•
1.3
— A Strategy for Routing the MPC8544E in a Six-Layer PCB (AN3535) — PowerQUICC™ DDR2 SDRAM Controller Register Setting Considerations (AN3369) — Programming the PowerQUICC™ III/PowerQUICC II Pro DDR SDRAM Controller (AN2583) — Hardware and Layout Design Considerations for DDR Memory Interfaces (AN2582) — Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces (AN2910) Tools — Software – Boot sequencer generator tool (I2CBOOTSEQ) – UPM Programming tool (LBCUPMIBCG) — Hardware – Development System (MPC8544DS) including schematics, bill of materials, board errata list, User’s Guide, and configuration guide Models — IBIS — BSDL — Flowtherm
Device Errata
The device errata document MPC8544ECE describes the latest fixes and work arounds for the MPC8544E. The errata document should be thoroughly researched prior to starting a design with the respective MPC8544E device.
1.4
Boot Sequencer Tool
The MPC8544E features the boot sequencer to allow configuration of any memory-mapped register before the completion of power-on reset (POR). The register data to be changed is stored in an I2C EEPROM. The MPC8544E requires a particular data format for register changes as outlined in the MPC8544ERM. The boot sequencer tool (I2CBOOTSEQ) is a C-code file. When compiled and given a sample data file, it will generate the appropriate raw data format as outlined in the MPC8544ERM. The file that is generated is an s-record file that can be used to program the EEPROM.
1.5
UPM Programming Tool
The UPM Programming Tool (LBCUPMIBCG) features a GUI for a user-friendly programming interface. It allows programming of all three of the MPC8544E’s UPM machines. The GUI consists of a wave editor, a table editor, and a report generator. The user can edit the waveform directly or the RAM array directly.
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
3
Power
At the end of programming, the report generator will print out the UPM RAM array that can be used in a C-program.
1.6
Available Training
Our third-party partners are part of an extensive Design Alliance Program. The current training partners can be found on our website under Design Alliance Program at www.freescale.com/alliances. Training material from past Smart Network Developer’s Forums and Freescale Technology Forums are also available. These trainings modules are a valuable resource in understanding the MPC8544E. This material is also available at our website listed on the back cover of this document.
1.7
Product Revisions
Table 1 lists the Processor Version Register (PVR) and System Version Register (SVR) values for the various MPC8544E derivatives of silicon. Table 1. MPC8544E PowerQUICC III Product Revisions Device Number
Device Revision
e500 v2 Core Revision
Processor Version Register Value
System Version Register Value
Note
MPC8544E
1.0
2.1
0x8021_0021
0x803C_0110
With Security
MPC8544
1.0
2.1
0x8021_0021
0x8034_0110
Without Security
MPC8544E
1.1/1.1.1
2.2
0x8021_0022
0x803C_0111
With Security
MPC8544
1.1
2.2
0x8021_0022
0x8034_0111
Without Security
2
Power
This section provides design considerations for the power supplies and power sequencing. For information on AC and DC electrical specifications and thermal characteristics, refer to the MPC8544EEC Hardware Specification document.
2.1
Power Supplies
The MPC8544E has a core voltage VDD and SerDes voltages SVDD and XVDD that operate at a lower voltage than the I/O voltages BVDD, GVDD, LVDD, OVDD, and TVDD. The core voltage, 1.0 V (±5%), is supplied across VDD and GND. The I/O blocks are supplied with the following: • 1.8 V (±5%) or 2.5 V (±5%) or 3.3 V (±5%) across BVDD and GND • 1.8 V (±5%) or 2.5 V (±5%) across GVDD and GND • 2.5 V (±5%) or 3.3 V (±5%) across LVDD and GND • 3.3 V (±5%) across OVDD and GND • 1.0 V (±5%) across SVDD and GND MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 4
Freescale Semiconductor
Power
• •
2.5 V (±5%) or 3.3 V (±5%) across TVDD and GND 1.0 V (±5%) across XVDD and GND
Both LVDD and TVDD are used to supply the eTSEC interfaces on the device: LVDD manages eTSEC1, and TVDD manages eTSEC3. For the respective eTSEC, LVDD/TVDD • 3.3 V or 2.5 V for GMII, MII, RMII, TBI, or FIFO modes of operation • 2.5 V for RGMII or RTBI modes of operation NOTE eTSEC1 and/or eTSEC3 can be configured to operate in SGMII mode. Details are provided in the MPC8544E PowerQUICC III™ Integrated Host Processor Family Reference Manual (MPC8544ERM).
2.2
Power Consumption
Operating-mode power dissipation numbers (Typical) are provided in the MPC8544EEC Hardware Specification. Typical and Thermal numbers are provided to assist in the thermal design for the device. If the targeted junction temperature (TJ) of the MPC8544E in the system is not one of these two temperatures, a linear extrapolation of these two TYPICAL dissipation values can be used to estimate the power dissipation at the targeted junction temperature. The Maximum is intended to assist in the power supply design selection.
2.2.1
Low Power Modes Power Dissipation
A low-power mode estimates provided in Table 2 for applications concerned about minimizing power consumption when the core is not active. Table 2. Power Dissipation Estimated For Low Power Modes Core/CCB Frequency Low Power Modes
667/333 MHz
800/400 MHz
1000/400 MHz
1067/533 MHz
SLEEP
1.50 W
1.55 W
1.55 W
1.6 W
NAP
1.75 W
1.80 W
1.90 W
2.0 W
DOZE
2.20 W
2.35 W
2.6 W
2.7 W
NOTE The Typical, Thermal, and Maximum power numbers are based on the power dissipation on the 1.0 V nominal VDD supply only. Typical power dissipation estimates on the peripheral supplies (BVDD, GVDD, LVDD, OVDD, TVDD, and XVDD) are provided in MPC8544EEC.
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
5
Power
2.2.2
I/O Power Dissipation
Because I/O usage varies from design to design, power dissipation estimates for the I/O supplies are provided in Table 3. Table 3. Estimated I/O Power Dissipation Interface
Parameters
1.0 V (XVDD)
1.8 V (GVDD)
2.5 V (B/G/LV DD)
3.3 V (B/L/OV DD)
Comments
DDR
333 MHz data
—
0.38 W
0.73 W
—
—
400 MHz data
—
0.46 W
—
—
533 MHz data
—
0.60 W
—
—
PCI Express
x4, 2.5 G-baud
0.36 W
—
—
—
—
PCI
32-bit, 66 MHz
—
—
—
0.07 W
32-bit, 33 MHz
—
—
—
0.04 W
Power per PCI port
32-bit, 133 MHz
—
—
0.14 W
0.24 W
32-bit, 66 MHz
—
—
0.07 W
0.13 W
32-bit, 33 MHz
—
—
0.04 W
0.07 W
MII
—
—
—
0.01 W
GMII
—
—
—
0.07 W
TBI
—
—
—
0.07 W
RGMII
—
—
0.04 W
—
RTBI
—
—
0.04 W
—
8-bit, 200 MHz
—
—
0.11 W
—
8-bit, 155 MHz
—
—
0.08 W
—
Local bus
eTSEC (10/100/1000 Ethernet)
eTSEC (packet FIFO)
2.3
—
Power per eTSEC used
Power per FIFO interface used
Power Sequencing
The device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. Per MPC8544EEC, the requirements for power-up are as follows: 1. VDD, AVDD_n, BVDD, LVDD, OVDD, SVDD, TVDD, XVDD 2. GVDD All supplies must be at their stable values within 50 ms. Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs. The purpose of the sequence is to guarantee the state of the DDR signals at reset. In order to guarantee MCKE low during power-up (as should be attempted per the JEDEC JESD79-2C specification), the above sequencing for GVDD is required. If there is no concern about any of the DDR signals being in an indeterminate state during power-up, then the sequencing of GVDD is not required. MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 6
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Power
From a system standpoint, if any of the I/O power supplies ramp prior to the VDD core supply, the I/Os associated with that I/O supply may drive a logic one or zero during power-up, and extra current may be drawn by the device.
2.4
PLL Power Supply Filtering
Each of the PLLs is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CORE, AVDD_PCI, AVDD_LBIU, and AVDD_SRDS respectively). Preferably these voltages will be derived directly from VDD through a low-frequency filter scheme. Although there are a number of ways to reliably provide power to the PLLs, the recommended solution is to provide independent filter circuits per PLL power supply as illustrated in Figure 2, one to each of the AVDD pins. By providing independent filters to each PLL, the opportunity to cause noise injection from one PLL to the other is reduced. This circuit is intended to filter noise in the PLLs’ resonant frequency range from a 500 kHz to 10 MHz range. If the PCI is run in synchronous mode, no filter is required for AVDD_PCI. 10 Ω V DD
AVDD 2.2 µF
2.2 µF
GND
Low ESL Surface Mount Capacitors
Figure 2. PLL Power Supply Filter Circuit
The AVDD_SRDSn signals provide power for the analog portions of the SerDes PLL. To ensure stability of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in Figure 3. For maximum effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn balls to ensure it filters out as much noise as possible. The ground connection should be near the AVDD_SRDSn balls. The 0.003-µF capacitor is closest to the balls, followed by the 1-µF capacitor, and finally the 1-Ω resistor to the board supply plane. The capacitors are connected from AVDD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. If the SerDes is not used, a filter for AVDD_SRDS is not required. SVDD
1.0 Ω
AVDD_SRDS 2.2 µF 1
2.2 µF 1
0.003 µF
GND 1. An 0805 sized capacitor is recommended for system initial bring-up. 2. AVDD_SRDS should be a filtered version of SVDD. 3. Signals on the SerDes interface are fed from the XVDD power plane.
Figure 3. SerDes PLL Power Supply Filter
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from nearby circuits. These filters are a necessary extension of the PLL circuitry and are to what the device is specified. Any deviation from the recommended filters are done at the customer’s risk. MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
7
Power
2.5
Power Supply Decoupling
The MPC8544E requires a clean, tightly regulated source of power. The system designer should place at least one decoupling capacitor at each VDD and B/G/L/O/TVDD pin of the device. These decoupling capacitors should have a value of 0.01 or 0.1 µF and receive their power from separate VDD, B/G/L/O/TVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. In addition, several bulk storage capacitors should be distributed around the PCB to feed the VDD and B/G/L/O/TVDD planes in order to enable quick recharging of the smaller chip capacitors. The capacitors should be placed as close as possible to the processor. The capacitors need to be selected to work well with the power-supply so as to be able to handle the MPC8544E’s dynamic load requirements. The customer should work closely with their power-supply vendor to choose the correct value and type of capacitors for good and clean power. If the SerDes is used, it requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low jitter on transmit and reliable recovery of data in the receiver: • • •
2.6
The board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to the supply balls of the device. There should be a 1-µF ceramic chip capacitor from each SerDes supply (SVDD and XVDD) to the board ground plane on each side of the device. Between the device and any SerDes voltage regulator there should be a 10-µF, low ESR SMT tantalum chip capacitor and a 100-µF, low ESR SMT tantalum chip capacitor. This should be done for all SerDes supplies.
Power Supplies Checklist
Table 4 provides a summary power supply checklist for the designer. Table 4. Power Supplies Checklist Item
Description
Completed
1
All power supplies have a voltage tolerance no greater than 5% from the nominal value.
2
eTSEC supplies are chosen according to the mode of operation used.
3
Power supply selected is based on MAXIMUM power dissipation.
4
Thermal design is based on TYPICAL power dissipation.
5
Power-up sequence is less than 50 ms.
6
Power sequencing is understood and based on whether or not latch-up or garbage data written to DDR is a concern.
7
Recommended PLL filter circuit is applied to AVDD_PLAT, AVDD_CORE, and AVDD_LBIU.
8
If PCI is used in asynchonous mode, then the recommended PLL filter circuit is applied to AVDD_PCI. However, If the PCI is used in synchronous mode, no filter is required for AVDD_PCI.
9
If SerDes is used, the recommended PLL filter circuit is applied to AVDD_SRDS. However, If SerDes is not used, a filter for AVDD_SRDS is not required.
10
PLL filter circuits are placed as close to the respective AVDD pin as possible.
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 8
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Power-on Reset and Reset Configurations
Table 4. Power Supplies Checklist Item
Description
Completed
11
Decoupling capacitors of 0.01 or 0.1 µF are placed at each VDD, B/G/L/O/TVDD pin.
12
Bulk capacitors are placed on each VDD, B/G/L/O/TVDD plane.
13
If SerDes is used, the recommended decoupling for S/XVDD is used.
3
Power-on Reset and Reset Configurations
This section discusses reset configurations.
3.1
Configuration and Timing
Various device functions are initialized by sampling certain signals during the assertion of HRESET. These power-on reset (POR) inputs are either pulled high or low during this period. While these pins are generally output pins during normal operation, they are treated as inputs while HRESET is asserted. HRESET must be asserted for a minimum on 100 μs. When HRESET de-asserts, the configuration pins are sampled and latched into registers, and the pins then take on their normal output circuit characteristics. Most of the configuration pins have an internally gated 20 kΩ pull-up resistor, enabled only during HRESET. For those configurations in which the default state is desired, no external pull-up is required. Otherwise, a 4.7 kΩ pull-down resistor is recommended to pull the configuration pin to a valid logic low level. In the case where a configuration pin has no default, 4.7 kΩ pull-up or pull-down resistors are recommended for appropriate configuration of the pin. An alternative to using pull-up and pull-down resistors to configure the POR pins is to use a PLD or similar device that drives the configuration signals to the MPC8544E when HRESET is asserted. The PLD must begin to drive these signals at least four SYSCLK cycles prior to the de-assertion of HRESET (PLL configuration inputs must meet a 100 μs set-up time to HRESET), hold their values for at least 2 SYSCLK cycles after the de-assertion of HRESET, and then release the pins to high impedance afterward for normal device operation.
3.2
Configuration Settings
The following table summarizes the customer configurable device settings. Refer to the MPC8544ERM for a more detailed description of each configuration option. Table 5. User Configuration Options Configuration Type
Functional Pins
Device
DMA_DACK[0:1]
CCB Clock PLL Ratio
LA[28:31]
e500 Core PLL Ratio
Comments Refer to Table 7 Checklist for POR and Reset Configurations There is no default value for this PLL ratio; these signals must be pulled to the desired value. Refer to Section 5.1, “System PLL Ratio.”
LBCTL, LALE, There is no default value for this PLL ratio; these signals must be pulled LGPL2/LOE/LSDRAS to the desired value. Refer to Section 5.2, “e500 Core PLL Ratio.”
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
9
Power-on Reset and Reset Configurations
Table 5. User Configuration Options (continued) Configuration Type
Functional Pins
Comments
SEC Frequency Ratio
LWE[0]
Boot ROM Location
TSEC1_TXD[6:4]
Default: Local Bus GPCM (32-bit ROM)
Host/Agent
LWE[1:3]/LBS[1:3]
Default: MPC8544E acts as the host processor/root complex on all interfaces.
I/O Port Selection
TSEC3_TXD[6:4]
Default: All three PCI Express ports active and SGMII ports active.
CPU Boot
LA27
Boot Sequencer
LGPL3/LSDCAS, LGPL5
DDR SDRAM Type
LGPL[0:1]
eTSEC1 Serial
TSEC1_TXD[2]
Default: eTSEC1 Ethernet interface uses parallel interface according to POR config inputs of eTSEC1 width and eTSEC1 protocol.
eTSEC3 Serial
TSEC3_TXD[2]
Default: eTSEC3 Ethernet interface uses parallel interface according to POR config inputs of eTSEC3 width and eTSEC3 protocol.
eTSEC1 Width
TSEC1_TX_ER
Default: eTSEC1 interface operates in standard width TBI, GMII, MII, or 8-bit FIFO mode.
eTSEC3 Width
TSEC3_TX_ER
Default: eTSEC3 Ethernet interface operates in standard TBI, GMII, MII, or 8-bit FIFO mode.
eTSEC1 Protocol
TSEC1_TXD[0:1]
Default: The eTSEC1 controller operates using the TBI protocol (or RTBI if configured in reduced mode).
eTSEC3 Protocol
TSEC3_TXD[0:1]
Default: The eTSEC3 controller operates using the TBI protocol (or RTBI if configured in reduced mode).
SGMII SerDes Reference Clock
TSEC3_TXD[3]
Default: SGMII SerDes expects a 125 MHz reference clock frequency.
PCI Clock Select
PCI1_GNT[4]
Default: Synchronous mode. SYSCLK is used as the clock for the PCI interface.
PCI Speed
PCI1_GNT[3]
Default: PCI frequency above 33 MHz.
PCI I/O Impedance
PCI1_GNT[1]
Default: 42 Ω I/O drivers are used on the PCI interface.
PCI Arbiter
PCI1_GNT[2]
Default: The on-chip PCI arbiter is enabled.
Memory Debug
MSRCID[0]
Default: Debug information from the DDR SDRAM controller is driven on the MSRCID and MDVAL signals.
DDR Debug
MSRCID[1]
Default: Debug information is not driven on ECC pins. ECC pins function in their normal mode.
General Purpose POR
LAD[0:31]
There is no default value for this general purpose POR.
Default: SEC in 3:1 (CCB CLK:SEC CLK). Refer to Section 5.3, “Security Controller PLL Ratio.”
Default: e500 core is allowed to boot without waiting for configuration by an external master. Default: Boot sequencer is disabled. No I2C ROM is accessed. Default: DDR controller is configured for DDR2.
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 10
Freescale Semiconductor
Power-on Reset and Reset Configurations
3.3
Internal Test Modes
Several pins double as test mode enables. These test modes are for internal use only, and if enabled during reset could result in the MPC8544E not coming out of reset. Table 6 lists these pins and how they should be addressed during the reset sequence. Table 6. Internal Test Mode Pins Pin Group
Pins
DDR
TEST_IN
Guideline for Reset Connect directly to ground
TEST_OUT Debug
This pin may be left floating.
TRIG_OUT/READY/ Because these pins have an internal pull-up enabled only at QUIESCE reset, they may be left floating if unconnected. Otherwise, they may need to be driven high (i.e., by a PLD), if the device to MSRCID[2] which they are connected does not release these pins to high impedance during reset. MSRCID[3] MSRCID[4
Design For Test
LSSD_MODE
These pins must be pulled to OVDD via a 100 Ω - 1 kΩ resistor.
L1_TSTCLK L2_TSTCLK TEST_SEL eTSEC
EC_MDC TSEC1_TXD[7] TSEC1_TXD[3]
Because these pins have an internal pull-up enabled only at reset, they may be left floating if unconnected. Otherwise, they may need to be driven high (i.e., by a PLD), if the device to which they are connected does not release these pins to high impedance during reset.
TSEC3_TXD[7]
3.4
Power Management
ASLEEP
System Control
HRESET_REQ
Reset Checklist
Table 7 provides a summary POR and reset checklist for the designer. Table 7. Checklist for POR and Reset Configurations Item
Description
1
HRESET is asserted for a minimum of 100 μs.
2
SRESET is asserted for a minimum of 3 SYSCLKs.
3
DMA_DACK[0:1] For proper state of these signals during reset, DMA_DACK[1] must be pulled down to GND through a resistor. DMA_DACK[0] can be pulled up or left without a resistor. However, if there is any device on the net which might pull down the value of the net at reset, a pull-up is needed on DMA_DACK[0].
4
Configuration pins are either appropriately tied-off with a 4.7 kΩ resistor or driven by an external device (meeting their required setup and hold times).
Completed
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
11
Device Pins
Table 7. Checklist for POR and Reset Configurations (continued) Item
Description
5
PLL configurations are defined and meet the required set-up and hold times.
6
Internal test mode pins are guaranteed not to be low during reset.
4
Completed
Device Pins
This section discusses the recommended test points and provides a device pin map.
4.1
Recommended Test Points
For easier debug, it is recommended that the test points on the board include the following pins: • CLK_OUT (This helps to verify the CCB clock.) • TRIG_OUT (This helps to verify the end of the reset sequence.) • ASLEEP (This helps to verify the end of the reset sequence.) • SENSEVDD (This helps to verify power plane VDD.) • SENSEVSS (This helps to verify ground plane VSS.) • HRESET_REQ (This helps to verify proper boot sequencer functions and reset requests.)
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 12
Freescale Semiconductor
Device Pins
4.2
Pin Map
Figure 4 provides a bottom view of the pin map of the device. A 1 2
MDQ [44]
B
C
D
E
F
G
GVDD
MDQS [5]
MDQ [32]
MDQ [46]
MDQ [47]
MDQ [34]
MDQ [40]
MDM [5]
MDQ [45]
MDQ [41]
4
MBA [0]
MWE
MCS [2]
5
MA [10]
MBA [1]
3
GND
MRAS
TEST_ OUT
NC
GND
7
GND
MA [0]
GVDD
8
MCK [3]
MCK [3]
MA [2]
6
9
MCK [0]
10
MA [3]
11
MA [6]
12
MA [11]
MCK [0]
GND
MODT [0]
GVDD
NC
GND
MA [4]
GVDD
MA [12]
14
GND
15
MDQ [26]
MDQ [31] MDQS [3]
GND
MECC [7]
MECC [6]
MDQS [8]
GVDD
MECC [1]
GND MDQ [19]
GVDD MDQ [23]
17
MDQS [3]
MDM [3]
GVDD
GND
18
MDQ [25]
MDQ [24]
MDQS [2]
MDM [2]
19 20
MDQ [29] MDQ [11]
21
MDQ [15]
22
MDQS [1]
23
MDQ [9]
MDQ [28] MDQ [10]
GVDD
MDQS [1]
MDQ [2]
MDQ [6]
MDM [1]
24 25
MDQ [12]
MDQ [5]
27 28
GND
GVDD MDQ [3]
MDQ [13]
MDQ [0]
GND
MDQ [17]
MDQ [14]
MDQ [8]
26
NC
MDQ [1] LDP [2]
MVREF
GND
A
B
MDQS [0]
MDQ [42] MDQ [33]
GVDD
GND
MDM [4]
GVDD
MDQ [37]
K
GND
MDQ [57]
MDQ [35]
MDQ [60]
MDQ [61]
GND
MA [15]
GVDD
MECC [2]
NC
GND
GND
MDQ [49]
MDQS [6]
MDQ [54]
MDQ [55]
LVDD [1]
MDQS [4]
MDQS [4]
MDQ [48]
GVDD
MCK [2]
NC
MCK [2]
MCKE [3]
MCK [5]
MCKE [0]
GVDD
GVDD
MCK [1]
MCK [1]
GVDD
GND
GND
GVDD
GVDD
GVDD
GND
GVDD
GND
MDIC [0]
GND
MDIC [1]
LCS [4]
LCS5/ DMA_ DREQ2
LCS6/ DMA_ DACK2
GND
MDQS [2]
MDQ [22]
GVDD
MDQ [21]
MDQ [16]
GND
LA [31]
LA [30]
GND
LGPL3/ LSDCAS
MDQ [20]
LCS [1]
BVDD
LGPL2 /LOE/ LSDRAS
LCS [3]
LAD [31]
LWE3/ LBS3/ LSDDQM [3]
MDQ [7]
GND
LCS [2]
GVDD LAD [27]
BVDD
GVDD
LAD [23]
MDM [0]
MDQ [4]
LDP [3]
LAD [19]
LAD [22]
LAD [18]
LAD [16]
BVDD
VDD
BVDD
GND
TSEC1_ TX_CLK
LGPL5
TVDD [1]
TSEC3_ TSEC3_ TSEC1_ TSEC1_ RXD RXD RXD RX_DV [3] [2] [3]
GND
TSEC3_ TSEC3_ RXD RXD [2] [0]
TVDD [2]
LA [27]
NC
VDD
GND
VDD
GND
VDD
GND
NC
VDD
GND
VDD
GND
VDD
GND
VDD
NC
NC
VDD
GND
VDD
GND
VDD
GND
NC
VDD
GND
VDD
GND
VDD
GND
VDD
NC
TSEC1_ TSEC1_ RXD RXD [7] [5] NC
NC
VDD
GND
VDD
GND
VDD
GND
NC
NC
VDD
GND
VDD
GND
VDD
GND
VDD
NC
NC
NC
BVDD
BVDD
AC
NC
MSRCID DMA_ DDONE [0] [0]
MSRCID [1]
MDVAL EC_ MDIO
UART_ CTS [0]
8
MSRCID PCI1_ AD [2] [26]
PCI1_ AD [25]
OVDD [7]
PCI1_ AD [24]
PCI1_ REQ [4]
UART_ RTS [1]
GND
9
PCI1_ AD [23]
PCI1_ AD [22]
OVDD [14]
PCI1_ REQ [3]
PCI1_ REQ [2]
10
PCI1_ GNT [2]
11
GND
NC
SENSE- DMA_ DMA_ VDD DDONE DREQ [1] [1]
PCI1_ AD [20]
PCI1_ AD [21]
OVDD [8]
PCI1_ AD [16]
GND
PCI1_ GNT [3]
NC
NC
DMA_ DACK [1]
CKSTP_ PCI1_ AD OUT [19]
PCI1_ AD [18]
PCI1_ FRAME
PCI1_ C_BE [2]
PCI1_ AD [17]
PCI1_ AD [27]
PCI1_ AD [28]
12
NC
DMA_ DACK [0]
PCI1_ STOP
OVDD PCI1_ DEVSEL [4]
PCI1_ TRDY
OVDD [9]
PCI1_ IRDY
IIC2_ SCL
TEST_ SEL
13
NC
PCI1_ AD [15]
PCI1_ C_BE [1]
PCI1_ PAR
PCI1_ SERR
IRQ_ OUT
PCI1_ PERR
GND
IIC2_ SDA
AVDD_ CORE
14
NC
PCI1_ AD [9]
PCI1_ AD [11]
PCI1_ AD [12]
PCI1_ AD [13]
OVDD [10]
PCI1_ AD [14]
RTC
HRESET_ REQ
UDE
15
OVDD [1]
PCI1_ AD [0]
PCI1_ AD [8]
GND
PCI1_ AD [10]
CLK_ OUT
IRQ [5]
HRESET SYSCLK
PCI1_ L2_ C_BE TSTCLK [0]
NC
NC
NC
NC
NC
NC
NC
NC SD1_ PLL_ TPA
LAD [15]
LAD [14]
GND
LAD [11]
LAD [9]
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SRDS [0] [2] SRDS SRDS
AVDD_ LSYNC_ OUT LBIU
LAD [20]
LAD [17]
LDP [1]
LAD [13]
LAD [12]
LAD [10]
LAD [8]
SGND_ SD1_RX SVDD_ SD1_RX SGND_ [2] [0] SRDS SRDS SRDS
SD1_ REF_ CLK
SD1_ PLL_ TPD
E
F
G
H
J
K
L
U
V
T
7
UART_ RTS [0]
OVDD [3]
GND
R
UART_ SOUT [0]
SENSEVSS
NC
GND
NC
NC
GND
PCI1_ AD [2]
PCI1_ AD [5]
NC
PCI1_ AD [1]
OVDD [6] IRQ [8]
AGND_ SRDS
IRQ [1]
16
IRQ [4]
ASLEEP
17 18
GND
PCI1_ AD [6]
PCI1_ AD [7]
MCP
AVDD_ PLAT
PCI1_ AD [3]
PCI1_ AD [4]
IRQ [3]
SRESET
LSSD_ MODE
19
GPIN [7]
OVDD [15]
IRQ[9] DMA_ DREQ3
AVDD_ PCI1
20
IRQ [2]
GPIN [3]
GPOUT [4]
IIC1_ SCL
IIC1_ SDA
21
GPIN [4]
OVDD [13]
GPOUT [0]
IRQ [0]
TRST
22
GPIN [2]
GND
GPIN [5]
GND
GPOUT [1]
23
IRQ[11] DMA_ DDONE3
OVDD [16]
GPIN [1]
GPIN [0]
24
SGND_ SD1_RX SVDD_ SD1_RX SGND_ SD2_RX SGND_ GPOUT [5] SRDS2 SRDS2 SRDS [0] [4] [6] SRDS
GPIN [6]
GPOUT [3]
25
PCI1_ CLK
26
NC
NC
NC
SVDD_ SGND_ SGND_ SVDD_ SRDS SRDS SRDS SRDS
SD1_ SGND_ SD1_RX SVDD_ SD1_RX SGND_ IMP_CAL SRDS SRDS [3] [1] SRDS _RX
P
UART_ SIN [0]
NC
NC
NC
NC
L1_ OVDD TSTCLK [11]
NC
GND
SEE DETAIL D
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SRDS [1] [3] SRDS SRDS
N
UART_ SOUT [1] PCI1_ AD [29]
IRQ [6]
M
6
PCI1_ GNT [4] PCI1_ AD [31]
NC
GND
PCI1_ IDSEL
UART_ SIN [1]
GND
XVDD_ SD1_TX XGND_ SD1_TX XVDD_ [5] [7] SRDS SRDS SRDS2
LDP [0]
UART_ CTS [1]
PCI1_ AD [30]
SD1_TX XVDD_ SD1_TX XGND_ [0] [2] SRDS SRDS
NC
PCI1_ GNT [0]
PCI1_ GNT [1]
NC
LBCTL
5
PCI1_ REQ [1]
PCI1_ REQ [0]
SD1_ TST_ CLK
NC
XVDD_ XVDD_ CKSTP_ SRDS2 SRDS2 IN
EC_ MDC
IRQ [7]
LAD [6]
4
OVDD [12]
SD2_ TST_ CLK
OVDD [2]
XGND_ SD1_TX XVDD_ SD1_TX XGND_ [5] [7] SRDS SRDS2 SRDS
LAD [7]
2 3
SEE DETAIL B
NC
1
XGND_ SRDS2
NC
XVDD_ XVDD_ MSRCID OVDD [3] [5] SRDS2 SRDS2
SVDD_ SGND_ SRDS2 SRDS2
SD2_ TST_ CLK
TRIG_ SD2_TX SD2_TX OUT/READY TRIG_ MSRCID IN [3] [3] [4] /QUIESCE
NC
AH SD2_ PLL_ TPA
SD2_ IMP_CAL _RX
NC
SD1_ TST_ CLK
SGND_ SVDD_ SRDS SRDS
AG
SD2_ PLL_ TPD
XGND_ XGND_ SD2_TX SD2_TX XGND_ XGND_ SRDS2 SRDS2 SRDS2 SRDS2 [2] [2]
SD1_TX XGND_ SD1_TX XVDD_ [2] SRDS [0] SRDS
XGND_ SRDS
SD2_ REF_ CLK
TEMP_ TEMP_ SGND_ SGND_ SGND_ SGND_ SGND_ ANODE CATHODE SRDS2 SRDS2 SRDS2 SRDS2 SRDS2
LAD [2]
LAD [5]
SD2_ REF_ CLK
NC
LAD [0]
LAD [4]
AF
NC
GND
BVDD
AE
SGND_ SD2_RX SD2_RX SGND_ SVDD_ SRDS2 SRDS2 SRDS2 [3] [3]
XVDD_ SD1_TX XGND_ SD1_TX XGND_ SD1_TX XVDD_ SD1_TX XGND_ SD2_TX SRDS SRDS SRDS [0] [3] [4] [6] [1] SRDS SRDS
LAD [3]
AD
NC
LAD [1]
LCLK [1]
LALE
AB
NC
LAD [21]
D
AA
PCI1_ C_BE [3]
LSYNC_ IN
C
Y
SD2_ SGND_ SVDD_ SD2_RX SD2_RX SGND_ AGND_ AVDD_ IMP_CAL SRDS2 SRDS2 SRDS2 SRDS2 SRDS2 [2] [2] _TX
DMA_ DREQ [0]
SD1_ REF_ CLK
GND
W
LGPL4 LGPL0/ LGPL1/ /LGTA/ XGND_ SD1_TX XVDD_ SD1_TX XVDD_ SD1_TX XGND_ SD1_TX XVDD_ SD2_TX LSDA10 LSDWE LUPWAIT/ SRDS [1] [3] [4] [6] [0] SRDS SRDS SRDS SRDS LPBSE
LAD [28]
GND
GND
LCS7/ DMA_ DDONE2
LWE2/ LBS2/ LSDDQM [2]
LCLK [2]
VDD
LCS [0]
LWE1/ LWE0/ LBS1/ LBS0/ LSDDQM LSDDQM [1] [0]
LCLK [0]
LA [28]
NC
LCKE
LAD [30]
LAD [26]
NC
GND
LA [29]
SEE DETAIL C LAD [29]
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TXD TXD RXD TXD TX_EN [2] [1] [0] [0]
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC3_ RXD RXD RXD RXD RX_ER [4] [5] [6] [7]
GND
BVDD
GND
TSEC1_ TSEC1_ TSEC1_ TSEC1_ TXD TXD TXD COL [6] [7] [5]
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ RXD RXD RX_CLK RX_ER RXD CRS COL [6] [1] [4]
MCKE TSEC3_ TX_CLK [1]
MECC [4]
MDQ [18]
MCK [4]
TSEC1_ TSEC1_ TX_EN CRS
TSEC1_ TXD [4]
GND
MECC [5]
MCK [4]
GND
LVDD [2]
TSEC3_ TSEC3_ TXD TX_ER [4]
NC
NC
GVDD
V
GND
GND
LAD [24]
GND
MCK [5]
NC
GND
U
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ GTX_ TXD TXD TXD TXD RXD RX_DV RX_CLK [5] [6] [3] CLK [7] [1]
MDM [8]
GVDD
MDQ [63]
MDQ [53]
MDQS [8]
GND
MDQS [7]
MDQ [39]
MCKE [2]
MECC [0]
GND
GVDD TSEC1_ TX_ER
MCAS
MA [14]
MDQS [7]
MDQ [51]
MODT [1]
GVDD
GVDD
T
TSEC1_ TSEC1_ TSEC1_ GTX_ TXD TXD [0] [2] CLK EC_ TSEC1_ TSEC1_ GTX_ TXD TXD CLK125 [1] [3]
MDQ [50]
GVDD
MA [7]
R MDQ [59]
MDQS [6]
MA [13]
MA [8]
P MDQ [58]
MDM [6]
MCS [1]
GND
MDM [7]
N MDQ [62]
GVDD
MCS [3]
GVDD
GND
M
MDQ [52]
MODT [3]
MA [1]
L
MDQ [38]
MODT [2]
MDQS [0]
LAD [25]
MDQ [43]
J MDQ [56]
SEE DETAIL A
MECC [3]
MDQ [27]
MDQ [30]
GVDD
MDQ [36]
NC
MBA [2]
16
GND
MA [5]
MA [9]
GVDD
MCS [0]
GND
TEST_ IN
13
GVDD
MDQS [5]
H
SVDD_ SGND_ SGND_ SGND_ SGND_ SRDS SRDS SRDS SRDS2 SRDS
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SD2_RX SVDD_ GPOUT GPOUT [7] [6] SRDS [6] [4] SRDS SRDS2 SRDS2 [0] NC
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SRDS [5] [7] SRDS SRDS
IRQ[10] DMA_ DACK3
AVDD_ SGND_ SD1_RX SVDD_ SD1_RX SGND_ SD1_ IMP_CAL [7] [5] SRDS SRDS SRDS SRDS _TX
W
Y
AA
AB
AC
AD
AE
OVDD [17]
GPOUT [2]
TMS
27
TDO
TCK
TDI
28
AF
AG
AH
Figure 4. MPC8544E Pin Map Top View
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
13
Device Pins
A 1
B
C
D
E
F
G
H
J
K
L
M
N
P
GVDD
MDQS [5]
MDQ [32]
MDQ [46]
MDQ [47]
MDQ [34]
GND
MDQ [56]
MDQ [57]
GND
GVDD
MDQ [62]
MDQ [58]
2
MDQ [44]
MDQ [40]
MDM [5]
MDQS [5]
GVDD
MDQ [42]
MDQ [43]
MDQ [35]
MDQ [60]
MDQ [61]
MDM [7]
MDQS [7]
GND
MDQS [7]
3
GND
MDQ [45]
MDQ [41]
MCS [0]
GND
MDQ [33]
GVDD
MDQ [38]
MDQ [52]
GVDD
MDM [6]
MDQS [6]
MDQ [50]
MDQ [51]
4
MBA [0]
MWE
MCS [2]
GVDD
MDQ [36]
GND
MDM [4]
GND
MDQ [39]
MDQ [53]
MDQ [49]
MDQS [6]
MDQ [54]
MDQ [55]
5
MA [10]
MBA [1]
MRAS
GND
MODT [0]
GVDD
MDQ [37]
GVDD
MDQS [4]
MDQS [4]
MDQ [48]
GND
GVDD
GND
6
TEST_ OUT
NC
GND
GVDD
MODT [2]
MODT [3]
MCS [3]
MCS [1]
MCK [2]
MCK [2]
NC
7
GND
MA [0]
GVDD
NC
MCAS
MA [13]
GVDD
MODT [1]
NC
GND
TSEC3_ TSEC3_ TXD TXD [3] [7]
8
MCK [3]
MCK [3]
MA [2]
GND
GVDD
GND
MA [1]
MCK [5]
MCK [5]
GND
TSEC3_ TSEC3_ TXD TX_ER [4]
9
MCK [0]
MCK [0]
GVDD
MA [4]
MA [8]
MA [7]
GVDD
MCKE [3]
NC
NC
TSEC3_ TSEC3_ CRS COL
TSEC3_ TSEC3_ RXD RX_CLK [1]
10
MA [3]
GND
MA [5]
NC
MA [14]
MA [15]
MCKE [2]
MCKE [0]
GVDD
MCKE [1]
TSEC3_ TX_CLK
TSEC3_ TSEC3_ RXD RXD [0] [2]
11
MA [6]
GVDD
MECC [3]
MA [12]
GVDD
MECC [2]
GVDD
MCK [1]
MCK [1]
GND
TSEC3_ TSEC3_ TSEC3_ TSEC3_ RXD RXD RXD RXD [4] [5] [6] [7]
12
MA [11]
MA [9]
GND
MECC [7]
GND
NC
MECC [0]
GVDD
GND
GVDD
GND
NC
VDD
NC
13
TEST_ IN
MBA [2]
MECC [6]
MDQS [8]
MDQS [8]
MDM [8]
GND
MCK [4]
MCK [4]
NC
NC
VDD
GND
VDD
14
GND
MDQ [27]
GVDD
MECC [1]
GVDD
MECC [5]
MECC [4]
GVDD
GND
GVDD
VDD
GND
VDD
GND
TSEC3_ TSEC3_ TSEC3_ TXD TXD TX_EN [1] [0]
GND
TSEC3_ TSEC3_ TXD TXD [5] [6] TVDD [1]
TSEC3_ RX_DV
DETAIL A Figure 5. MPC8544E Pin Map Detail A
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 14
Freescale Semiconductor
Device Pins
R
T
U
MDQ [59]
TSEC1_ GTX_ CLK
TSEC1_ TSEC1_ TXD TXD [2] [0]
NC
MDQ [63]
EC_ GTX_ CLK125
TSEC1_ TSEC1_ TXD TXD [3] [1]
NC
SGND_ SD2_RX SD2_RX SRDS2 [3] [3]
SGND_ SRDS2
GVDD
TSEC1_ TX_ER
TSEC1_ TXD [4]
NC
TEMP_ TEMP_ SGND_ ANODE CATHODE SRDS2
LVDD [1]
TSEC1_ TSEC1_ TX_EN CRS
GND
NC
XGND_ SRDS2
LVDD [2]
V
W
Y
AA
SD2_ SGND_ IMP_CAL SRDS2 _TX
XGND_ SRDS2
AB
AE
AF
AG
AH
SGND_ SRDS2
AGND_ SRDS2
AVDD_ SRDS2
SD2_ PLL_ TPA
1
SVDD_ SRDS2
SD2_ REF_ CLK
SD2_ REF_ CLK
SVDD_ SRDS2
SGND_ SRDS2
2
SGND_ SRDS2
SGND_ SRDS2
SGND_ SRDS2
SGND_ SRDS2
SD2_ PLL_ TPD
SD2_ IMP_CAL _RX
3
SD2_TX SD2_TX [2] [2]
XGND_ SRDS2
XGND_ SRDS2
SD2_ TST_ CLK
SD2_ TST_ CLK
XGND_ SRDS2
4
MSRCID [4]
OVDD [12]
XVDD_ SRDS2
XVDD_ SRDS2
CKSTP_ IN
5
OVDD [5]
PCI1_ REQ [1]
PCI1_ GNT [0]
UART_ CTS [1]
PCI1_ IDSEL
UART_ SIN [1]
6
SVDD_ SRDS2
AC
AD
SD2_RX SD2_RX [2] [2]
TSEC1_ COL
TSEC1_ TSEC1_ TSEC1_ TXD TXD TXD [5] [7] [6]
NC
TRIG_ SD2_TX SD2_TX OUT/READY TRIG_ IN [3] [3] /QUIESCE
TSEC3_ TXD [2]
TSEC1_ RXD [0]
TSEC1_ TX_CLK
NC
XVDD_ SRDS2
TSEC3_ TSEC1_ TSEC1_ TSEC1_ GTX_ RXD RX_DV RX_CLK [1] CLK
NC
DMA_ MSRCID DDONE [0] [0]
OVDD [2]
EC_ MDC
GND
PCI1_ GNT [4]
UART_ SOUT [1]
UART_ SIN [0]
UART_ SOUT [0]
7
TSEC3_ TSEC1_ TSEC1_ RXD RXD RXD [2] [3] [3]
NC
NC
MDVAL
GND
PCI1_ REQ [0]
PCI1_ GNT [1]
PCI1_ AD [30]
PCI1_ AD [31]
PCI1_ AD [29]
UART_ RTS [0]
UART_ CTS [0]
8
TSEC1_ TSEC1_ RXD RX_ER [4]
TSEC1_ RXD [6]
NC
MSRCID [1]
EC_ MDIO
MSRCID [2]
PCI1_ AD [26]
PCI1_ AD [25]
OVDD [7]
PCI1_ AD [24]
PCI1_ REQ [4]
UART_ RTS [1]
GND
9
TVDD [2]
TSEC1_ RXD [5]
TSEC1_ RXD [7]
NC
SENSEVSS
GND
DMA_ DREQ [0]
OVDD [3]
PCI1_ C_BE [3]
PCI1_ AD [23]
PCI1_ AD [22]
OVDD [14]
PCI1_ REQ [3]
PCI1_ REQ [2]
10
TSEC3_ RX_ER
NC
NC
NC
DMA_ SENSEDDONE VDD [1]
DMA_ DREQ [1]
PCI1_ AD [20]
PCI1_ AD [21]
OVDD [8]
PCI1_ AD [16]
GND
PCI1_ GNT [3]
PCI1_ GNT [2]
11
VDD
NC
VDD
NC
NC
DMA_ DACK [1]
CKSTP_ OUT
PCI1_ AD [19]
PCI1_ AD [18]
PCI1_ FRAME
PCI1_ C_BE [2]
PCI1_ AD [17]
PCI1_ AD [27]
PCI1_ AD [28]
12
GND
VDD
GND
NC
NC
DMA_ DACK [0]
PCI1_ STOP
OVDD [4]
PCI1_ DEVSEL
PCI1_ TRDY
OVDD [9]
PCI1_ IRDY
IIC2_ SCL
TEST_ SEL
13
VDD
GND
VDD
NC
NC
PCI1_ AD [15]
PCI1_ C_BE [1]
PCI1_ PAR
PCI1_ SERR
IRQ_ OUT
PCI1_ PERR
GND
IIC2_ SDA
AVDD_ CORE
14
GND
XVDD_ MSRCID [3] SRDS2
DETAIL B Figure 6. MPC8544E Pin Map Detail B
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
15
Device Pins
DETAIL C 15
MDQ [26]
MDQ [31]
GND
GVDD
GND
GVDD
GND
MDIC [0]
GND
MDIC [1]
GND
VDD
GND
VDD
16
MDQ [30]
MDQS [3]
MDQ [19]
MDQ [23]
MDQ [18]
GND
LCS [4]
LCS5/ DMA_ DREQ2
LCS6/ DMA_ DACK2
LA [28]
VDD
GND
VDD
GND
17
MDQS [3]
MDM [3]
GVDD
GND
MDQS [2]
MDQ [22]
LA [31]
LA [30]
GND
LA [29]
LCKE
VDD
GND
VDD
18
MDQ [25]
MDQ [24]
MDQS [2]
MDM [2]
GVDD
MDQ [21]
GND
LGPL3/ LSDCAS
BVDD
LCS [0]
LCS7/ DMA_ DDONE2
GND
VDD
GND
19
MDQ [29]
MDQ [28]
NC
MDQ [17]
MDQ [16]
MDQ [20]
LCS [1]
LCS [2]
BVDD
LGPL5
LA [27]
NC
NC
NC
20
MDQ [11]
MDQ [10]
GND
GVDD
GND
BVDD
LGPL2 /LOE/ LSDRAS
LCS [3]
LGPL0/ LSDA10
LGPL4 LGPL1/ /LGTA/ XGND_ LSDWE LUPWAIT/ SRDS LPBSE
SD1_TX [1]
XVDD_ SRDS
21
MDQ [15]
MDQ [14]
GVDD
MDQ [3]
MDQ [7]
GND
LAD [31]
LWE3/ LBS3/ LSDDQM [3]
BVDD
22
MDQS [1]
MDQS [1]
MDQ [2]
MDQ [6]
GVDD
LAD [29]
LAD [30]
23
MDQ [9]
MDM [1]
MDQS [0]
GND
LAD [27]
BVDD
24
MDQ [8]
MDQ [13]
GVDD
MDQS [0]
LAD [24]
25
MDQ [12]
MDQ [5]
MDM [0]
MDQ [4]
26
MDQ [0]
MDQ [1]
LAD [25]
27
GND
LDP [2]
28
MVREF
A
GND
LAD [1]
XVDD_ SRDS
SD1_TX [1]
XGND_ SRDS
LWE1/ LWE0/ LBS1/ LBS0/ LSDDQM LSDDQM [1] [0]
LAD [0]
LAD [2]
SD1_TX [0]
XGND_ SRDS
SD1_TX [2]
LAD [28]
LWE2/ LBS2/ LSDDQM [2]
BVDD
LAD [3]
BVDD
SD1_TX [0]
XVDD_ SRDS
SD1_TX [2]
LAD [23]
LAD [26]
LCLK [0]
LCLK [1]
LAD [4]
LAD [5]
XGND_ SRDS
NC
SGND_ SRDS
LDP [3]
LAD [19]
GND
LCLK [2]
LBCTL
LAD [7]
LAD [6]
NC
SVDD_ SRDS
SD1_RX [1]
GND
LAD [22]
LAD [18]
LAD [16]
BVDD
LALE
LDP [0]
GND
GND
LSYNC_ IN
LAD [21]
GND
LAD [15]
LAD [14]
GND
LAD [11]
LAD [9]
SVDD_ SRDS
SD1_RX [0]
SGND_ SRDS
GND
AVDD_ LBIU
LSYNC_ OUT
LAD [20]
LAD [17]
LDP [1]
LAD [13]
LAD [12]
LAD [10]
LAD [8]
SGND_ SRDS
SD1_RX [0]
SVDD_ SRDS
B
C
D
E
F
G
H
J
K
L
M
N
P
SD1_ SGND_ SD1_RX IMP_CAL SRDS [1] _RX
Figure 7. MPC8544E Pin Map Detail C
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 16
Freescale Semiconductor
Device Pins
DETAIL D GND
VDD
GND
NC
NC
PCI1_ AD [9]
PCI1_ AD [11]
PCI1_ AD [12]
PCI1_ AD [13]
OVDD [10]
PCI1_ AD [14]
RTC
HRESET_ REQ
VDD
GND
VDD
NC
NC
OVDD [1]
PCI1_ AD [0]
PCI1_ AD [8]
GND
PCI1_ AD [10]
CLK_ OUT
IRQ [5]
HRESET SYSCLK
GND
VDD
GND
NC
NC
NC
GND
PCI1_ AD [2]
PCI1_ AD [5]
PCI1_ C_BE [0]
L2_ TSTCLK
IRQ [1]
IRQ [4]
ASLEEP
17
VDD
GND
VDD
NC
NC
NC
NC
PCI1_ AD [1]
OVDD [6]
GND
PCI1_ AD [6]
PCI1_ AD [7]
MCP
AVDD_ PLAT
18
NC
NC
NC
NC
NC
NC
NC
NC
IRQ [8]
PCI1_ AD [3]
PCI1_ AD [4]
IRQ [3]
SRESET
LSSD_ MODE
19
SD1_TX [3]
XVDD_ SRDS
SD1_TX [4]
XGND_ SRDS
SD1_TX [6]
XVDD_ SRDS
SD2_TX [0]
NC
L1_ TSTCLK
OVDD [11]
GPIN [7]
OVDD [15]
IRQ[9] DMA_ DREQ3
AVDD_ PCI1
20
SD1_TX [3]
XGND_ SRDS
SD1_TX [4]
XVDD_ SRDS
SD1_TX [6]
XGND_ SRDS
SD2_TX [0]
NC
GND
IRQ [2]
GPIN [3]
GPOUT [4]
IIC1_ SCL
IIC1_ SDA
21
XVDD_ SRDS
SD1_ TST_ CLK
XGND_ SRDS
SD1_TX [5]
XVDD_ SRDS
SD1_TX [7]
XGND_ SRDS2
NC
IRQ [7]
GPIN [4]
OVDD [13]
GPOUT [0]
IRQ [0]
TRST
22
XGND_ SRDS
SD1_ TST_ CLK
XVDD_ SRDS
SD1_TX [5]
XGND_ SRDS
SD1_TX [7]
XVDD_ SRDS2
NC
IRQ [6]
GPIN [2]
GND
GPIN [5]
GND
GPOUT [1]
23
SVDD_ SRDS
SVDD_ SRDS
SGND_ SRDS
SGND_ SRDS
SVDD_ SRDS
SVDD_ SRDS
SGND_ SRDS
SGND_ SRDS
SGND_ SRDS
SGND_ SRDS2
IRQ[11] DMA_ DDONE3
OVDD [16]
GPIN [1]
GPIN [0]
24
SGND_ SRDS
SD1_RX [3]
SVDD_ SRDS
NC
SGND_ SD1_RX SRDS [4]
SVDD_ SRDS
SD1_RX SGND_ SRDS2 [6]
SD2_RX SGND_ [0] SRDS2
GPOUT [5]
GPIN [6]
GPOUT [3]
25
SVDD_ SRDS
SD1_RX [3]
SGND_ SRDS
SD1_ PLL_ TPA
SVDD_ SRDS
SD1_RX [4]
SGND_ SD1_RX [6] SRDS
SVDD_ SRDS2
SD2_RX [0]
SVDD_ SRDS2
GPOUT [7]
GPOUT [6]
PCI1_ CLK
26
SD1_RX [2]
SVDD_ SRDS
SD1_ REF_ CLK
AGND_ SRDS
NC
SVDD_ SRDS
SD1_RX SGND_ SD1_RX [5] [7] SRDS
SVDD_ SRDS
IRQ[10] DMA_ DACK3
OVDD [17]
GPOUT [2]
TMS
27
SD1_RX [2]
SGND_ SRDS
SD1_ REF_ CLK
SD1_ PLL_ TPD
AVDD_ SRDS
TDO
TCK
TDI
28
R
T
U
V
W
AF
AG
AH
SGND_ SD1_RX [5] SRDS
Y
AA
SVDD_ SRDS
AB
SD1_ SD1_RX SGND_ IMP_CAL [7] SRDS _TX
AC
AD
AE
UDE
15
16
Figure 8. MPC8544E Pin Map Detail D
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
17
Device Pins
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
GVDD
MDQS [5]
MDQ [32]
MDQ [46]
MDQ [47]
MDQ [34]
GND
MDQ [56]
MDQ [57]
GND
GVDD
MDQ [62]
MDQ [58]
MDQ [59]
MDQ [44]
MDQ [40]
MDM [5]
MDQS [5]
GVDD
MDQ [42]
MDQ [43]
MDQ [35]
MDQ [60]
MDQ [61]
MDM [7]
MDQS [7]
GND
MDQS [7]
MDQ [63]
GND
MDQ [45]
MDQ [41]
MCS [0]
GND
MDQ [33]
GVDD
MDQ [38]
MDQ [52]
GVDD
MDM [6]
MDQS [6]
MDQ [50]
MDQ [51]
GVDD TSEC1_ TX_ER
1 2 3 4
MBA [0]
5
MA [10]
6
TEST_ OUT
7
GND
MWE MBA [1]
NC MA [0]
8
MCK [3]
MCK [3]
9
MCK [0]
10
MA [3]
11
MA [6]
MCS [2] MRAS
GND
GVDD
GVDD
MDQ [36]
GND
MDQ [37]
GVDD
MDQS [4]
MDQS [4]
GVDD
MODT [2]
MODT [3]
MCS [3]
MCS [1]
MCK [2]
MCK [2]
NC
MCAS
MA [13]
MA [7]
GVDD
MCKE [3]
MA [15]
MCKE [2]
MCKE [0]
GVDD
MA [4]
MA [8]
GND
MA [5]
NC
MA [14]
12 13
TEST_ IN
MBA [2]
GVDD
MODT [1] MCK [5]
MCK [0]
MA [12]
GVDD MA [1]
GND
MA [9]
MDQ [53]
GVDD
GVDD
MA [11]
MDQ [39]
MODT [0]
GND
MECC [3]
GND
GND
MA [2]
GVDD
MDM [4]
MECC [2]
GND
MECC [7]
GND
NC
MECC [6]
MDQS [8]
MDQS [8]
MDM [8]
GVDD
MCK [1]
NC MCK [5]
NC
GVDD MCK [1]
MECC [0]
GVDD
GND
GND
MCK [4]
MCK [4]
GND
GND
NC
MDQ [49] MDQ [48]
NC
GVDD
NC
GND
MDQ [54] GVDD
MDQ [55]
GND
LVDD [1]
U
V
LVDD [2]
TSEC1_ TSEC1_ TX_EN CRS
TSEC1_ TXD [4] GND
TSEC1_ TSEC1_ TSEC1_ TSEC1_ TXD TXD TXD COL [6] [7] [5]
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TXD TXD RXD TXD TX_EN [1] [2] [0] [0]
GND
TSEC1_ TX_CLK
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ GTX_ TXD TXD TXD TXD RXD RX_DV RX_CLK [6] [5] CLK [3] [7] [1] TSEC3_ TSEC3_ TXD TX_ER [4]
TVDD [1]
TSEC3_ TSEC3_ TSEC1_ TSEC1_ RXD RXD RXD RX_DV [3] [2] [3]
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC1_ TSEC1_ TSEC1_ RXD RX_CLK RX_ER RXD RXD CRS COL [1] [6] [4]
MCKE TSEC3_ TX_CLK [1]
GND
MDQS [6]
T
TSEC1_ TSEC1_ TSEC1_ GTX_ TXD TXD [0] [2] CLK EC_ TSEC1_ GTX_ TSEC1_ TXD TXD CLK125 [1] [3]
GND
TSEC3_ TSEC3_ RXD RXD [2] [0]
TVDD [2]
TSEC3_ TSEC3_ TSEC3_ TSEC3_ TSEC3_ RXD RXD RXD RXD RX_ER [4] [5] [6] [7] GND
NC
NC
VDD
VDD
GND
NC
VDD
VDD
GND
TSEC1_ TSEC1_ RXD RXD [5] [7] NC
NC
VDD
NC
VDD
GND
W
Y
AC
AD
AE
NC
TEMP_ TEMP_ SGND_ SGND_ SGND_ SGND_ SGND_ ANODE CATHODE SRDS2 SRDS2 SRDS2 SRDS2 SRDS2
NC
XGND_ XGND_ SD2_TX SD2_TX XGND_ XGND_ SRDS2 SRDS2 SRDS2 SRDS2 [2] [2]
NC
TRIG_ SD2_TX SD2_TX OUT/READY TRIG_ MSRCID OVDD IN [4] [3] [3] [12] /QUIESCE
NC
XVDD_ SRDS2
NC
MSRCID DMA_ DDONE [0] [0]
OVDD [2]
EC_ MDC
PCI1_ REQ [0]
PCI1_ GNT [1]
MSRCID PCI1_ AD [2] [26]
MDVAL
NC
MSRCID [1]
EC_ MDIO
NC
SENSEVSS
NC
SENSE- DMA_ VDD DDONE [1]
GND
GND
6
GND
7
PCI1_ AD [30]
PCI1_ AD [31]
PCI1_ AD [29]
UART_ RTS [0]
UART_ CTS [0]
8
PCI1_ AD [25]
OVDD [7]
PCI1_ AD [24]
PCI1_ REQ [4]
UART_ RTS [1]
GND
9
PCI1_ AD [23]
PCI1_ AD [22]
OVDD [14]
PCI1_ REQ [3]
PCI1_ REQ [2]
10
OVDD [8]
PCI1_ AD [16]
GND
PCI1_ GNT [3]
PCI1_ GNT [2]
11
PCI1_ FRAME
PCI1_ C_BE [2]
PCI1_ AD [17]
PCI1_ AD [27]
PCI1_ AD [28]
12
OVDD [9]
PCI1_ IRDY
IIC2_ SCL
TEST_ SEL
13
DMA_ DREQ [0]
OVDD [3]
PCI1_ C_BE [3]
DMA_ DREQ [1]
PCI1_ AD [20]
PCI1_ AD [21]
NC
DMA_ DACK [1]
CKSTP_ OUT
PCI1_ AD [19]
NC
DMA_ DACK [0]
PCI1_ STOP
OVDD [4]
PCI1_ C_BE [1]
PCI1_ PAR
PCI1_ SERR
IRQ_ OUT
PCI1_ PERR
GND
IIC2_ SDA
AVDD_ CORE
14
PCI1_ AD [13]
OVDD [10]
PCI1_ AD [14]
RTC
HRESET_ REQ
UDE
15
CLK_ OUT
IRQ [5]
HRESET SYSCLK
PCI1_ AD [18]
PCI1_ PCI1_ DEVSEL TRDY
GND
GVDD
VDD
GND
VDD
GND
VDD
GND
VDD
NC
NC
15
MDQ [26]
MDQ [31]
GND
GVDD
GND
GVDD
GND
MDIC [0]
GND
MDIC [1]
GND
VDD
GND
VDD
GND
VDD
GND
NC
NC
PCI1_ AD [9]
PCI1_ AD [11]
PCI1_ AD [12]
16
MDQ [30]
MDQS [3]
MDQ [19]
MDQ [23]
MDQ [18]
GND
LCS [4]
LCS5/ DMA_ DREQ2
LCS6/ DMA_ DACK2
LA [28]
NC
OVDD [1]
PCI1_ AD [0]
PCI1_ AD [8]
GND
PCI1_ AD [10]
GND
PCI1_ AD [2]
PCI1_ AD [5]
PCI1_ L2_ C_BE TSTCLK [0]
NC
PCI1_ AD [1]
OVDD [6]
NC
IRQ [8]
MDM [3]
18
MDQ [25]
MDQ [24]
19
MDQ [29]
MDQ [28]
20
MDQ [11]
MDQ [10]
21
MDQ [15]
MDQ [14]
GVDD
GND
MDQS [2]
MDQ [22]
LA [31]
LA [30]
GND
LCKE
LCS [0]
LCS7/ DMA_ DDONE2
LGPL5
LA [27]
MDQS [2]
MDM [2]
GVDD
MDQ [21]
GND
NC
MDQ [17]
MDQ [16]
MDQ [20]
LCS [1]
LCS [2]
BVDD
LGPL2 /LOE/ LSDRAS
LCS [3]
LAD [31]
LWE3/ LBS3/ LSDDQM [3]
LAD [29]
LAD [30]
LWE1/ LWE0/ LBS1/ LBS0/ LSDDQM LSDDQM [1] [0]
LAD [0]
BVDD
LAD [28]
LWE2/ LBS2/ LSDDQM [2]
LAD [3]
GND
GVDD
22
MDQS [1]
MDQS [1]
MDQ [2]
23
MDQ [9]
MDM [1]
MDQS [0]
GVDD MDQ [3]
GND MDQ [7]
MDQ [6]
GVDD
GND
LAD [27]
GND
LGPL3/ BV DD LSDCAS
LA [29]
BVDD
VDD
GND
NC
NC
ASLEEP
17
GND
MCP
AVDD_ PLAT
18
PCI1_ AD [3]
PCI1_ AD [4]
IRQ [3]
LSSD_ SRESET MODE
19
L1_ OVDD TSTCLK [11]
GPIN [7]
OVDD [15]
IRQ[9] DMA_ DREQ3
AVDD_ PCI1
20
IIC1_ SDA
21
IIC1_ SCL
NC
IRQ [7]
GPIN [4]
OVDD [13]
GPOUT [0]
IRQ [0]
TRST
22
NC
IRQ [6]
GPIN [2]
GND
GPIN [5]
GND
GPOUT [1]
23
OVDD [16]
GPIN [1]
GPIN [0]
24
SGND_ SD1_RX SVDD_ SD1_RX SGND_ SD2_RX SGND_ GPOUT [5] SRDS2 SRDS2 SRDS [0] [4] [6] SRDS
GPIN [6]
GPOUT [3]
25
PCI1_ CLK
26
BVDD
LAD [2]
SD1_TX XGND_ SD1_TX XVDD_ [2] SRDS [0] SRDS
BVDD
SD1_TX XVDD_ SD1_TX XGND_ [2] [0] SRDS SRDS
SD1_ TST_ CLK
SGND_ SVDD_ SRDS SRDS
LCLK [1]
LAD [4]
LAD [5]
XGND_ SRDS
25
MDQ [12]
MDQ [5]
MDM [0]
MDQ [4]
LDP [3]
LAD [19]
GND
LCLK [2]
LBCTL
LAD [7]
LAD [6]
NC
26
MDQ [0]
MDQ [1]
LAD [25]
GND
LAD [22]
LAD [18]
LAD [16]
BVDD
LALE
LDP [0]
GND
GND
LDP [2]
LSYNC_ IN
LAD [21]
GND
LAD [15]
LAD [14]
GND
LAD [11]
LAD [9]
D
NC
IRQ [4]
PCI1_ AD [7]
GPOUT [4]
LCLK [0]
C
NC
NC
IRQ [1]
PCI1_ AD [6]
GPIN [3]
LAD [26]
B
NC
NC
NC
IRQ [2]
SD1_ TST_ CLK
LAD [23]
A
NC
NC
NC
GND
LAD [1]
LAD [24]
AVDD_ LSYNC_ OUT LBIU
NC
VDD
NC
NC
GND
MDQS [0]
GND
NC
GND
GND
XVDD_ SD1_TX XGND_ SD1_TX XGND_ SD1_TX XVDD_ SD1_TX XGND_ SD2_TX SRDS SRDS SRDS [3] [4] [6] [0] [1] SRDS SRDS
BVDD
GVDD
MVREF
NC
VDD
VDD
NC
MDQ [13]
28
NC
GND
GND
LGPL4
MDQ [8]
GND
VDD
VDD
16
LGPL0/ LGPL1/ /LGTA/ XGND_ SD1_TX XVDD_ SD1_TX XVDD_ SD1_TX XGND_ SD1_TX XVDD_ SD2_TX LSDA10 LSDWE LUPWAIT/ SRDS [1] [3] [4] [6] [0] SRDS SRDS SRDS SRDS LPBSE
24
27
GND
5
UART_ SOUT [0]
GVDD
MDQS [3]
XVDD_ XVDD_ CKSTP_ SRDS2 SRDS2 IN
UART_ SIN [0]
MECC [4]
17
4
UART_ SOUT [1]
MECC [5]
NC
XGND_ SRDS2
PCI1_ GNT [4]
GVDD
VDD
3
SD2_ TST_ CLK
SD2_ TST_ CLK
UART_ SIN [1]
MECC [1]
GND
SD2_ IMP_CAL _RX
PCI1_ IDSEL
GVDD
VDD
2
SD2_ PLL_ TPD
UART_ CTS [1]
MDQ [27]
GND
1
SVDD_ SGND_ SRDS2 SRDS2
PCI1_ GNT [0]
GND
VDD
SD2_ REF_ CLK
AH SD2_ PLL_ TPA
PCI1_ REQ [1]
XVDD_ MSRCID OVDD [3] [5] SRDS2
14
GND
AG
NC
SD2_ REF_ CLK
PCI1_ AD [15]
VDD
AF
SGND_ SD2_RX SD2_RX SGND_ SVDD_ SRDS2 SRDS2 SRDS2 [3] [3]
NC
NC
AB
SD2_ SGND_ SV DD_ SD2_RX SD2_RX SGND_ AGND_ AVDD_ IMP_CAL SRDS2 SRDS2 SRDS2 SRDS2 SRDS2 [2] [2] _TX
NC
NC
AA
NC
LAD [20]
LAD [17]
LDP [1]
LAD [13]
LAD [12]
LAD [10]
LAD [8]
E
F
G
H
J
K
L
NC
XGND_ SD1_TX XVDD_ SD1_TX XGND_ [5] [7] SRDS SRDS2 SRDS XVDD_ SD1_TX XGND_ SD1_TX XVDD_ [5] [7] SRDS SRDS SRDS2
SVDD_ SGND_ SGND_ SVDD_ SRDS SRDS SRDS SRDS
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SRDS [1] [3] SRDS SRDS
SD1_ SGND_ SD1_RX SVDD_ SD1_RX SGND_ IMP_CAL SRDS SRDS [3] [1] SRDS _RX
NC SD1_ PLL_ TPA
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SD2_RX SVDD_ GPOUT GPOUT [7] [6] SRDS [6] [4] SRDS SRDS2 SRDS2 [0]
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SRDS [0] [2] SRDS SRDS
SD1_ REF_ CLK
AGND_ SRDS
SGND_ SD1_RX SVDD_ SD1_RX SGND_ SRDS SRDS [2] [0] SRDS
SD1_ REF_ CLK
SD1_ PLL_ TPD
AVDD_ SRDS
U
V
W
M
N
P
R
T
SVDD_ SGND_ SGND_ SGND_ SGND_ IRQ[11] DMA_ SRDS SRDS SRDS2 DDONE3 SRDS SRDS
NC
SVDD_ SD1_RX SGND_ SD1_RX SVDD_ SRDS [5] [7] SRDS SRDS
IRQ[10] DMA_ DACK3
SD1_ SGND_ SD1_RX SVDD_ SD1_RX SGND_ IMP_CAL SRDS SRDS [7] [5] SRDS _TX
Y
AA
AB
AC
AD
AE
OVDD [17]
GPOUT [2]
TMS
27
TDO
TCK
TDI
28
AF
AG
AH
Figure 9. MPC8544E Ball Map
4.3
Pin Listings
A downloadable version of the pin list is available in the file AN3547SW.zip on Freescale.com.
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 18
Freescale Semiconductor
Table 7. Pin List—By Bus (continued)
Table 7. Pin List—By Bus Bus
PCI1_AD[31] PCI1_AD[30] PCI1_AD[29] PCI1_AD[28] PCI1_AD[27] PCI1_AD[26] PCI1_AD[25] PCI1_AD[24] PCI1_AD[23] PCI1_AD[22] PCI1_AD[21] PCI1_AD[20] PCI1_AD[19] PCI1_AD[18] PCI1_AD[17] PCI1_AD[16] PCI1_AD[15] PCI1_AD[14] PCI1_AD[13] PCI1_AD[12] PCI1_AD[11] PCI1_AD[10] PCI1_AD[9] PCI1_AD[8] PCI1_AD[7] PCI1_AD[6] PCI1_AD[5] PCI1_AD[4] PCI1_AD[3] PCI1_AD[2] PCI1_AD[1] PCI1_AD[0] PCI1_C_BE[3] PCI1_C_BE[2] PCI1_C_BE[1] PCI1_C_BE[0] PCI1_GNT[4] PCI1_GNT[3] PCI1_GNT[2] PCI1_GNT[1] PCI1_GNT[0] PCI1_IRDY PCI1_PAR PCI1_PERR PCI1_SERR PCI1_STOP
AE8 AD8 AF8 AH12 AG12 AB9 AC9 AE9 AD10 AE10 AC11 AB11 AB12 AC12 AF12 AE11 Y14 AE15 AC15 AB15 AA15 AD16 Y15 AB16 AF18 AE18 AC17 AE19 AD19 AB17 AB18 AA16 AC10 AE12 AA14 AD17 AE7 AG11 AH11 AC8 AE6 AF13 AB14 AE14 AC14 AA13
Bus
DDR SDRAM Memory Interface
Pin
PCI
PCI
Signal
Signal
Pin
PCI1_TRDY PCI1_REQ[4] PCI1_REQ[3] PCI1_REQ[2] PCI1_REQ[1] PCI1_REQ[0] PCI1_CLK PCI1_DEVSEL PCI1_FRAME PCI1_IDSEL MDQ[0] MDQ[1] MDQ[2] MDQ[3] MDQ[4] MDQ[5] MDQ[6] MDQ[7] MDQ[8] MDQ[9] MDQ[10] MDQ[11] MDQ[12] MDQ[13] MDQ[14] MDQ[15] MDQ[16] MDQ[17] MDQ[18] MDQ[19] MDQ[20] MDQ[21] MDQ[22] MDQ[23] MDQ[24] MDQ[25] MDQ[26] MDQ[27] MDQ[28] MDQ[29] MDQ[30] MDQ[31] MDQ[32] MDQ[33] MDQ[34] MDQ[35]
AD13 AF9 AG10 AH10 AD6 AB8 AH26 AC13 AD12 AG6 A26 B26 C22 D21 D25 B25 D22 E21 A24 A23 B20 A20 A25 B24 B21 A21 E19 D19 E16 C16 F19 F18 F17 D16 B18 A18 A15 B14 B19 A19 A16 B15 D1 F3 G1 H2
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
19
Table 7. Pin List—By Bus (continued) Bus
Table 7. Pin List—By Bus (continued) Pin
MDQ[36] MDQ[37] MDQ[38] MDQ[39] MDQ[40] MDQ[41] MDQ[42] MDQ[43] MDQ[44] MDQ[45] MDQ[46] MDQ[47] MDQ[48] MDQ[49] MDQ[50] MDQ[51] MDQ[52] MDQ[53] MDQ[54] MDQ[55] MDQ[56] MDQ[57] MDQ[58] MDQ[59] MDQ[60] MDQ[61] MDQ[62] MDQ[63] MECC[0] MECC[1] MECC[2] MECC[3] MECC[4] MECC[5] MECC[6] MECC[7] MDM[0] MDM[1] MDM[2] MDM[3] MDM[4] MDM[5] MDM[6] MDM[7] MDM[8] MDQS[0]
E4 G5 H3 J4 B2 C3 F2 G2 A2 B3 E1 F1 L5 L4 N3 P3 J3 K4 N4 P4 J1 K1 P1 R1 J2 K2 N1 R2 G12 D14 F11 C11 G14 F14 C13 D12 C25 B23 D18 B17 G4 C2 L3 L2 F13 D24
Bus
DDR SDRAM Memory Interface
DDR SDRAM Memory Interface
Signal
Signal
Pin
MDQS[1] MDQS[2] MDQS[3] MDQS[4] MDQS[5] MDQS[6] MDQS[7] MDQS[8] MDQS[0] MDQS[1] MDQS[2] MDQS[3] MDQS[4] MDQS[5] MDQS[6] MDQS[7] MDQS[8] MA[0] MA[1] MA[2] MA[3] MA[4] MA[5] MA[6] MA[7] MA[8] MA[9] MA[10] MA[11] MA[12] MA[13] MA[14] MA[15] MBA[0] MBA[1] MBA[2] MWE MCAS MRAS MCKE[0] MCKE[1] MCKE[2] MCKE[3] MCS[0] MCS[1] MCS[2]
B22 C18 A17 J5 C1 M4 M2 E13 C23 A22 E17 B16 K5 D2 M3 P2 D13 B7 G8 C8 A10 D9 C10 A11 F9 E9 B12 A5 A12 D11 F7 E10 F10 A4 B5 B13 B4 E7 C5 H10 K10 G10 H9 D3 H6 C4
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 20
Freescale Semiconductor
Table 7. Pin List—By Bus (continued) Bus
Table 7. Pin List—By Bus (continued)
DDR SDRAM Memory Interface
MCS[3] MCK[0] MCK[1] MCK[2] MCK[3] MCK[4] MCK[5] MCK[0] MCK[1] MCK[2] MCK[3] MCK[4] MCK[5] MODT[0] MODT[1] MODT[2] MODT[3] MDIC[0] MDIC[1] TEST_IN TEST_OUT LAD[0] LAD[1] LAD[2] LAD[3] LAD[4] LAD[5] LAD[6] LAD[7] LAD[8] LAD[9] LAD[10] LAD[11] LAD[12] LAD[13] LAD[14] LAD[15] LAD[16] LAD[17] LAD[18] LAD[19] LAD[20] LAD[21] LAD[22] LAD[23] LAD[24]
G6 A9 J11 J6 A8 J13 H8 B9 H11 K6 B8 H13 J8 E5 H7 E6 F6 H15 K15 A13 A6 K22 L21 L22 K23 K24 L24 L25 K25 L28 L27 K28 K27 J28 H28 H27 G27 G26 F28 F26 F25 E28 E27 E26 F24 E24
Bus
DMA
Pin
Local Bus Controller Interface
Local Bus Controller Interface
Signal
Signal
Pin
LAD[25] LAD[26] LAD[27] LAD[28] LAD[29] LAD[30] LAD[31] LDP[0] LDP[1] LDP[2] LDP[3] LA[27] LA[28] LA[29] LA[30] LA[31] LCS[0] LCS[1] LCS[2] LCS[3] LCS[4] LCS5/DMA_DREQ2 LCS6/DMA_DACK2 LCS7/DMA_DDONE2 LWE0/LBS0/LSDDQM[0] LWE1/LBS1/LSDDQM[1] LWE2/LBS2/LSDDQM[2] LWE3/LBS3/LSDDQM[3] LALE LBCTL LGPL0/LSDA10 LGPL1/LSDWE LGPL2/LOE/LSDRAS LGPL3/LSDCAS LGPL4/LGTA/LUPWAIT/LPBSE LGPL5 LCKE LCLK[0] LCLK[1] LCLK[2] LSYNC_IN LSYNC_OUT DMA_DACK[0] DMA_DACK[1] DMA_DREQ[0] DMA_DREQ[1]
C26 G24 E23 G23 F22 G22 G21 K26 G28 B27 E25 L19 K16 K17 H17 G17 K18 G19 H19 H20 G16 H16 J16 L18 J22 H22 H23 H21 J26 J25 J20 K20 G20 H18 L20 K19 L17 H24 J24 H25 D27 D28 Y13 Y12 AA10 AA11
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
21
Table 7. Pin List—By Bus (continued) Bus DM A Gigabit Reference Clock
AA7 Y11 AH15 AG18 AG22 AF17 AD21 AF19 AG17 AF16 AC23 AC22 AC19 AG20 AE27 AE24 AD14 AC7 Y9 T2
TSEC1_RXD[7] TSEC1_RXD[6] TSEC1_RXD[5] TSEC1_RXD[4] TSEC1_RXD[3] TSEC1_RXD[2] TSEC1_RXD[1] TSEC1_RXD[0] TSEC1_TXD[7] TSEC1_TXD[6] TSEC1_TXD[5] TSEC1_TXD[4] TSEC1_TXD[3] TSEC1_TXD[2] TSEC1_TXD[1] TSEC1_TXD[0] TSEC1_COL TSEC1_CRS TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER TSEC1_TX_CLK TSEC1_TX_EN TSEC1_TX_ER
U10 U9 T10 T9 U8 T8 T7 T6 T5 U5 V5 V3 V2 V1 U2 U1 R5 T4 T1 V7 U7 R9 V6 U4 T3
SerDes1
DMA_DDONE[0] DMA_DDONE[1] UDE MCP IRQ[0] IRQ[1] IRQ[2] IRQ[3] IRQ[4] IRQ[5] IRQ[6] IRQ[7] IRQ[8] IRQ[9]/DMA_DREQ3 IRQ[10]/DMA_DACK3 IRQ[11]/DMA_DDONE3 IRQ_OUT EC_MDC EC_MDIO EC_GTX_CLK125
Bus
I2C Interface
Pin
DUART
Three-Speed Ethernet Controller (Gigabit Ethernet 1) Three-Speed Ethernet Controller (Gigabit Ethernet
Signal
Three-Speed Ethernet Controller (Gigabit Ethernet 3)
Programmable Interrupt Controller Ethernet
Table 7. Pin List—By Bus (continued) Signal
Pin
TSEC3_RXD[7] TSEC3_RXD[6] TSEC3_RXD[5] TSEC3_RXD[4] TSEC3_RXD[3] TSEC3_RXD[2] TSEC3_RXD[1] TSEC3_RXD[0] TSEC3_TXD[7] TSEC3_TXD[6] TSEC3_TXD[5] TSEC3_TXD[4] TSEC3_TXD[3] TSEC3_TXD[2] TSEC3_TXD[1] TSEC3_TXD[0] TSEC3_COL TSEC3_CRS TSEC3_GTX_CLK TSEC3_RX_CLK TSEC3_RX_DV TSEC3_RX_ER TSEC3_TX_CLK TSEC3_TX_EN TSEC3_TX_ER UART_CTS[0] UART_CTS[1] UART_RTS[0] UART_RTS[1] UART_SIN[0] UART_SIN[1] UART_SOUT[0] UART_SOUT[1] IIC1_SCL IIC1_SDA IIC2_SCL IIC2_SDA SD1_RX[0] SD1_RX[1] SD1_RX[2] SD1_RX[3] SD1_RX[4] SD1_RX[5] SD1_RX[6] SD1_RX[7] SD1_RX[0]
P11 N11 M11 L11 R8 N10 N9 P10 M7 N7 P7 M8 L7 R6 P6 M6 M9 L9 R7 P9 P8 R11 L10 N6 L8 AH8 AF6 AG8 AG9 AG7 AH6 AH7 AF7 AG21 AH21 AG13 AG14 N28 P26 R28 T26 Y26 AA28 AB26 AC28 N27
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 22
Freescale Semiconductor
Table 7. Pin List—By Bus (continued) Bus
Table 7. Pin List—By Bus (continued)
System Control Debug Cloc k JTAG DFT
P25 R27 T25 Y25 AA27 AB25 AC27 M23 N21 P23 R21 U21 V23 W21 Y23 M22 N20 P22 R20 U20 V22 W20 Y22 V28 U28 U27 T22 T23 AD26 AD1 AB2 AD25 AC1 AA2 AA21 AC4 AA5 AA20 AB4 Y5 AG3 AE2 AF2 AG4 AF4
Ther mal Man age
SD1_RX[1] SD1_RX[2] SD1_RX[3] SD1_RX[4] SD1_RX[5] SD1_RX[6] SD1_RX[7] SD1_TX[0] SD1_TX[1] SD1_TX[2] SD1_TX[3] SD1_TX[4] SD1_TX[5] SD1_TX[6] SD1_TX[7] SD1_TX[0] SD1_TX[1] SD1_TX[2] SD1_TX[3] SD1_TX[4] SD1_TX[5] SD1_TX[6] SD1_TX[7] SD1_PLL_TPD SD1_REF_CLK SD1_REF_CLK SD1_TST_CLK SD1_TST_CLK SD2_RX[0] SD2_RX[2] SD2_RX[3] SD2_RX[0] SD2_RX[2] SD2_RX[3] SD2_TX[0] SD2_TX[2] SD2_TX[3] SD2_TX[0] SD2_TX[2] SD2_TX[3] SD2_PLL_TPD SD2_REF_CLK SD2_REF_CLK SD2_TST_CLK SD2_TST_CLK
Bus
General-Purpose Input
SerDes2
Pin
General-Purpose Output
SerDes1
Signal
Signal
Pin
GPOUT[0] GPOUT[1] GPOUT[2] GPOUT[3] GPOUT[4] GPOUT[5] GPOUT[6] GPOUT[7] GPIN[0] GPIN[1] GPIN[2] GPIN[3] GPIN[4] GPIN[5] GPIN[6] GPIN[7] HRESET HRESET_REQ SRESET CKSTP_IN CKSTP_OUT TRIG_IN TRIG_OUT/READY/QUIESCE MSRCID[0] MSRCID[1] MSRCID[2] MSRCID[3] MSRCID[4] MDVAL CLK_OUT RTC SYSCLK TCK TDI TDO TMS TRST L1_TSTCLK L2_TSTCLK LSSD_MODE TEST_SEL TEMP_ANODE TEMP_CATHODE
AF22 AH23 AG27 AH25 AF21 AF25 AG26 AF26 AH24 AG24 AD23 AE21 AD22 AF23 AG25 AE20 AG16 AG15 AG19 AH5 AA12 AC5 AB5 Y7 W9 AA9 AB6 AD5 Y8 AE16 AF15 AH16 AG28 AH28 AF28 AH27 AH22 AC20 AE17 AH19 AH13 Y3 AA3
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
23
Table 7. Pin List—By Bus (continued) Bus
Table 7. Pin List—By Bus (continued)
Power Management
Pin
ASLEEP
AH17
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
D5 M10 F4 D26 D23 C12 C15 E20 D8 B10 E3 J14 K21 F8 A3 F16 E12 E15 D17 L1 F21 H1 G13 G15 G18 C6 A14 A7 G25 H4 C20 J12 J15 J17 F27 M5 J27 K11 L26
Bus
Power and Ground Signals
Power and Ground Signals
Signal
Signal
Pin
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND OVDD OVDD OVDD OVDD OVDD
K7 K8 L12 L15 M14 M16 M18 N13 N15 N17 N2 P5 P14 P16 P18 R13 R15 R17 T14 T16 T18 U13 U15 U17 AA8 U6 Y10 AC21 AA17 AC16 V4 AD7 AD18 AE23 AF11 AF14 AG23 AH9 A27 B28 C27 Y16 AB7 AB10 AB13 AC6
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 24
Freescale Semiconductor
Table 7. Pin List—By Bus (continued) Bus
Table 7. Pin List—By Bus (continued) Pin
OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD LVDD LVDD TVDD TVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD
AC18 AD9 AD11 AE13 AD15 AD20 AE5 AE22 AF10 AF20 AF24 AF27 R4 U3 N8 R10 B1 B11 C7 C9 C14 C17 D4 D6 R3 D15 E2 E8 C24 E18 F5 E14 C21 G3 G7 G9 G11 H5 H12 E22 F15 J10 K3 K12 K14 H14
Bus
Power and Ground Signals
Power and Ground Signals
Signal
Signal
Pin
GVDD GVDD GVDD GVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD BVDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS
D20 E11 M1 N5 L23 J18 J19 F20 F23 H26 J21 J23 L16 L14 M13 M15 M17 N12 N14 N16 N18 P13 P15 P17 R12 R14 R16 R18 T13 T15 T17 U12 U14 U16 U18 M27 N25 P28 R24 R26 T24 T27 U25 W24 W26 Y24
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
25
Table 7. Pin List—By Bus (continued) Bus
Table 7. Pin List—By Bus (continued)
Y27 AA25 AB28 AD27 AB1 AC26 AD2 AE26 AG2 M21 N23 P20 R22 T20 U23 V21 W22 Y20 Y6 AA6 AA23 AF5 AG5 M20 M24 N22 P21 R23 T21 U22 V20 W23 Y21 Y4 AA4 AA22 AD4 AE4 AH4 M28 N26 P24 P27 R25 T28 U24
No Connect Pins
SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS SVDD_SRDS2 SVDD_SRDS2 SVDD_SRDS2 SVDD_SRDS2 SVDD_SRDS2 XVDD_SRDS XVDD_SRDS XVDD_SRDS XVDD_SRDS XVDD_SRDS XVDD_SRDS XVDD_SRDS XVDD_SRDS XVDD_SRDS XVDD_SRDS2 XVDD_SRDS2 XVDD_SRDS2 XVDD_SRDS2 XVDD_SRDS2 XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS XGND_SRDS2 XGND_SRDS2 XGND_SRDS2 XGND_SRDS2 XGND_SRDS2 XGND_SRDS2 SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS
Bus
Analog Signals
Pin
Power and Ground Signals
Power and Ground Signals
Signal
Signal
Pin
SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS SGND_SRDS AGND_SRDS SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 SGND_SRDS2 AGND_SRDS2 AVDD_LBIU AVDD_PCI1 AVDD_CORE AVDD_PLAT AVDD_SRDS AVDD_SRDS2 SENSEVDD SENSEVSS MVREF SD1_IMP_CAL_RX SD1_IMP_CAL_TX SD1_PLL_TPA SD2_IMP_CAL_RX SD2_IMP_CAL_TX SD2_PLL_TPA NC NC NC NC NC NC
U26 V24 W25 Y28 AA24 AA26 AB24 AB27 AC24 AD28 V27 Y2 AA1 AB3 AC2 AC3 AC25 AD3 AD24 AE3 AE1 AE25 AF3 AH2 AF1 C28 AH20 AH14 AH18 W28 AG1 W11 W10 A28 M26 AE28 V26 AH3 Y1 AH1 C19 D7 D10 K13 L6 K9
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 26
Freescale Semiconductor
Table 7. Pin List—By Bus (continued) Bus
Table 7. Pin List—By Bus (continued) Pin
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
B6 F12 J7 M19 M25 N19 N24 P19 R19 AB19 T12 W3 M12 W5 P12 T19 W1 W7 L13 U19 W4 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W2 W6 W8 T11 U11 W12 W13 W14 W15 W16 W17 W18 W19
Bus
No Connect Pins
No Connect Pins
Signal
Signal
Pin
NC NC NC NC NC NC NC NC NC NC NC NC
W27 V25 Y17 Y18 Y19 AA18 AA19 AB20 AB21 AB22 AB23 J9
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
27
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal Signal
Pin
Signal
Pin
AGND_SRDS
V27
GND
D23
AGND_SRDS2
AF1
GND
C12
ASLEEP
AH17
GND
C15
AVDD_CORE
AH14
GND
E20
AVDD_LBIU
C28
GND
D8
AVDD_PCI1
AH20
GND
B10
AVDD_PLAT
AH18
GND
E3
AVDD_SRDS
W28
GND
J14
AVDD_SRDS2
AG1
GND
K21
BVDD
L23
GND
F8
BVDD
J18
GND
A3
BVDD
J19
GND
F16
BVDD
F20
GND
E12
BVDD
F23
GND
E15
BVDD
H26
GND
D17
BVDD
J21
GND
L1
BVDD
J23
GND
F21
CKSTP_IN
AH5
GND
H1
CKSTP_OUT
AA12
GND
G13
CLK_OUT
AE16
GND
G15
DMA_DACK[0]
Y13
GND
G18
DMA_DACK[1]
Y12
GND
C6
DMA_DDONE[0]
AA7
GND
A14
DMA_DDONE[1]
Y11
GND
A7
DMA_DREQ[0]
AA10
GND
G25
DMA_DREQ[1]
AA11
GND
H4
EC_GTX_CLK125
T2
GND
C20
EC_MDC
AC7
GND
J12
EC_MDIO
Y9
GND
J15
GND
D5
GND
J17
GND
M10
GND
F27
GND
F4
GND
M5
GND
D26
GND
J27
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 28
Freescale Semiconductor
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
GND
K11
GND
AD7
GND
L26
GND
AD18
GND
K7
GND
AE23
GND
K8
GND
AF11
GND
L12
GND
AF14
GND
L15
GND
AG23
GND
M14
GND
AH9
GND
M16
GND
A27
GND
M18
GND
B28
GND
N13
GND
C27
GND
N15
GPIN[0]
AH24
GND
N17
GPIN[1]
AG24
GND
N2
GPIN[2]
AD23
GND
P5
GPIN[3]
AE21
GND
P14
GPIN[4]
AD22
GND
P16
GPIN[5]
AF23
GND
P18
GPIN[6]
AG25
GND
R13
GPIN[7]
AE20
GND
R15
GPOUT[0]
AF22
GND
R17
GPOUT[1]
AH23
GND
T14
GPOUT[2]
AG27
GND
T16
GPOUT[3]
AH25
GND
T18
GPOUT[4]
AF21
GND
U13
GPOUT[5]
AF25
GND
U15
GPOUT[6]
AG26
GND
U17
GPOUT[7]
AF26
GND
AA8
GVDD
B1
GND
U6
GVDD
B11
GND
Y10
GVDD
C7
GND
AC21
GVDD
C9
GND
AA17
GVDD
C14
GND
AC16
GVDD
C17
GND
V4
GVDD
D4
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
29
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
GVDD
D6
IRQ[0]
AG22
GVDD
R3
IRQ[1]
AF17
GVDD
D15
IRQ[10]/DMA_DACK3
AE27
GVDD
E2
IRQ[11]/DMA_DDONE3
AE24
GVDD
E8
IRQ[2]
AD21
GVDD
C24
IRQ[3]
AF19
GVDD
E18
IRQ[4]
AG17
GVDD
F5
IRQ[5]
AF16
GVDD
E14
IRQ[6]
AC23
GVDD
C21
IRQ[7]
AC22
GVDD
G3
IRQ[8]
AC19
GVDD
G7
IRQ[9]/DMA_DREQ3
AG20
GVDD
G9
IRQ_OUT
AD14
GVDD
G11
L1_TSTCLK
AC20
GVDD
H5
L2_TSTCLK
AE17
GVDD
H12
LA[27]
L19
GVDD
E22
LA[28]
K16
GVDD
F15
LA[29]
K17
GVDD
J10
LA[30]
H17
GVDD
K3
LA[31]
G17
GVDD
K12
LAD[0]
K22
GVDD
K14
LAD[1]
L21
GVDD
H14
LAD[10]
K28
GVDD
D20
LAD[11]
K27
GVDD
E11
LAD[12]
J28
GVDD
M1
LAD[13]
H28
GVDD
N5
LAD[14]
H27
HRESET
AG16
LAD[15]
G27
HRESET_REQ
AG15
LAD[16]
G26
IIC1_SCL
AG21
LAD[17]
F28
IIC1_SDA
AH21
LAD[18]
F26
IIC2_SCL
AG13
LAD[19]
F25
IIC2_SDA
AG14
LAD[2]
L22
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 30
Freescale Semiconductor
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
LAD[20]
E28
LDP[0]
K26
LAD[21]
E27
LDP[1]
G28
LAD[22]
E26
LDP[2]
B27
LAD[23]
F24
LDP[3]
E25
LAD[24]
E24
LGPL0/LSDA10
J20
LAD[25]
C26
LGPL1/LSDWE
K20
LAD[26]
G24
LGPL2/LOE/LSDRAS
G20
LAD[27]
E23
LGPL3/LSDCAS
H18
LAD[28]
G23
LGPL4/LGTA/LUPWAIT/LPBSE
L20
LAD[29]
F22
LGPL5
K19
LAD[3]
K23
LSSD_MODE
AH19
LAD[30]
G22
LSYNC_IN
D27
LAD[31]
G21
LSYNC_OUT
D28
LAD[4]
K24
LVDD
R4
LAD[5]
L24
LVDD
U3
LAD[6]
L25
LWE0/LBS0/LSDDQM[0]
J22
LAD[7]
K25
LWE1/LBS1/LSDDQM[1]
H22
LAD[8]
L28
LWE2/LBS2/LSDDQM[2]
H23
LAD[9]
L27
LWE3/LBS3/LSDDQM[3]
H21
LALE
J26
MA[0]
B7
LBCTL
J25
MA[1]
G8
LCKE
L17
MA[10]
A5
LCLK[0]
H24
MA[11]
A12
LCLK[1]
J24
MA[12]
D11
LCLK[2]
H25
MA[13]
F7
LCS[0]
K18
MA[14]
E10
LCS[1]
G19
MA[15]
F10
LCS[2]
H19
MA[2]
C8
LCS[3]
H20
MA[3]
A10
LCS[4]
G16
MA[4]
D9
LCS5/DMA_DREQ2
H16
MA[5]
C10
LCS6/DMA_DACK2
J16
MA[6]
A11
LCS7/DMA_DDONE2
L18
MA[7]
F9
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
31
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
MA[8]
E9
MDM[4]
G4
MA[9]
B12
MDM[5]
C2
MBA[0]
A4
MDM[6]
L3
MBA[1]
B5
MDM[7]
L2
MBA[2]
B13
MDM[8]
F13
MCAS
E7
MDQ[0]
A26
MCK[0]
A9
MDQ[1]
B26
MCK[0]
B9
MDQ[10]
B20
MCK[1]
J11
MDQ[11]
A20
MCK[1]
H11
MDQ[12]
A25
MCK[2]
J6
MDQ[13]
B24
MCK[2]
K6
MDQ[14]
B21
MCK[3]
A8
MDQ[15]
A21
MCK[3]
B8
MDQ[16]
E19
MCK[4]
J13
MDQ[17]
D19
MCK[4]
H13
MDQ[18]
E16
MCK[5]
H8
MDQ[19]
C16
MCK[5]
J8
MDQ[2]
C22
MCKE[0]
H10
MDQ[20]
F19
MCKE[1]
K10
MDQ[21]
F18
MCKE[2]
G10
MDQ[22]
F17
MCKE[3]
H9
MDQ[23]
D16
MCP
AG18
MDQ[24]
B18
MCS[0]
D3
MDQ[25]
A18
MCS[1]
H6
MDQ[26]
A15
MCS[2]
C4
MDQ[27]
B14
MCS[3]
G6
MDQ[28]
B19
MDIC[0]
H15
MDQ[29]
A19
MDIC[1]
K15
MDQ[3]
D21
MDM[0]
C25
MDQ[30]
A16
MDM[1]
B23
MDQ[31]
B15
MDM[2]
D18
MDQ[32]
D1
MDM[3]
B17
MDQ[33]
F3
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 32
Freescale Semiconductor
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
MDQ[34]
G1
MDQ[7]
E21
MDQ[35]
H2
MDQ[8]
A24
MDQ[36]
E4
MDQ[9]
A23
MDQ[37]
G5
MDQS[0]
C23
MDQ[38]
H3
MDQS[0]
D24
MDQ[39]
J4
MDQS[1]
A22
MDQ[4]
D25
MDQS[1]
B22
MDQ[40]
B2
MDQS[2]
E17
MDQ[41]
C3
MDQS[2]
C18
MDQ[42]
F2
MDQS[3]
B16
MDQ[43]
G2
MDQS[3]
A17
MDQ[44]
A2
MDQS[4]
K5
MDQ[45]
B3
MDQS[4]
J5
MDQ[46]
E1
MDQS[5]
D2
MDQ[47]
F1
MDQS[5]
C1
MDQ[48]
L5
MDQS[6]
M3
MDQ[49]
L4
MDQS[6]
M4
MDQ[5]
B25
MDQS[7]
P2
MDQ[50]
N3
MDQS[7]
M2
MDQ[51]
P3
MDQS[8]
D13
MDQ[52]
J3
MDQS[8]
E13
MDQ[53]
K4
MDVAL
Y8
MDQ[54]
N4
MECC[0]
G12
MDQ[55]
P4
MECC[1]
D14
MDQ[56]
J1
MECC[2]
F11
MDQ[57]
K1
MECC[3]
C11
MDQ[58]
P1
MECC[4]
G14
MDQ[59]
R1
MECC[5]
F14
MDQ[6]
D22
MECC[6]
C13
MDQ[60]
J2
MECC[7]
D12
MDQ[61]
K2
MODT[0]
E5
MDQ[62]
N1
MODT[1]
H7
MDQ[63]
R2
MODT[2]
E6
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
33
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
MODT[3]
F6
NC
L13
MRAS
C5
NC
U19
MSRCID[0]
Y7
NC
W4
MSRCID[1]
W9
NC
V8
MSRCID[2]
AA9
NC
V9
MSRCID[3]
AB6
NC
V10
MSRCID[4]
AD5
NC
V11
MVREF
A28
NC
V12
MWE
B4
NC
V13
NC
C19
NC
V14
NC
D7
NC
V15
NC
D10
NC
V16
NC
K13
NC
V17
NC
L6
NC
V18
NC
K9
NC
V19
NC
B6
NC
W2
NC
F12
NC
W6
NC
J7
NC
W8
NC
M19
NC
T11
NC
M25
NC
U11
NC
N19
NC
W12
NC
N24
NC
W13
NC
P19
NC
W14
NC
R19
NC
W15
NC
AB19
NC
W16
NC
T12
NC
W17
NC
W3
NC
W18
NC
M12
NC
W19
NC
W5
NC
W27
NC
P12
NC
V25
NC
T19
NC
Y17
NC
W1
NC
Y18
NC
W7
NC
Y19
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 34
Freescale Semiconductor
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
NC
AA18
PCI1_AD[17]
AF12
NC
AA19
PCI1_AD[18]
AC12
NC
AB20
PCI1_AD[19]
AB12
NC
AB21
PCI1_AD[2]
AB17
NC
AB22
PCI1_AD[20]
AB11
NC
AB23
PCI1_AD[21]
AC11
NC
J9
PCI1_AD[22]
AE10
OVDD
Y16
PCI1_AD[23]
AD10
OVDD
AB7
PCI1_AD[24]
AE9
OVDD
AB10
PCI1_AD[25]
AC9
OVDD
AB13
PCI1_AD[26]
AB9
OVDD
AC6
PCI1_AD[27]
AG12
OVDD
AC18
PCI1_AD[28]
AH12
OVDD
AD9
PCI1_AD[29]
AF8
OVDD
AD11
PCI1_AD[3]
AD19
OVDD
AE13
PCI1_AD[30]
AD8
OVDD
AD15
PCI1_AD[31]
AE8
OVDD
AD20
PCI1_AD[4]
AE19
OVDD
AE5
PCI1_AD[5]
AC17
OVDD
AE22
PCI1_AD[6]
AE18
OVDD
AF10
PCI1_AD[7]
AF18
OVDD
AF20
PCI1_AD[8]
AB16
OVDD
AF24
PCI1_AD[9]
Y15
OVDD
AF27
PCI1_C_BE[0]
AD17
PCI1_AD[0]
AA16
PCI1_C_BE[1]
AA14
PCI1_AD[1]
AB18
PCI1_C_BE[2]
AE12
PCI1_AD[10]
AD16
PCI1_C_BE[3]
AC10
PCI1_AD[11]
AA15
PCI1_CLK
AH26
PCI1_AD[12]
AB15
PCI1_DEVSEL
AC13
PCI1_AD[13]
AC15
PCI1_FRAME
AD12
PCI1_AD[14]
AE15
PCI1_GNT[0]
AE6
PCI1_AD[15]
Y14
PCI1_GNT[1]
AC8
PCI1_AD[16]
AE11
PCI1_GNT[2]
AH11
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
35
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
PCI1_GNT[3]
AG11
SD1_RX[6]
AB26
PCI1_GNT[4]
AE7
SD1_RX[6]
AB25
PCI1_IDSEL
AG6
SD1_RX[7]
AC28
PCI1_IRDY
AF13
SD1_RX[7]
AC27
PCI1_PAR
AB14
SD1_TST_CLK
T22
PCI1_PERR
AE14
SD1_TST_CLK
T23
PCI1_REQ[0]
AB8
SD1_TX[0]
M23
PCI1_REQ[1]
AD6
SD1_TX[0]
M22
PCI1_REQ[2]
AH10
SD1_TX[1]
N21
PCI1_REQ[3]
AG10
SD1_TX[1]
N20
PCI1_REQ[4]
AF9
SD1_TX[2]
P23
PCI1_SERR
AC14
SD1_TX[2]
P22
PCI1_STOP
AA13
SD1_TX[3]
R21
PCI1_TRDY
AD13
SD1_TX[3]
R20
RTC
AF15
SD1_TX[4]
U21
SD1_IMP_CAL_RX
M26
SD1_TX[4]
U20
SD1_IMP_CAL_TX
AE28
SD1_TX[5]
V23
SD1_PLL_TPA
V26
SD1_TX[5]
V22
SD1_PLL_TPD
V28
SD1_TX[6]
W21
SD1_REF_CLK
U28
SD1_TX[6]
W20
SD1_REF_CLK
U27
SD1_TX[7]
Y23
SD1_RX[0]
N28
SD1_TX[7]
Y22
SD1_RX[0]
N27
SD2_IMP_CAL_RX
AH3
SD1_RX[1]
P26
SD2_IMP_CAL_TX
Y1
SD1_RX[1]
P25
SD2_PLL_TPA
AH1
SD1_RX[2]
R28
SD2_PLL_TPD
AG3
SD1_RX[2]
R27
SD2_REF_CLK
AE2
SD1_RX[3]
T26
SD2_REF_CLK
AF2
SD1_RX[3]
T25
SD2_RX[0]
AD26
SD1_RX[4]
Y26
SD2_RX[0]
AD25
SD1_RX[4]
Y25
SD2_RX[2]
AD1
SD1_RX[5]
AA28
SD2_RX[2]
AC1
SD1_RX[5]
AA27
SD2_RX[3]
AB2
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 36
Freescale Semiconductor
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
SD2_RX[3]
AA2
SGND_SRDS2
AC25
SD2_TST_CLK
AG4
SGND_SRDS2
AD3
SD2_TST_CLK
AF4
SGND_SRDS2
AD24
SD2_TX[0]
AA21
SGND_SRDS2
AE3
SD2_TX[0]
AA20
SGND_SRDS2
AE1
SD2_TX[2]
AC4
SGND_SRDS2
AE25
SD2_TX[2]
AB4
SGND_SRDS2
AF3
SD2_TX[3]
AA5
SGND_SRDS2
AH2
SD2_TX[3]
Y5
SRESET
AG19
SENSEVDD
W11
SVDD_SRDS
M27
SENSEVSS
W10
SVDD_SRDS
N25
SGND_SRDS
M28
SVDD_SRDS
P28
SGND_SRDS
N26
SVDD_SRDS
R24
SGND_SRDS
P24
SVDD_SRDS
R26
SGND_SRDS
P27
SVDD_SRDS
T24
SGND_SRDS
R25
SVDD_SRDS
T27
SGND_SRDS
T28
SVDD_SRDS
U25
SGND_SRDS
U24
SVDD_SRDS
W24
SGND_SRDS
U26
SVDD_SRDS
W26
SGND_SRDS
V24
SVDD_SRDS
Y24
SGND_SRDS
W25
SVDD_SRDS
Y27
SGND_SRDS
Y28
SVDD_SRDS
AA25
SGND_SRDS
AA24
SVDD_SRDS
AB28
SGND_SRDS
AA26
SVDD_SRDS
AD27
SGND_SRDS
AB24
SVDD_SRDS2
AB1
SGND_SRDS
AB27
SVDD_SRDS2
AC26
SGND_SRDS
AC24
SVDD_SRDS2
AD2
SGND_SRDS
AD28
SVDD_SRDS2
AE26
SGND_SRDS2
Y2
SVDD_SRDS2
AG2
SGND_SRDS2
AA1
SYSCLK
AH16
SGND_SRDS2
AB3
TCK
AG28
SGND_SRDS2
AC2
TDI
AH28
SGND_SRDS2
AC3
TDO
AF28
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
37
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
TEMP_ANODE
Y3
TSEC1_TXD[7]
T5
TEMP_CATHODE
AA3
TSEC3_COL
M9
TEST_IN
A13
TSEC3_CRS
L9
TEST_OUT
A6
TSEC3_GTX_CLK
R7
TEST_SEL
AH13
TSEC3_RX_CLK
P9
TMS
AH27
TSEC3_RX_DV
P8
TRIG_IN
AC5
TSEC3_RX_ER
R11
TRIG_OUT/READY/QUIESCE
AB5
TSEC3_RXD[0]
P10
TRST
AH22
TSEC3_RXD[1]
N9
TSEC1_COL
R5
TSEC3_RXD[2]
N10
TSEC1_CRS
T4
TSEC3_RXD[3]
R8
TSEC1_GTX_CLK
T1
TSEC3_RXD[4]
L11
TSEC1_RX_CLK
V7
TSEC3_RXD[5]
M11
TSEC1_RX_DV
U7
TSEC3_RXD[6]
N11
TSEC1_RX_ER
R9
TSEC3_RXD[7]
P11
TSEC1_RXD[0]
T6
TSEC3_TX_CLK
L10
TSEC1_RXD[1]
T7
TSEC3_TX_EN
N6
TSEC1_RXD[2]
T8
TSEC3_TX_ER
L8
TSEC1_RXD[3]
U8
TSEC3_TXD[0]
M6
TSEC1_RXD[4]
T9
TSEC3_TXD[1]
P6
TSEC1_RXD[5]
T10
TSEC3_TXD[2]
R6
TSEC1_RXD[6]
U9
TSEC3_TXD[3]
L7
TSEC1_RXD[7]
U10
TSEC3_TXD[4]
M8
TSEC1_TX_CLK
V6
TSEC3_TXD[5]
P7
TSEC1_TX_EN
U4
TSEC3_TXD[6]
N7
TSEC1_TX_ER
T3
TSEC3_TXD[7]
M7
TSEC1_TXD[0]
U1
TVDD
N8
TSEC1_TXD[1]
U2
TVDD
R10
TSEC1_TXD[2]
V1
UART_CTS[0]
AH8
TSEC1_TXD[3]
V2
UART_CTS[1]
AF6
TSEC1_TXD[4]
V3
UART_RTS[0]
AG8
TSEC1_TXD[5]
V5
UART_RTS[1]
AG9
TSEC1_TXD[6]
U5
UART_SIN[0]
AG7
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 38
Freescale Semiconductor
Table 8. Pin List—By Signal (continued)
Table 8. Pin List—By Signal (continued)
Signal
Pin
Signal
Pin
UART_SIN[1]
AH6
XGND_SRDS
U22
UART_SOUT[0]
AH7
XGND_SRDS
V20
UART_SOUT[1]
AF7
XGND_SRDS
W23
UDE
AH15
XGND_SRDS
Y21
VDD
L16
XGND_SRDS2
Y4
VDD
L14
XGND_SRDS2
AA4
VDD
M13
XGND_SRDS2
AA22
VDD
M15
XGND_SRDS2
AD4
VDD
M17
XGND_SRDS2
AE4
VDD
N12
XGND_SRDS2
AH4
VDD
N14
XVDD_SRDS
M21
VDD
N16
XVDD_SRDS
N23
VDD
N18
XVDD_SRDS
P20
VDD
P13
XVDD_SRDS
R22
VDD
P15
XVDD_SRDS
T20
VDD
P17
XVDD_SRDS
U23
VDD
R12
XVDD_SRDS
V21
VDD
R14
XVDD_SRDS
W22
VDD
R16
XVDD_SRDS
Y20
VDD
R18
XVDD_SRDS2
Y6
VDD
T13
XVDD_SRDS2
AA6
VDD
T15
XVDD_SRDS2
AA23
VDD
T17
XVDD_SRDS2
AF5
VDD
U12
XVDD_SRDS2
AG5
VDD
U14
VDD
U16
VDD
U18
XGND_SRDS
M20
XGND_SRDS
M24
XGND_SRDS
N22
XGND_SRDS
P21
XGND_SRDS
R23
XGND_SRDS
T21
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
39
Table 9. Pin List—By Pin Number
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
MDQ[44]
A2
MA[0]
B7
GND
A3
MCK[3]
B8
MBA[0]
A4
MCK[0]
B9
MA[10]
A5
GND
B10
TEST_OUT
A6
GVDD
B11
GND
A7
MA[9]
B12
MCK[3]
A8
MBA[2]
B13
MCK[0]
A9
MDQ[27]
B14
MA[3]
A10
MDQ[31]
B15
MA[6]
A11
MDQS[3]
B16
MA[11]
A12
MDM[3]
B17
TEST_IN
A13
MDQ[24]
B18
GND
A14
MDQ[28]
B19
MDQ[26]
A15
MDQ[10]
B20
MDQ[30]
A16
MDQ[14]
B21
MDQS[3]
A17
MDQS[1]
B22
MDQ[25]
A18
MDM[1]
B23
MDQ[29]
A19
MDQ[13]
B24
MDQ[11]
A20
MDQ[5]
B25
MDQ[15]
A21
MDQ[1]
B26
MDQS[1]
A22
LDP[2]
B27
MDQ[9]
A23
GND
B28
MDQ[8]
A24
MDQS[5]
C1
MDQ[12]
A25
MDM[5]
C2
MDQ[0]
A26
MDQ[41]
C3
GND
A27
MCS[2]
C4
MVREF
A28
MRAS
C5
GVDD
B1
GND
C6
MDQ[40]
B2
GVDD
C7
MDQ[45]
B3
MA[2]
C8
MWE
B4
GVDD
C9
MBA[1]
B5
MA[5]
C10
NC
B6
MECC[3]
C11
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 40
Freescale Semiconductor
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
GND
C12
GND
D17
MECC[6]
C13
MDM[2]
D18
GVDD
C14
MDQ[17]
D19
GND
C15
GVDD
D20
MDQ[19]
C16
MDQ[3]
D21
GVDD
C17
MDQ[6]
D22
MDQS[2]
C18
GND
D23
NC
C19
MDQS[0]
D24
GND
C20
MDQ[4]
D25
GVDD
C21
GND
D26
MDQ[2]
C22
LSYNC_IN
D27
MDQS[0]
C23
LSYNC_OUT
D28
GVDD
C24
MDQ[46]
E1
MDM[0]
C25
GVDD
E2
LAD[25]
C26
GND
E3
GND
C27
MDQ[36]
E4
AVDD_LBIU
C28
MODT[0]
E5
MDQ[32]
D1
MODT[2]
E6
MDQS[5]
D2
MCAS
E7
MCS[0]
D3
GVDD
E8
GVDD
D4
MA[8]
E9
GND
D5
MA[14]
E10
GVDD
D6
GVDD
E11
NC
D7
GND
E12
GND
D8
MDQS[8]
E13
MA[4]
D9
GVDD
E14
NC
D10
GND
E15
MA[12]
D11
MDQ[18]
E16
MECC[7]
D12
MDQS[2]
E17
MDQS[8]
D13
GVDD
E18
MECC[1]
D14
MDQ[16]
E19
GVDD
D15
GND
E20
MDQ[23]
D16
MDQ[7]
E21
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
41
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
GVDD
E22
GND
F27
LAD[27]
E23
LAD[17]
F28
LAD[24]
E24
MDQ[34]
G1
LDP[3]
E25
MDQ[43]
G2
LAD[22]
E26
GVDD
G3
LAD[21]
E27
MDM[4]
G4
LAD[20]
E28
MDQ[37]
G5
MDQ[47]
F1
MCS[3]
G6
MDQ[42]
F2
GVDD
G7
MDQ[33]
F3
MA[1]
G8
GND
F4
GVDD
G9
GVDD
F5
MCKE[2]
G10
MODT[3]
F6
GVDD
G11
MA[13]
F7
MECC[0]
G12
GND
F8
GND
G13
MA[7]
F9
MECC[4]
G14
MA[15]
F10
GND
G15
MECC[2]
F11
LCS[4]
G16
NC
F12
LA[31]
G17
MDM[8]
F13
GND
G18
MECC[5]
F14
LCS[1]
G19
GVDD
F15
LGPL2/LOE/LSDRAS
G20
GND
F16
LAD[31]
G21
MDQ[22]
F17
LAD[30]
G22
MDQ[21]
F18
LAD[28]
G23
MDQ[20]
F19
LAD[26]
G24
BVDD
F20
GND
G25
GND
F21
LAD[16]
G26
LAD[29]
F22
LAD[15]
G27
BVDD
F23
LDP[1]
G28
LAD[23]
F24
GND
H1
LAD[19]
F25
MDQ[35]
H2
LAD[18]
F26
MDQ[38]
H3
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 42
Freescale Semiconductor
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
GND
H4
NC
J9
GVDD
H5
GVDD
J10
MCS[1]
H6
MCK[1]
J11
MODT[1]
H7
GND
J12
MCK[5]
H8
MCK[4]
J13
MCKE[3]
H9
GND
J14
MCKE[0]
H10
GND
J15
MCK[1]
H11
LCS6/DMA_DACK2
J16
GVDD
H12
GND
J17
MCK[4]
H13
BVDD
J18
GVDD
H14
BVDD
J19
MDIC[0]
H15
LGPL0/LSDA10
J20
LCS5/DMA_DREQ2
H16
BVDD
J21
LA[30]
H17
LWE0/LBS0/LSDDQM[0]
J22
LGPL3/LSDCAS
H18
BVDD
J23
LCS[2]
H19
LCLK[1]
J24
LCS[3]
H20
LBCTL
J25
LWE3/LBS3/LSDDQM[3]
H21
LALE
J26
LWE1/LBS1/LSDDQM[1]
H22
GND
J27
LWE2/LBS2/LSDDQM[2]
H23
LAD[12]
J28
LCLK[0]
H24
MDQ[57]
K1
LCLK[2]
H25
MDQ[61]
K2
BVDD
H26
GVDD
K3
LAD[14]
H27
MDQ[53]
K4
LAD[13]
H28
MDQS[4]
K5
MDQ[56]
J1
MCK[2]
K6
MDQ[60]
J2
GND
K7
MDQ[52]
J3
GND
K8
MDQ[39]
J4
NC
K9
MDQS[4]
J5
MCKE[1]
K10
MCK[2]
J6
GND
K11
NC
J7
GVDD
K12
MCK[5]
J8
NC
K13
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
43
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
GVDD
K14
LA[27]
L19
MDIC[1]
K15
LGPL4/LGTA/LUPWAIT/LPBSE
L20
LA[28]
K16
LAD[1]
L21
LA[29]
K17
LAD[2]
L22
LCS[0]
K18
BVDD
L23
LGPL5
K19
LAD[5]
L24
LGPL1/LSDWE
K20
LAD[6]
L25
GND
K21
GND
L26
LAD[0]
K22
LAD[9]
L27
LAD[3]
K23
LAD[8]
L28
LAD[4]
K24
GVDD
M1
LAD[7]
K25
MDQS[7]
M2
LDP[0]
K26
MDQS[6]
M3
LAD[11]
K27
MDQS[6]
M4
LAD[10]
K28
GND
M5
GND
L1
TSEC3_TXD[0]
M6
MDM[7]
L2
TSEC3_TXD[7]
M7
MDM[6]
L3
TSEC3_TXD[4]
M8
MDQ[49]
L4
TSEC3_COL
M9
MDQ[48]
L5
GND
M10
NC
L6
TSEC3_RXD[5]
M11
TSEC3_TXD[3]
L7
NC
M12
TSEC3_TX_ER
L8
VDD
M13
TSEC3_CRS
L9
GND
M14
TSEC3_TX_CLK
L10
VDD
M15
TSEC3_RXD[4]
L11
GND
M16
GND
L12
VDD
M17
NC
L13
GND
M18
VDD
L14
NC
M19
GND
L15
XGND_SRDS
M20
VDD
L16
XVDD_SRDS
M21
LCKE
L17
SD1_TX[0]
M22
LCS7/DMA_DDONE2
L18
SD1_TX[0]
M23
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 44
Freescale Semiconductor
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
XGND_SRDS
M24
MDQ[58]
P1
NC
M25
MDQS[7]
P2
SD1_IMP_CAL_RX
M26
MDQ[51]
P3
SVDD_SRDS
M27
MDQ[55]
P4
SGND_SRDS
M28
GND
P5
MDQ[62]
N1
TSEC3_TXD[1]
P6
GND
N2
TSEC3_TXD[5]
P7
MDQ[50]
N3
TSEC3_RX_DV
P8
MDQ[54]
N4
TSEC3_RX_CLK
P9
GVDD
N5
TSEC3_RXD[0]
P10
TSEC3_TX_EN
N6
TSEC3_RXD[7]
P11
TSEC3_TXD[6]
N7
NC
P12
TVDD
N8
VDD
P13
TSEC3_RXD[1]
N9
GND
P14
TSEC3_RXD[2]
N10
VDD
P15
TSEC3_RXD[6]
N11
GND
P16
VDD
N12
VDD
P17
GND
N13
GND
P18
VDD
N14
NC
P19
GND
N15
XVDD_SRDS
P20
VDD
N16
XGND_SRDS
P21
GND
N17
SD1_TX[2]
P22
VDD
N18
SD1_TX[2]
P23
NC
N19
SGND_SRDS
P24
SD1_TX[1]
N20
SD1_RX[1]
P25
SD1_TX[1]
N21
SD1_RX[1]
P26
XGND_SRDS
N22
SGND_SRDS
P27
XVDD_SRDS
N23
SVDD_SRDS
P28
NC
N24
MDQ[59]
R1
SVDD_SRDS
N25
MDQ[63]
R2
SGND_SRDS
N26
GVDD
R3
SD1_RX[0]
N27
LVDD
R4
SD1_RX[0]
N28
TSEC1_COL
R5
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
45
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
TSEC3_TXD[2]
R6
NC
T11
TSEC3_GTX_CLK
R7
NC
T12
TSEC3_RXD[3]
R8
VDD
T13
TSEC1_RX_ER
R9
GND
T14
TVDD
R10
VDD
T15
TSEC3_RX_ER
R11
GND
T16
VDD
R12
VDD
T17
GND
R13
GND
T18
VDD
R14
NC
T19
GND
R15
XVDD_SRDS
T20
VDD
R16
XGND_SRDS
T21
GND
R17
SD1_TST_CLK
T22
VDD
R18
SD1_TST_CLK
T23
NC
R19
SVDD_SRDS
T24
SD1_TX[3]
R20
SD1_RX[3]
T25
SD1_TX[3]
R21
SD1_RX[3]
T26
XVDD_SRDS
R22
SVDD_SRDS
T27
XGND_SRDS
R23
SGND_SRDS
T28
SVDD_SRDS
R24
TSEC1_TXD[0]
U1
SGND_SRDS
R25
TSEC1_TXD[1]
U2
SVDD_SRDS
R26
LVDD
U3
SD1_RX[2]
R27
TSEC1_TX_EN
U4
SD1_RX[2]
R28
TSEC1_TXD[6]
U5
TSEC1_GTX_CLK
T1
GND
U6
EC_GTX_CLK125
T2
TSEC1_RX_DV
U7
TSEC1_TX_ER
T3
TSEC1_RXD[3]
U8
TSEC1_CRS
T4
TSEC1_RXD[6]
U9
TSEC1_TXD[7]
T5
TSEC1_RXD[7]
U10
TSEC1_RXD[0]
T6
NC
U11
TSEC1_RXD[1]
T7
VDD
U12
TSEC1_RXD[2]
T8
GND
U13
TSEC1_RXD[4]
T9
VDD
U14
TSEC1_RXD[5]
T10
GND
U15
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 46
Freescale Semiconductor
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
VDD
U16
XVDD_SRDS
V21
GND
U17
SD1_TX[5]
V22
VDD
U18
SD1_TX[5]
V23
NC
U19
SGND_SRDS
V24
SD1_TX[4]
U20
NC
V25
SD1_TX[4]
U21
SD1_PLL_TPA
V26
XGND_SRDS
U22
AGND_SRDS
V27
XVDD_SRDS
U23
SD1_PLL_TPD
V28
SGND_SRDS
U24
NC
W1
SVDD_SRDS
U25
NC
W2
SGND_SRDS
U26
NC
W3
SD1_REF_CLK
U27
NC
W4
SD1_REF_CLK
U28
NC
W5
TSEC1_TXD[2]
V1
NC
W6
TSEC1_TXD[3]
V2
NC
W7
TSEC1_TXD[4]
V3
NC
W8
GND
V4
MSRCID[1]
W9
TSEC1_TXD[5]
V5
SENSEVSS
W10
TSEC1_TX_CLK
V6
SENSEVDD
W11
TSEC1_RX_CLK
V7
NC
W12
NC
V8
NC
W13
NC
V9
NC
W14
NC
V10
NC
W15
NC
V11
NC
W16
NC
V12
NC
W17
NC
V13
NC
W18
NC
V14
NC
W19
NC
V15
SD1_TX[6]
W20
NC
V16
SD1_TX[6]
W21
NC
V17
XVDD_SRDS
W22
NC
V18
XGND_SRDS
W23
NC
V19
SVDD_SRDS
W24
XGND_SRDS
V20
SGND_SRDS
W25
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
47
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
SVDD_SRDS
W26
TEMP_CATHODE
AA3
NC
W27
XGND_SRDS2
AA4
AVDD_SRDS
W28
SD2_TX[3]
AA5
SD2_IMP_CAL_TX
Y1
XVDD_SRDS2
AA6
SGND_SRDS2
Y2
DMA_DDONE[0]
AA7
TEMP_ANODE
Y3
GND
AA8
XGND_SRDS2
Y4
MSRCID[2]
AA9
SD2_TX[3]
Y5
DMA_DREQ[0]
AA10
XVDD_SRDS2
Y6
DMA_DREQ[1]
AA11
MSRCID[0]
Y7
CKSTP_OUT
AA12
MDVAL
Y8
PCI1_STOP
AA13
EC_MDIO
Y9
PCI1_C_BE[1]
AA14
GND
Y10
PCI1_AD[11]
AA15
DMA_DDONE[1]
Y11
PCI1_AD[0]
AA16
DMA_DACK[1]
Y12
GND
AA17
DMA_DACK[0]
Y13
NC
AA18
PCI1_AD[15]
Y14
NC
AA19
PCI1_AD[9]
Y15
SD2_TX[0]
AA20
OVDD
Y16
SD2_TX[0]
AA21
NC
Y17
XGND_SRDS2
AA22
NC
Y18
XVDD_SRDS2
AA23
NC
Y19
SGND_SRDS
AA24
XVDD_SRDS
Y20
SVDD_SRDS
AA25
XGND_SRDS
Y21
SGND_SRDS
AA26
SD1_TX[7]
Y22
SD1_RX[5]
AA27
SD1_TX[7]
Y23
SD1_RX[5]
AA28
SVDD_SRDS
Y24
SVDD_SRDS2
AB1
SD1_RX[4]
Y25
SD2_RX[3]
AB2
SD1_RX[4]
Y26
SGND_SRDS2
AB3
SVDD_SRDS
Y27
SD2_TX[2]
AB4
SGND_SRDS
Y28
TRIG_OUT/READY/QUIESCE
AB5
SGND_SRDS2
AA1
MSRCID[3]
AB6
SD2_RX[3]
AA2
OVDD
AB7
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 48
Freescale Semiconductor
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
PCI1_REQ[0]
AB8
PCI1_DEVSEL
AC13
PCI1_AD[26]
AB9
PCI1_SERR
AC14
OVDD
AB10
PCI1_AD[13]
AC15
PCI1_AD[20]
AB11
GND
AC16
PCI1_AD[19]
AB12
PCI1_AD[5]
AC17
OVDD
AB13
OVDD
AC18
PCI1_PAR
AB14
IRQ[8]
AC19
PCI1_AD[12]
AB15
L1_TSTCLK
AC20
PCI1_AD[8]
AB16
GND
AC21
PCI1_AD[2]
AB17
IRQ[7]
AC22
PCI1_AD[1]
AB18
IRQ[6]
AC23
NC
AB19
SGND_SRDS
AC24
NC
AB20
SGND_SRDS2
AC25
NC
AB21
SVDD_SRDS2
AC26
NC
AB22
SD1_RX[7]
AC27
NC
AB23
SD1_RX[7]
AC28
SGND_SRDS
AB24
SD2_RX[2]
AD1
SD1_RX[6]
AB25
SVDD_SRDS2
AD2
SD1_RX[6]
AB26
SGND_SRDS2
AD3
SGND_SRDS
AB27
XGND_SRDS2
AD4
SVDD_SRDS
AB28
MSRCID[4]
AD5
SD2_RX[2]
AC1
PCI1_REQ[1]
AD6
SGND_SRDS2
AC2
GND
AD7
SGND_SRDS2
AC3
PCI1_AD[30]
AD8
SD2_TX[2]
AC4
OVDD
AD9
TRIG_IN
AC5
PCI1_AD[23]
AD10
OVDD
AC6
OVDD
AD11
EC_MDC
AC7
PCI1_FRAME
AD12
PCI1_GNT[1]
AC8
PCI1_TRDY
AD13
PCI1_AD[25]
AC9
IRQ_OUT
AD14
PCI1_C_BE[3]
AC10
OVDD
AD15
PCI1_AD[21]
AC11
PCI1_AD[10]
AD16
PCI1_AD[18]
AC12
PCI1_C_BE[0]
AD17
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
49
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
GND
AD18
GND
AE23
PCI1_AD[3]
AD19
IRQ[11]/DMA_DDONE3
AE24
OVDD
AD20
SGND_SRDS2
AE25
IRQ[2]
AD21
SVDD_SRDS2
AE26
GPIN[4]
AD22
IRQ[10]/DMA_DACK3
AE27
GPIN[2]
AD23
SD1_IMP_CAL_TX
AE28
SGND_SRDS2
AD24
AGND_SRDS2
AF1
SD2_RX[0]
AD25
SD2_REF_CLK
AF2
SD2_RX[0]
AD26
SGND_SRDS2
AF3
SVDD_SRDS
AD27
SD2_TST_CLK
AF4
SGND_SRDS
AD28
XVDD_SRDS2
AF5
SGND_SRDS2
AE1
UART_CTS[1]
AF6
SD2_REF_CLK
AE2
UART_SOUT[1]
AF7
SGND_SRDS2
AE3
PCI1_AD[29]
AF8
XGND_SRDS2
AE4
PCI1_REQ[4]
AF9
OVDD
AE5
OVDD
AF10
PCI1_GNT[0]
AE6
GND
AF11
PCI1_GNT[4]
AE7
PCI1_AD[17]
AF12
PCI1_AD[31]
AE8
PCI1_IRDY
AF13
PCI1_AD[24]
AE9
GND
AF14
PCI1_AD[22]
AE10
RTC
AF15
PCI1_AD[16]
AE11
IRQ[5]
AF16
PCI1_C_BE[2]
AE12
IRQ[1]
AF17
OVDD
AE13
PCI1_AD[7]
AF18
PCI1_PERR
AE14
IRQ[3]
AF19
PCI1_AD[14]
AE15
OVDD
AF20
CLK_OUT
AE16
GPOUT[4]
AF21
L2_TSTCLK
AE17
GPOUT[0]
AF22
PCI1_AD[6]
AE18
GPIN[5]
AF23
PCI1_AD[4]
AE19
OVDD
AF24
GPIN[7]
AE20
GPOUT[5]
AF25
GPIN[3]
AE21
GPOUT[7]
AF26
OVDD
AE22
OVDD
AF27
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 50
Freescale Semiconductor
Table 9. Pin List—By Pin Number (continued)
Table 9. Pin List—By Pin Number (continued)
Signal
Pin
Signal
Pin
TDO
AF28
CKSTP_IN
AH5
AVDD_SRDS2
AG1
UART_SIN[1]
AH6
SVDD_SRDS2
AG2
UART_SOUT[0]
AH7
SD2_PLL_TPD
AG3
UART_CTS[0]
AH8
SD2_TST_CLK
AG4
GND
AH9
XVDD_SRDS2
AG5
PCI1_REQ[2]
AH10
PCI1_IDSEL
AG6
PCI1_GNT[2]
AH11
UART_SIN[0]
AG7
PCI1_AD[28]
AH12
UART_RTS[0]
AG8
TEST_SEL
AH13
UART_RTS[1]
AG9
AVDD_CORE
AH14
PCI1_REQ[3]
AG10
UDE
AH15
PCI1_GNT[3]
AG11
SYSCLK
AH16
PCI1_AD[27]
AG12
ASLEEP
AH17
IIC2_SCL
AG13
AVDD_PLAT
AH18
IIC2_SDA
AG14
LSSD_MODE
AH19
HRESET_REQ
AG15
AVDD_PCI1
AH20
HRESET
AG16
IIC1_SDA
AH21
IRQ[4]
AG17
TRST
AH22
MCP
AG18
GPOUT[1]
AH23
SRESET
AG19
GPIN[0]
AH24
IRQ[9]/DMA_DREQ3
AG20
GPOUT[3]
AH25
IIC1_SCL
AG21
PCI1_CLK
AH26
IRQ[0]
AG22
TMS
AH27
GND
AG23
TDI
AH28
GPIN[1]
AG24
GPIN[6]
AG25
GPOUT[6]
AG26
GPOUT[2]
AG27
TCK
AG28
SD2_PLL_TPA
AH1
SGND_SRDS2
AH2
SD2_IMP_CAL_RX
AH3
XGND_SRDS2
AH4
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
51
Clocks
5
Clocks
Figure 10 shows the internal distribution of clocks.
e500 Core cfg_core_pll[0:2]
cfg_sys_pll[0:3]
3
4
Core PLL
Device PLL
CCB_clk
÷2
core_clk
6 DDR
6
MCK[0:5] MCK[0:5]
DDR Controller
SYSCLK LSYNC_IN
÷n PCI_CLK
LSYNC_OUT PLL
PCI
LCLK0 LCLK1 LCLK2
LBC
CCB_clk to Rest of the Device
Figure 10. Clock Subsystem Block Diagram
The clock inputs for the MPC8544E are the EC_GTX_CLK125, PCI1_CLK, RTC, SD_REF_CLK/SD_REF_CLK and SYSCLK. The EC_GTX_CLK125 input is used by the eTSEC controller as a reference clock for gigabit Ethernet modes. The PCI1_CLK input are PCI clock input if the PCI controller is configured in asynchronous mode. SD_REF_CLK/SD_REF_CLK are the reference clocks for PCI-Express and SGMII operating modes. SYSCLK is the primary clock input to the device. Table 10 shows how the clock pins should be connected. Table 10. Clock Pin Recommendations Pin Name EC_GTX_CLK125 PCI1_CLK
RTC
Pin Used If any of the eTSECs are used in gigabit mode, connect to a 125 MHz clock.
Pin Not Used Pull high or low through a 2–10 kΩ resistor to LVDD or GND, respectively.
Pull high or low through a 2–10 kΩ resistor to If PCI1 is configured for PCI and isochronous OVDD or GND, respectively. mode, connect to a 16 - 66 MHz clock. If PCI1 is configured for PCI-X and asychronous mode, connect to a 66 - 133 MHz clock. If used, connect to a clock that runs no greater than 1/4 the platform CCB_clk.
Pull high or low through a 2–10 kΩ resistor to OVDD or GND, respectively.
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 52
Freescale Semiconductor
Clocks
Table 10. Clock Pin Recommendations (continued) Pin Name
Pin Used
SD_REF_CLK / SD_REF_CLK
These pins must be connected to GND. If the SerDes is enabled at POR, connect to a clock at the frequency specified per the POR I/O Port Selection.
SYSCLK
5.1
Pin Not Used
This must always be connected to an input clock of 16–133 MHz
System PLL Ratio
The system PLL inputs, shown in Table 11, establish the clock ratio between the SYSCLK input and the platform clock. Table 11. CCB Clock Ratio
5.2
Binary Value of LA[28:31] Signals
CCB:SYSCLK Ratio
Binary Value of LA[28:31] Signals
CCB:SYSCLK Ratio
0000
16:1
1000
8:1
0001
Reserved
1001
9:1
0010
Reserved
1010
10:1
0011
3:1
1011
Reserved
0100
4:1
1100
12:1
0101
5:1
1101
Reserved
0110
6:1
1110
Reserved
0111
Reserved
1111
Reserved
e500 Core PLL Ratio
Table 12 describes the e500 core clock PLL inputs that program the core PLL and establish the ratio between the e500 core clock and the e500 core complex bus (CCB) clock. Table 12. e500 Core to CCB Clock Ratio Binary Value of LBCTL, LALE, LGPL2 Signals
e500 core: CCB Clock Ratio
Binary Value of LBCTL, LALE, LGPL2 Signals
e500 core: CCB Clock Ratio
000
4:1
100
2:1
001
Reserved
101
5:2
010
Reserved
110
3:1
011
3:2
111
7:2
MPC8544E PowerQUICC™ III Bring-up Guide, Rev. 2 Freescale Semiconductor
53
DDR Interface
5.3
Security Controller PLL Ratio
The SEC mode frequency configuration allows for CCB CLK:SEC_CLK ratio of 2:1 or 3:1. Depending on the SEC PLL ratio of 2:1 or 3:1 the serial bit clock frequency of I2C (SCL) can be either one -half or one third of the CCB clock respectively. Table 13. SEC Frequency Ratio Pin Name
Value (Binary)
CCB CLK:SEC CLK
LWE
0
2:11
1
3:12
Notes: 1. In 2:1 mode the CCB frequency must be operating
